JPH07222031A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To improve the quality of a reproduced picture by stabilizing a reference potential with respect to a clamp operation at a special reproduction such as variable speed reproduction with simple circuit configuration, thereby eliminating the fluctuation of brightness at the special reproduction. CONSTITUTION:This reproducing device is provided with a potential insert block 21 inserting a set potential Vr in a prescribed timing of a reproduced brightness signal Sv at special reproduction and a clamp means clamping the setting potential Vr as a reference potential of the reproduced brightness signal Sv. The potential insert block is made up of 1st monostable multivibrator (M.M) 23 selecting an optional point of time for a back porch period, a 2nd M.M 24 setting an output width of the setting potential Vr and a switching circuit SW1 selecting the reproduced brightness signal Sv to the setting potential Vr by an output width t2 only, and the clamp means is made up of a clamp pulse generating block 22, a write processor 10 and a bias correction circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal reproducing apparatus, and more particularly, it is suitable for use in a VTR which records a video signal on a magnetic tape by a helical scan system or reproduces a video signal from the magnetic tape. is there.

[0002]

2. Description of the Related Art Generally, in a VTR which records a video signal on a magnetic tape by a helical scan method or reproduces a video signal from the magnetic tape, two recording / reproducing magnetic heads are provided on a rotating drum for recording / reproducing for 1CH. Head and 2C
As recording and reproducing heads for H, they have rotary heads installed at 180 ° opposite positions. The magnetic tape has an oblique track (1CH track) by the 1CH recording / reproducing head and an oblique track (2CH) by the 2CH recording / reproducing head.
Tracks) will be recorded adjacent to each other.

The respective recording / reproducing heads are set so that the magnetic gaps thereof are different from each other, and when the recording / reproducing head for 1CH has an azimuth angle of + 6 °, for example,
The recording / playback head for 2CH is set to an azimuth angle of -6 °. The azimuth angle is provided to suppress crosstalk from a track adjacent to the track currently being traced.

Normally, the reproduction output of the magnetic head becomes maximum when the magnetic gap and the magnetism from the magnetic tape are orthogonal to each other. However, when the magnetic head is provided with an azimuth angle as described above, an image of the track currently being traced is displayed. The signal can be reproduced at high output, and the reproduction output of the video signal of the adjacent track becomes very small due to the loss due to the azimuth angle (azimuth loss). Therefore, by providing the magnetic head with an azimuth angle, it is possible to effectively suppress crosstalk from adjacent tracks.

Further, the magnetic tape has a 1CH track by a 1CH recording / reproducing head having an azimuth angle of + 6 ° and a −
2C with 2CH recording / playback head with 6 ° azimuth angle
Since the H tracks are recorded adjacent to each other, the track having the reverse azimuth angle is interposed between the two tracks having the same azimuth angle, and as a result, the track having the reverse azimuth angle is the above-mentioned two tracks. It becomes a guard band for tracks with the same azimuth angle, and it is possible to suppress interference between tracks with the same azimuth angle.

By providing different azimuth angles in the magnetic gaps of the recording and reproducing heads of 1CH and 2CH in this way, it is advantageous in terms of C / N (ratio of carrier output C to noise) and tape consumption. It is possible to reduce the running cost, downsize the device, and increase the recording time.

[0007]

A helical scan type VTR using a rotary head having a pair of magnetic heads having an azimuth angle or more magnetic heads has only a track suitable for the azimuth angle due to its azimuth loss. , It is possible to pick up the reproduction signal from the magnetic tape.
There is no problem when the magnetic tape runs at 1 × speed during normal reproduction, but during special reproduction such as variable speed reproduction, tracks that do not necessarily match the azimuth angle are also scanned. In this case, a missing portion of the reproduced signal occurs due to the above-mentioned azimuth loss, and if the reproduced signal is demodulated as it is, the video signal is naturally lost and the portion becomes noise.

Further, in the VTR, after the reproduction video signal is subjected to deviation adjustment (to adjust the white peak level), a portion of the video signal, for example, the potential of the front porch section in the horizontal blanking period. Is clamped, and the so-called clamp operation (carrier adjustment) is performed with the potential as a reference potential (for example, black level potential) of the video signal.

However, when noise is superimposed on the portion to be clamped during variable speed reproduction or the like, the noise is clamped, so the reference potential becomes unstable and the quality of the reproduced image deteriorates. . Therefore, conventionally, the clamp operation is not performed during special reproduction such as variable speed reproduction.

However, if the loss of the video signal is too long, the reference potential fluctuates, and when the normal video signal is input next, the clamp operation is restarted from the potential different from the true value. At this time, there is a problem in that the brightness also changes and the quality of the reproduced image deteriorates.

Therefore, the following method has been considered as a method for solving the above problem. That is, generally, in a helical scan type consumer VTR in which a magnetic gap of a magnetic head is provided with an azimuth angle, there are a plurality of modes related to tape speed in the same format, and accordingly, track widths are different. The magnetic head corresponding to the track width is mounted. That is, the magnetic head used differs depending on the mode, and the azimuth angle also changes accordingly.

Taking advantage of this difference in azimuth angle, a magnetic head having an azimuth angle with little azimuth loss is used in another mode, and the rotary heads are switched and used when scanning a track adapted to a different azimuth angle. By doing so, it is possible to prevent the video signal from being lost.

However, in the case of this method, the number of types of control signals handled in the signal processing increases, and the number of necessary circuits also increases. As a result, the structure of the VTR is complicated and the size of the VTR is increased, and the manufacturing cost is increased.

The present invention has been made in view of the above problems, and an object of the present invention is to stabilize a reference potential relating to a clamp operation during special reproduction such as variable speed reproduction with a simple circuit configuration. Therefore, it is another object of the present invention to provide a video signal reproducing apparatus capable of eliminating the fluctuation of the luminance at the time of special reproduction and improving the quality of reproduced image.

[0015]

SUMMARY OF THE INVENTION The present invention provides a video signal reproducing apparatus for performing normal reproduction or variable speed reproduction of a video signal recorded on a recording medium by selectively switching between a normal mode and a speed change mode. Video signal reproduced at the time of selection (for example, reproduction luminance signal Sv)
The potential inserting means 21 for inserting the variable speed reproduction clamp potential Vr and the clamping means for clamping the variable speed reproduction clamp potential Vr as the reference potential of the video signal Sv at the time of variable speed reproduction are provided.

In this case, the insertion point of the variable speed reproduction clamp potential Vr by the potential inserting means 21 can be set to the back porch section Bp in the horizontal blanking period Hb.

Further, the potential inserting means 21 is a selecting means 23 for selecting an arbitrary time point in the back porch section Bp in the horizontal blanking period Hb, and a setting means 24 for setting the output width t2 of the variable speed reproduction clamp potential Vr. And a switching means SW1 for switching the reproduced video signal Sv to the variable speed reproduction clamp potential Vr by the output width t2 set by the setting means 24 from the time point selected by the selection means 23.
You may make it comprise by providing.

In addition to the above construction, the potential inserting means 2
The first selection means SW2 may be provided to disable the operation of the switching means SW1 during normal reproduction and enable the operation of the switching means SW1 during variable speed reproduction.

Then, the potential inserting means 2 having the above structure
1 can be inserted and connected in front of the A / D converter 4 incorporated in the time base collector.

On the other hand, the clamp means is outputted within the insertion period t2 of the variable speed reproduction clamp potential Vr based on the normal reproduction clamp pulse P for performing the normal pedestal clamp, and the variable speed reproduction clamp potential Vr is outputted. Clamp pulse generating means (27, 28) for generating the clamp pulse Sm4 for variable speed reproduction for extracting the variable speed and the clamp pulse P for normal reproduction at the time of normal reproduction, and the clamp pulse generating means (27, 28 at the time of variable speed reproduction). 28)
The selection means SW3 for selecting the variable speed reproduction clamp pulse Sm4 from may be provided.

The clamp pulse generating means (2
7, 28) and selecting means SW3 are inserted and connected between the timing generator 3 incorporated in the time base collector and the write processor 10, and these clamp pulse generating means (27, 28), selecting means SW3, write processor 10 and The clamp means can be configured by the bias correction circuit 12 that corrects the bias of the video signal based on the clamp error signal Vc from the writing processor 10.

Further, the present invention is a video signal reproducing apparatus for performing normal reproduction or variable speed reproduction of a video signal recorded on a recording medium by selectively switching between the normal mode and the speed change mode, and is reproduced when the speed change mode is selected. Signal smoothing means 31 for smoothing the signal level of a predetermined video signal (for example, reproduction luminance signal Sv) in a front porch section Fp of the horizontal blanking period Hb, and the signal level smoothed by this signal smoothing means 31 Clamping means for clamping the signal Sv as a reference signal is provided.

In this case, the signal smoothing means 31 may be inserted and connected before the A / D converter 4 incorporated in the time base collector.

Further, the signal smoothing means 31 is provided with a selecting means 36 for activating smoothing of the signal level in a predetermined period in the front porch section Fp of the horizontal blanking period Hb of the video signal Sv during variable speed reproduction. Good.

On the other hand, the signal level smoothed by the signal smoothing means 31 based on the normal reproduction clamp pulse P for performing the normal pedestal clamp is applied to the clamp means regardless of the normal reproduction and the variable speed reproduction. Video signal S
It may be configured to be clamped as the reference potential of v.

The clamp means is used as a write processor 10 incorporated in the time base collector and a clamp error signal V from the write processor 10.
The bias correction circuit 12 can correct the bias of the video signal Sv based on c.

[0027]

In the video signal reproducing apparatus according to the present invention, the normal reproduction or the variable speed reproduction of the video signal recorded on the recording medium is performed by selectively switching the normal mode or the variable speed mode. Reproduced video signal (for example, reproduction luminance signal S
In v), the variable-speed reproduction clamp potential Vr is inserted at the predetermined timing by the potential inserting means 21.

Then, at the time of variable speed reproduction, the clamp potential Vr for variable speed reproduction is changed to the video signal Sv by the clamp means.
Will be clamped as the reference potential.

Therefore, even when the video signal is lost due to the azimuth loss during variable speed reproduction, and the noise component due to the lack is superimposed on the video signal Sv, particularly in the clamp section by the clamp means, the clamping operation by the clamp means is performed. In the previous stage, since the variable speed reproducing clamp potential Vr is inserted by the potential inserting means 21 at a predetermined timing for clamping by the clamping means in the video signal Sv, the variable speed reproducing clamp potential Vr is clamped by the clamping means. Can be clamped as a reference potential.

As a result, the reference potential relating to the clamp operation during special reproduction such as variable speed reproduction can be stabilized, and the fluctuation in luminance during special reproduction can be eliminated, and as a result, the image quality of the reproduced image can be improved. Can be improved.
Further, if there is a brightness change during special reproduction, the viewer watching the reproduced image will be very tired, but in the video signal reproduction device according to the present invention, the brightness change during special reproduction will occur. Since it is improved, it also has a health effect of suppressing eye fatigue of the viewer.

When the insertion point of the variable speed reproduction clamp potential Vr by the potential inserting means 21 is set to the back porch section Bp in the horizontal blanking period Hb, there is no influence on the color synchronization signal (color burst signal).
It is possible to avoid the inconvenience that the quality of the color is deteriorated by the clamp potential Vr.

As the potential inserting means 21, a selecting means 23 for selecting an arbitrary time point in the back porch section Bp in the horizontal blanking period Hb and a setting means 24 for setting the output width t2 of the variable speed reproduction clamp potential Vr. And the switching means S for switching the reproduced video signal Sv to the variable speed reproduction clamp potential Vr by the output width t2 set by the setting means 24 from the time point selected by the selection means 23.
In the case where W1 is provided, the selection means 23 first causes the horizontal blanking period H of the video signal Sv.
An arbitrary time point in the back porch section Bp in b is selected, and the setting means 24 sets the output width t2 of the variable speed reproduction clamp potential Vr.

Then, the switching means SW1 switches from the time point selected by the selection means 23 to the variable-speed reproduction clamp potential Vr by the output width t2 set by the setting means 24, whereby the video signal Sv The variable speed reproduction clamp potential Vr is inserted into the back porch section Bp in the horizontal blanking period Hb.

In this case, the variable-speed reproduction clamp potential Vr can be inserted in the back porch section Bp in the horizontal blanking period Hb of the reproduced video signal Sv with a simple circuit structure, and the luminance fluctuation during special reproduction can be suppressed. It is possible to realize simplification of the configuration of the reproducing system for improvement.

In addition to the above structure, the potential inserting means 2
In the case where the second selecting means SW2 for invalidating the operation of the switching means SW1 during the normal reproduction and for enabling the operation of the switching means SW1 during the variable speed reproduction is provided in FIG. 1, first, during the normal reproduction, Second selection means SW
2, the operation of the switching means SW1 is invalidated, and the video signal in which the variable speed reproduction clamp potential Vr is not inserted in the back porch section Bp in the horizontal blanking period Hb,
That is, the reproduced video signal Sv itself is selected. On the other hand, during variable speed reproduction, the operation of the switching means SW1 becomes effective by the second selecting means SW2,
Back porch section B in the horizontal blanking period Hb
The video signal Sv having the variable speed reproduction clamp potential Vr inserted in p is selected.

Accordingly, the clamp potential Vr for variable speed reproduction is not inserted during normal reproduction,
It is possible to avoid the inconvenience that the quality of the video signal is deteriorated during normal reproduction.

Further, the electric potential inserting means 21 having the above structure.
, Is inserted and connected in the preceding stage of the A / D converter 4 incorporated in the time base collector, the variable speed reproduction clamp potential Vr is inserted into the video signal Sv before digital conversion using an analog circuit. Therefore, the variable-speed reproduction clamp potential Vr can be inserted into the video signal Sv with a simple circuit configuration.

At the input stage of the time base collector, the variable speed reproduction clamp potential Vr is inserted, and the clamp means performs the clamp operation based on the clamp potential Vr. D
The converter 4 is supplied with the video signal Sv whose reference potential (bias level) is stabilized, and there is no time deviation such as jitter or phase delay from this time base collector, and the bias level is The stabilized video signal Sv is taken out.

Further, based on the normal reproduction clamp pulse P for performing the normal pedestal clamp, the clamp means is outputted within the insertion period t2 of the variable speed reproduction clamp potential Vr to generate the variable speed reproduction clamp potential Vr. Clamp pulse generating means (27, 28) for generating the clamp pulse Sm4 for variable speed reproduction for extracting the variable speed and the clamp pulse P for normal reproduction at the time of normal reproduction, and the clamp pulse generating means (27, 28 at the time of variable speed reproduction). 28)
In the case where the selection means SW3 for selecting the variable speed reproduction clamp pulse Sm4 is provided, first, during the normal reproduction, the selection means SW3 selects the normal reproduction clamp pulse P for performing the normal pedestal clamp. , The normal pedestal clamp is performed on the video signal Sv by the normal reproduction.

On the other hand, during variable speed reproduction, the clamp pulse generation means (27, 28) outputs the variable speed reproduction clamp potential Vr within the insertion period t2 based on the normal reproduction clamp pulse P. The variable speed reproduction clamp pulse Sm4 for extracting the variable speed reproduction clamp potential Vr is generated, and the variable speed reproduction clamp pulse Sm4 is further selected by the selection means SW3. At this time, since the clamp reproduction potential Vr for variable speed reproduction is inserted in the video signal Sv during variable speed reproduction, the clamp potential Vr is extracted by this clamp means, and the clamp potential Vr is converted to the video signal Sv. Will be clamped as the reference potential.

As described above, the normal pedestal clamp is performed during the normal reproduction, and the clamp potential Vr inserted by the potential inserting means 21 is clamped as the reference potential during the variable speed reproduction. For,
It is possible to stabilize the reference potential related to the clamp operation during special reproduction such as variable speed reproduction, it is possible to eliminate the fluctuation in luminance during special reproduction, and as a result, it is possible to improve the image quality of the reproduced image. .

Further, the clamp pulse generating means (2
7, 28) and selecting means SW3 are inserted and connected between the timing generator 3 incorporated in the time base collector and the write processor 10, and these clamp pulse generating means (27, 28), selecting means SW3, write processor 10 and In the case where the clamp means is constituted by the bias correction circuit 12 that corrects the bias of the video signal Sv based on the clamp error signal Vc from the write processor 10, first, during the normal reproduction, the write processor 10 makes the above selection. Based on the normal reproduction clamp pulse P selected by the means SW3, the signal level of the front porch section Fp in the predetermined period of the video signal Sv, for example, the horizontal blanking period Hb is extracted,
The clamp error signal Vc is supplied to the bias correction circuit 12.

The bias correction circuit 12 corrects the bias of the video signal Sv based on the clamp error signal Vc from the writing processor 10. by this,
The video signal Sv is clamped by shifting the entire signal level so that the signal level in the front porch section Fp becomes the pedestal potential Vp.

On the other hand, at the time of variable speed reproduction, in the writing processor 10, the variable speed reproduction inserted into the video signal Sv by the potential inserting means 21 based on the variable speed reproduction clamp pulse Sm4 selected by the selecting means SW3. Clamp potential Vr is extracted and clamp error signal Vc
Is supplied to the bias correction circuit 12. The bias correction circuit 12 corrects the bias of the video signal Sv based on the clamp error signal Vc from the writing processor 10. As a result, the video signal Sv is clamped by shifting the entire signal level so that the variable speed reproduction clamp potential Vr becomes the pedestal potential Vp.

As described above, the normal pedestal clamp is performed during the normal reproduction, and the clamp potential Vr inserted by the potential inserting means 21 during the variable speed reproduction.
Will be clamped as the reference potential, so the reference potential related to the clamp operation during special playback such as variable speed playback can be stabilized, and the fluctuation in brightness during special playback can be eliminated. The quality of reproduced image can be improved.

Further, in the video signal reproducing apparatus according to the present invention, the normal reproduction or the variable speed reproduction of the video signal recorded on the recording medium is performed by selectively switching the normal mode or the speed changing mode. The signal level of the reproduced video signal (for example, the reproduction luminance signal Sv) is smoothed by the signal smoothing means 31 for a predetermined period in the front porch section Fp of the horizontal blanking period Hb. Then, the clamp means clamps the smoothed signal level as the reference potential of the video signal Sv.

In this case, even when a video signal is lost due to azimuth loss during variable speed reproduction and a noise component due to the loss is superimposed on the video signal Sv particularly in the clamp section by the clamp means, the clamp operation by the clamp means is performed. In the previous stage, the signal smoothing means 31 suppresses the potential change in the section Fp to a low level in the front porch section Fp of the horizontal blanking period Hb clamped by the clamping means in the video signal Sv.
The clamp means can clamp the potential whose change is suppressed low as the reference potential.

As a result, the reference potential related to the clamp operation during special reproduction such as variable speed reproduction can be stabilized, and the fluctuation in luminance during special reproduction can be eliminated, and as a result, the image quality of the reproduced image can be improved. Can be improved.

When the signal smoothing means 31 is inserted and connected in the preceding stage of the A / D converter 4 incorporated in the time base collector, the horizontal smoothing is performed especially for the video signal Sv before digital conversion. The signal level in the front porch section Fp in the ranking period Hb can be smoothed, and the signal level in the front porch section Fp can be smoothed with a simple circuit configuration.

At the input stage of the time base collector, the signal level of the front porch section Fp is smoothed, and the clamping operation is performed by the clamping means based on the smoothed signal level. Therefore, the video signal Sv whose reference potential (bias level) is stabilized is supplied to the A / D converter 4, and a time deviation such as jitter or phase delay is generated from this time base collector. The video signal Sv which is not present and whose bias level is stabilized is taken out.

Further, in the case where the signal smoothing means 31 is provided with the selecting means 36 for validating the smoothing of the signal level for the predetermined period in the front porch section Fp of the horizontal blanking period Hb of the video signal Sv during the variable speed reproduction. First, during normal reproduction, the signal level smoothing process by the signal smoothing means 31 is not performed, and the reproduced video signal Sv itself is selected. On the other hand, during variable speed reproduction, the smoothing process of the signal level by the signal smoothing unit 31 is enabled by the selecting unit 36, and the front porch section F of the horizontal blanking period Hb.
The video signal S whose signal level at p is smoothed
v will be selected.

In the above structure, the clamp means is smoothed by the signal smoothing means 31 based on the normal reproduction clamp pulse P for performing the normal pedestal clamp regardless of the normal reproduction and the variable speed reproduction. In the case where the signal level is clamped as the reference potential of the video signal Sv, first, during the normal reproduction, the signal level smoothing process is not performed by the signal smoothing means 31, and the reproduced video signal is obtained. The signal level in the front porch section Fp of the horizontal blanking period Hb of Sv itself is extracted, and the signal level is clamped as the reference potential of the video signal Sv. On the other hand, during variable speed reproduction, the signal level of the video signal Sv in the front porch section Fp is smoothed by the signal smoothing means 31, the smoothed signal level is extracted, and the smoothed signal level is It will be clamped as the reference potential of the video signal Sv.

Then, the clamp means is used as a write processor 10 incorporated in the time base collector and a clamp error signal V from the write processor 10.
In the case of the bias correction circuit 12 that corrects the bias of the video signal Sv based on c, first, in the normal reproduction, the write processor 10 horizontally detects the horizontal direction of the video signal Sv based on the normal reproduction clamp pulse P. Front porch section Fp in the blanking period Hb
Is extracted and supplied to the bias correction circuit 12 as a clamp error signal Vc.

The bias correction circuit 12 corrects the bias of the video signal Sv based on the clamp error signal Vc from the writing processor 10. As a result, the entire signal level is shifted and clamped so that the signal level in the front porch section Fp becomes the pedestal potential.

On the other hand, during variable speed reproduction, the write processor 10 also extracts the signal level smoothed by the signal smoothing means 31 based on the normal reproduction clamp pulse P and biases it as the clamp error signal Vc. It is supplied to the correction circuit 12. The bias correction circuit 12 corrects the bias of the video signal Sv based on the clamp error signal Vc from the writing processor 10. As a result, the entire signal level is shifted and clamped so that the smoothed signal level becomes the pedestal potential.

In any of these configurations, the normal pedestal clamp is performed during normal reproduction, and the signal level smoothed by the signal smoothing means 31 is clamped as the reference potential during variable speed reproduction. Therefore, it is possible to stabilize the reference potential related to the clamp operation during special playback such as variable speed playback, and it is possible to eliminate the variation in brightness during special playback, and as a result, improve the image quality of the playback image. Can be made.

[0057]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments in which the video signal reproducing apparatus according to the present invention is applied to a part of a TBC (time base collector) mounted on a VTR which records and reproduces a video signal on a magnetic tape by a helical scan method. (Hereinafter, simply referred to as a reproducing apparatus according to the first embodiment and a reproducing apparatus according to the second embodiment) will be described with reference to FIGS. 1 to 4.

As one of the functions of this TBC, the reproduced video signal from the magnetic tape reproduced via the rotary head is temporarily and regularly stored in a storage device (for example, a field memory), and this is regularly stored. By taking out the tape, it has a function of eliminating a time deviation such as a jitter or a phase delay which occurs due to running of the tape or uneven rotation of the motor.

In the description of these embodiments, mainly the signal processing relating to the luminance signal of the video signal is mainly described, but in addition to this, there is another signal processing process of the chroma signal system, which is also included. It goes without saying that the TBC operates as a TBC. However, the color signal itself does not need to be clamped because it is superimposed on the luminance signal.

First, the reproducing apparatus according to the first embodiment is shown in FIG.
As shown in, REF supplied to the first input terminal φ1
A reference synchronization signal extraction circuit 1 for extracting a signal of a required timing from the video signal Svr and outputting it as a reference synchronization signal S1, and a reproduction luminance signal S supplied to a second input terminal φ2.
A sync signal extraction circuit 2 for extracting a signal (horizontal sync signal, vertical sync signal, etc.) of a required timing from v and outputting it as a sync signal S2, and a reference sync signal S1 and a sync signal extraction from the reference sync signal extraction circuit And a timing generator 3 for selecting or generating a timing signal to be actually used in the current state based on the synchronization signal S2 from the circuit 2.

Specifically, the timing generator 3 is
A write clock Pw and a write address update signal Sw are generated based on the sync signal S2 from the sync signal extraction circuit 2, and a read clock Pr and a read address are updated based on the reference sync signal S1 from the reference sync signal extraction circuit 1. The signal Sr is generated.

Further, this reproducing apparatus has the second input terminal φ.
The reproduction luminance signal Sv supplied to 2 is digitally converted to 8
A / D converter 4 for converting into a digital luminance signal Dv having a bit or 9-bit configuration, and a RAM for storing the digital luminance signal Dv from this A / D converter 4 as a parallel signal having an 8-bit or 9-bit configuration Field memory 5 consisting of a shift register and this field memory 5
And a D / A converter 6 that converts the digital luminance signal Dv read from the analog signal into an analog luminance signal Sv. The luminance signal Sv output from the D / A converter 6 is output via the buffer circuit 7 to the output terminal φ.
will be taken out.

Further, between the second input terminal φ2 and the A / D converter 4, a coupling capacitor 8 for removing a DC noise component from the reproduction luminance signal Sv supplied to the second input terminal φ2 is provided. A voltage follower circuit 9 that amplifies the reproduction luminance signal Sv from which the DC noise is removed by the coupling capacitor 8 with a gain of approximately 1 is connected.

The A / D converter 4 digitally converts the reproduction luminance signal Sv based on the timing signal St1 from the writing processor 10, and the D / A converter 4
Is the timing signal St from the read processor 11.
Based on 2, the digital luminance signal Dv from the field memory 5 is converted into analog.

Based on the write clock Pw from the timing generator 3, the write processor 10 outputs A /
The timing signal St1 to the D converter 4 is generated, and the digital luminance signal Dv from the A / D converter 4 is supplied to the field memory 5. This field memory 5
Updates the write address based on the write address update signal Sw from the timing generator 3, and sequentially writes the digital luminance signal Dv supplied via the write processor 10. Further, the field memory 5 updates the read address based on the read address update signal Sr from the timing generator 3,
The digital brightness signal Dv is sequentially read.

The write processor 10 also extracts the digital value of the digital luminance signal Dv from the A / D converter 4 based on the output timing of the input clamp pulse Pc, and uses this digital value as the clamp error voltage. The signal Vc is supplied to the bias correction circuit 12 described later.

On the other hand, the read processor 11 sequentially outputs the digital luminance signal Dv from the field memory 5 D / V based on the read clock Pr from the timing generator 3.
The timing signal St2 is supplied to the A converter 6 and the timing signal St2 to the D / A converter 6 is generated based on the read clock Pr.

That is, in this reproducing apparatus, the digital luminance signal Dv from the A / D converter 4 is converted into the reproducing luminance signal S.
The digital luminance signal D written in the field memory 5 based on the write clock Pw generated based on the sync signal S2 of v, and further stored in the field memory 5.
v is read based on the read clock Pr generated based on the reference synchronization signal S1, and the read digital luminance signal Dv from the field memory 5 is read by D /
Since the A converter 6 is configured to sequentially convert the analog luminance signal Sv, the luminance signal Sv extracted from the output terminal φout becomes a clean signal without time deviation such as jitter and phase delay.

Then, the luminance signal Sv taken out from the output terminal φout is thereafter combined with the chroma signal from the chroma signal processing system which is a separate system, and the sync signal is replaced to restore a beautiful video signal. .

A bias correction circuit 12 is connected to this reproducing apparatus. This bias correction circuit 12
Has a inverting input terminal to which the clamp error voltage signal Vc from the write processor 10 is input, and a non-inverting input terminal having a predetermined potential, for example, a pedestal potential (about 0.04V) Vp.
Is provided, and the output voltage of the integrator 13 is supplied to the previous stage of the voltage follower circuit 9 and added to the signal of the reproduction luminance signal Sv for a predetermined period. ing. That is, the reproduction luminance signal is clamped so that the signal level in the predetermined period becomes the pedestal potential.

In the reproducing apparatus according to the first embodiment, during the special reproduction such as the variable speed reproduction, the electric potential inserting block 21 for inserting the constant set electric potential Vr in the predetermined period of the reproducing luminance signal Sv and this electric potential. It is configured to include a clamp pulse generation block 22 that generates a clamp pulse whose clamp timing is the insertion period of the set potential Vr inserted in the insertion block 21.

The potential insertion block 21 is inserted and connected between the second input terminal φ2 to which the reproduction luminance signal Sv is supplied and the coupling capacitor 8, and the clamp pulse generation block 22 is connected to the timing generator 3 and the writing. It is inserted and connected to the processor 10.

Explaining the configuration of each block 21 and 22, the potential inserting block 21 has a third input terminal φ3.
A first monostable multivibrator (hereinafter referred to as a first MM) 23 that starts oscillation based on the rising edge of the burst signal Sb supplied to the first M.M. M2
A second monostable multivibrator (hereinafter referred to as the second monostable multivibrator) which starts oscillation based on the fall of the output signal Sm1 from
M. 24) and this second M.M. A first switching circuit SW1 that selectively switches the reproduction luminance signal Sv from the second input terminal φ2 and the set potential Vr based on the output signal Sm2 from the M24, and the fourth input terminal φ.
Based on the signal Sh indicating the normal mode / special reproduction mode, which is supplied to No. 4, the reproduction luminance signal Sv from the second input terminal φ2 and the output signal of the first switching circuit SW1 are selectively switched. It has a switching circuit SW3.

The first M. M23 is the third input terminal φ3
Is an up-edge operation type CMOS monostable multivibrator which starts oscillation at the moment when the burst signal Sb supplied to the signal rises from a low level to a high level. For example, the CR time constant is 0.7
A pulse signal Sm1 having a pulse width t1 corresponding to the product of 2 is output. In this embodiment, the output pulse signal Sm1 rises at the moment of rising of the burst signal Sb and rises within the back porch section Bp of the reproduction luminance signal Sv in the horizontal blanking period Hb as shown in FIG. The CR time constant is set by the externally attached capacitor and resistor so that the pulse width t1 decreases.

The second M.S. The M24 is the first M.M. M
23 is a down-edge operation type CMOS monostable multivibrator that starts oscillation at the moment when the pulse signal Sm1 output from H.23 falls from a high level to a low level. A pulse signal Sm2 having a pulse width t2 corresponding to a value obtained by multiplying the CR time constant of the resistor by 0.72, for example, is output. In this example,
The output pulse signal Sm2 is, as shown in FIG. A relatively small pulse width t2 that rises at the moment of the fall of the pulse signal Sm1 from M23 and falls within the back porch section Bp of the reproduction luminance signal Sv in the horizontal blanking period Hb,
A CR time constant is set by an externally attached capacitor and resistor.

Here, the burst signal Sb is a trigger pulse generated based on the horizontal synchronizing signal HD of the reproduction luminance signal Sv as shown in FIG. 2, and in this example, for example, the horizontal synchronization of the reproduction luminance signal Sv is performed. For a predetermined time from the fall of the signal HD, for example, the front porch section F in the horizontal blanking period Hb of the reproduction luminance signal Sv.
It is a trigger pulse that rises in p.

The signal Sh indicating the normal mode / special reproduction mode supplied to the fourth input terminal φ4 is the operation key indicating the normal reproduction on the operation panel of the VTR equipped with this reproducing apparatus. In this case, the signal level becomes, for example, a low level, and has a signal waveform in which the signal level becomes a high level when an operation key on the operation panel indicating a variable speed reproduction such as fast forward reproduction or fast rewind reproduction is operated. .

The first switching circuit SW1 has a movable contact 25c connected to one fixed contact (second fixed contact) 26b of the second switching circuit SW2 and a second contact to which a reproduction luminance signal Sv is supplied. It has a first fixed contact 25a connected to the input terminal φ2 and a second fixed contact 25b to which the set potential Vr is applied. M2
4, the movable contact 25c and the first fixed contact 25a are electrically connected to each other while the pulse signal Sm2 from the second M.4 is low. Pulse signal Sm2 from M24
Is high, the movable contact 25c and the second contact
The fixed contact 25b is electrically connected.

In this embodiment, the set potential Vr is set to a signal level which is about 50% of the maximum field signal level (white peak level) Lp in the reproduction luminance signal (FIG. 2). (See enlarged view of insertion).

On the other hand, the second switching circuit 24 is
A movable contact 26c connected to the non-inverting input terminal side (more precisely, one electrode of the coupling capacitor 8) of the voltage follower circuit 9 leading to the input side of the / D converter 4 and the second input terminal φ2. And the second fixed contact 26b connected to the movable contact 25c in the first switching circuit SW1 and supplied to the fourth input terminal φ4 in the normal mode / When the signal Sh indicating the special reproduction mode is, for example, low level and the normal reproduction is selected, the movable contact 26c and the first fixed contact 26a are electrically connected, and the signal Sh indicating the normal mode / special reproduction mode is set. Is at a high level and special reproduction is selected, the movable contact 26c and the second fixed contact 26b are electrically connected.

Next, the clamp pulse generation block 22
Is a third monostable multivibrator (hereinafter, referred to as a third MM) 27 which starts oscillation based on the rise of a normal clamp pulse P for performing a normal pedestal clamp from the timing generator 3. And this third M.M. A fourth monostable multivibrator (hereinafter, referred to as a fourth MM) 28 that starts oscillation based on the fall of the output signal Sm3 from the M27, and the fourth M.M. M2
8 output signal Sm4 and the above-mentioned normal clamp pulse P
And a third switching circuit SW3 for selectively outputting to the write processor 10 as a clamp pulse Pc.

The third M.M. M28 is an up-edge operation type CMOS monostable multivibrator that starts oscillation at the moment when the normal clamp pulse P rises from a low level to a high level. It rises with the oscillation and, for example, an external capacitor (not shown). A pulse signal Sm3 having a pulse width t3 corresponding to a value obtained by multiplying the CR time constant of the resistance by 0.72 is output.
In this embodiment, the output pulse signal Sm3
However, as shown in FIG. 2, when the normal clamp pulse P rises, it rises and the horizontal blanking period Hb
At the back porch section Bp of the reproduction luminance signal Sv
Among them, more specifically, the second M.M. The CR time constant of the externally attached capacitor and resistor is set so that the pulse width t3 falls within the pulse width t2 of the pulse signal Sm2 output from M24.

The fourth M.S. M28 is a third M.I. M
A down-edge operation type CMOS monostable multivibrator that starts oscillation at the moment when the pulse signal Sm3 output from 27 falls from a high level to a low level, rises with the oscillation, and is, for example, an external capacitor (not shown) And a pulse signal Sm4 having a pulse width t4 corresponding to the CR time constant of the resistor multiplied by 0.72, for example. In this example,
The output pulse signal Sm4 is, as shown in FIG. The pulse signal Sm3 from the M27 rises at the falling moment and within the back porch section Bp of the reproduction luminance signal Sv in the horizontal blanking period Hb, more specifically, the second M.M. The CR time constant of the externally attached capacitor and resistor is set so that the pulse width t4 of the pulse signal Sm2 output from M24 falls within a relatively small pulse width t4.

The third switching circuit SW3 includes a movable contact 29c connected to the input terminal side of the clamp pulse Pc in the write processor 10 and a fourth M.V. M2
8 has a first fixed contact 29a connected to the output side and a second fixed contact 29b connected to the terminal of the timing generator 3 to which the normal clamp pulse P is output. When the signal Sh indicating the normal mode / special reproduction mode supplied to the input terminal φ4 of
When the normal reproduction is selected, the movable contact 29c and the second
Is electrically connected to the fixed contact 29b of the normal mode /
When the signal Sh indicating the special reproduction mode is at a high level and special reproduction is selected, the movable contact 29c and the first fixed contact 29a are electrically connected.

Next, the operation of the reproducing apparatus according to the first embodiment will be described with reference to the timing chart of FIG.

First, when the normal reproduction mode is selected by operating the operation key indicating the normal reproduction on the operation panel, the signal Sh indicating the normal mode / special reproduction mode supplied to the fourth input terminal φ4 is , As a low level signal. Therefore, the second in the potential insertion block 21
Switching circuit SW2 of low-level normal mode /
Based on the signal Sh indicating the special reproduction mode, the first fixed contact 26a and the movable contact 26c are electrically connected, and the third switching circuit SW3 in the clamp pulse generation block 22 outputs the low-level signal Sh. Based on this, the second fixed contact 29b and the movable contact 29c are electrically connected. In the second switching circuit SW2, the first fixed contact 26a and the movable contact 26
By electrically connecting with c, the operation by the first switching circuit SW1 becomes invalid.

The reproduction luminance signal Sv input to the second input terminal φ2 based on the normal reproduction at 1 × speed is sequentially supplied to the A / D converter 4 based on the timing signal St1 from the writing processor 10. It is converted into a digital luminance signal Dv, and is further written into the field memory 5 through the write processor 10 based on the input of the write clock Pw to the write processor 10 and the input of the update signal Sw of the write address to the field memory 5.

At this time, the write processor 10
The normal clamp pulse P is supplied as the clamp pulse Pc of this time through the switching circuit SW3 of, and the front porch section Fp in the horizontal blanking period Hb.
Signal level is taken out and the clamp error voltage Vc
Is supplied to the bias correction circuit 12.

The bias correction circuit 12 outputs an output signal (DC voltage signal) obtained by integrating the difference between the clamp error voltage Vc from the write processor 10 and the pedestal potential Vp.
Output VDC. The output signal VDC is supplied to the preceding stage of the voltage follower circuit 9 connected to the preceding stage of the A / D converter 4, and the reproduced luminance signal Sv after the field next to the reproduced luminance signal Sv relating to the field extracted this time.
The entire signal level is shifted so that the signal level of the front porch Fp at v becomes the pedestal potential Vp. That is, it will be clamped.

At the stage where the digital data has been written up to almost the intermediate address of the field memory 5, the digital luminance signal Dv in the field memory 5 receives the read clock Pr to the read processor 11 and the read address to the field memory 5. Based on the input of the update signal Sr, the read processor 11 sequentially reads from the head address. Simultaneously with this reading, the digital luminance signal Dv is written to the addresses after the intermediate address in the field memory 5.

The digital luminance signal Dv read via the read processor 11 is read by the read processor 11
D / A converter 6 based on the timing signal St2 from
Is sequentially converted into an analog luminance signal Sv. The brightness signal Sv is taken out from the output terminal φout via the buffer circuit 7 in the next stage.

After a series of these operations are performed, the reproduction luminance signal S supplied to the second input terminal φ2 in the normal reproduction is supplied.
v is taken out from the output terminal φout as a clean luminance signal Sv having no time deviation such as jitter and phase delay.

Next, when the special reproduction mode is selected by operating the operation key for special reproduction such as variable speed reproduction on the operation panel, the normal mode / special reproduction mode supplied to the fourth input terminal φ4. Is input as a high level signal. Therefore, the potential insertion block 21
In the second switching circuit SW2 in, the second fixed contact 26b and the movable contact 26c are electrically connected to each other based on the signal Sh indicating the high level normal mode / special reproduction mode, and the clamp pulse generation is performed. Block 22
In the third switching circuit SW3 in, the first fixed contact 29a and the movable contact 29c are electrically connected based on the high-level signal Sh. In the second switching circuit SW2, the operation of the first switching circuit SW1 becomes effective by electrically connecting the second fixed contact 26b and the movable contact 26c.

That is, the horizontal synchronizing signal H of the reproduction luminance signal Sv
When the burst signal Sb generated based on D is supplied to the third input terminal φ3, as shown in FIG.
The first M.M. At M23, when the burst signal Sb rises, the reproduction luminance signal S in the field rises.
v, a pulse signal Sm1 that falls in the back porch section Bp in the horizontal blanking period Hb is generated, and the second M.V. M24.
A pulse signal Sm1 output from M23 rises at the time of falling and falls in the back porch section Bp, that is, a pulse signal Sm2 having a pulse width t2 shorter than the section Bp in the back porch section Bp. Is generated.

This second M.M. The pulse signal Sm2 generated in M24 is supplied to the first switching circuit SW1 and the second fixed contact 25b and the movable contact 25c only during a period (pulse width t2) in which the pulse signal Sm2 is at a high level.
And are electrically connected. As a result, during the back porch section Bp in the horizontal blanking period Hb of the reproduction luminance signal Sv, the second M.M. The set potential Vr is supplied to the second switching circuit SW2 side instead of the reproduction luminance signal Sv only for the time period synchronized with the high-level output timing of the pulse signal Sm2 output from M24. Therefore, from the second switching circuit SW2, as shown in FIG. 2, the reproduction luminance signal Sv in which the set potential Vr is inserted in the back porch section Bp of the horizontal blanking period Hb.
Will be output.

Then, the reproduction luminance signal Sv in which the set potential Vr is inserted is supplied to the A / D converter 4 via the voltage follower circuit 9 in the next stage and converted into the digital luminance signal Dv, which is described above. As in the case of normal reproduction, data is written in the field memory 5 through the write processor 10 based on the input of the write clock Pw to the write processor 10 and the input of the update signal Sw of the write address to the field memory 5.

On the other hand, the clamp pulse generation block 22
Is the third switching circuit SW3, as shown in FIG.
The first fixed contact 29a and the movable contact 29c in FIG. M27 and the fourth M.I. M
Since 28 lines are selected, as shown in FIG. M27 rises when the normal clamp pulse P rises, and the second M.M. in the back porch section Bp in the horizontal blanking period Hb of the reproduction luminance signal Sv in the field. A pulse signal Sm3 that falls within the pulse width t2 of the pulse signal Sm2 output from M24 is generated.

After that, the fourth M.S. M28. When the pulse signal Sm3 output from the M27 rises, the pulse signal Sm3 rises and the second M.M. A pulse signal falling within the pulse width t2 of the pulse signal Sm2 output from M24, that is, the back porch section Bp.
In the second M. A pulse signal Sm4 having a pulse width t4 shorter than the pulse width t2 of the pulse signal Sm2 output from M24 is generated.
m4 is supplied to the write processor 10 via the third switching circuit SW3 as the clamp pulse Pc.

Then, the digital luminance signal Dv from the A / D converter 4 is taken out by the write processor 10 in the signal level during the period when the clamp pulse Pc is at the high level. That is, in this case, while the clamp pulse Pc is at the high level, the set potential Vr is
Since this corresponds to the period in which is inserted, the set potential Vr is taken out as the clamp error voltage signal Vc in the write processor 10.

Therefore, the reproduction luminance signal Sv after the next field is the set potential Vr inserted in the back porch Bp.
Therefore, the entire signal level is shifted and clamped so that V becomes the pedestal potential Vp.

At the stage where the digital data has been written up to almost the intermediate address of the field memory 5, the digital luminance signal Dv in the field memory 5 receives the read clock Pr to the read processor 11 and the read address to the field memory 5. Based on the input of the update signal Sr, the read processor 11 sequentially reads from the head address. Simultaneously with this reading, the digital luminance signal Dv is written to the addresses after the intermediate address in the field memory.

The digital luminance signal Dv read via the read processor 11 is read by the read processor 11
D / A converter 6 based on the timing signal St2 from
Is sequentially converted into an analog luminance signal Sv. The brightness signal Sv is taken out from the output terminal φout via the buffer circuit 7 in the next stage.

After a series of these operations, the reproduction luminance signal S accompanying the special reproduction supplied to the second input terminal φ2 is supplied.
v is taken out as a clean luminance signal Sv having no time deviation such as jitter or phase delay.

As described above, in the reproducing apparatus according to the first embodiment, during the special reproduction such as the variable speed reproduction, the reproduction luminance signal Sv is lost due to the azimuth loss, so that the reproduction luminance signal Sv is clamped particularly normally. Even if the noise component due to the lack is superimposed during the pedestal clamp period by the pulse P, the clamp is performed in the reproduction luminance signal Sv before the clamp operation in the write processor 10 based on the clamp pulse Sm4 from the clamp pulse generation block 22. Since the set potential Vr is inserted by the potential insertion block 21 in the period t2 including the high level period t4 of the clamp pulse Sm4 output from the pulse generation block 22, the write processor 10 uses the set potential Vr as a reference. It can be clamped as a potential .

As a result, the reference potential related to the clamp operation during special reproduction such as variable speed reproduction can be stabilized, and the fluctuation of the luminance during special reproduction can be eliminated. As a result, the quality of reproduced image can be improved. Can be improved.
Also, if there is a brightness variation during special reproduction, the viewer looking at the reproduced image will be very tired. However, in the reproducing apparatus according to the first embodiment, the brightness variation during special reproduction will occur. As the result is improved, it also has a health effect of suppressing eye fatigue of the viewer.

In addition, in the first embodiment, as the insertion period of the set potential Vr by the potential insertion block 21,
Since the back porch section Bp of the horizontal blanking period Hb is set, when the luminance signal extracted from the output terminal φout of this reproducing device is combined with the color signal in the subsequent signal processing system, the color synchronization signal (color burst signal) is generated. ) Is not affected, it is possible to avoid the disadvantage that the quality of the color is adversely affected by the set potential.

Further, as the potential insertion block 21, the first M.V. which selects an arbitrary time point in the back porch section Bp in the horizontal blanking period Hb. M23 and the second M.M.T. which sets the output width t2 of the set potential Vr. M24 and the second
Of the reproduction luminance signal Sv input to the input terminal φ2 of
M. From the time point selected in M23, the second M.M. M24
Since the first switching circuit SW1 that switches to the set potential Vr for the output width t2 set in step 1 is provided, the back porch section Bp in the horizontal blanking period Hb of the reproduction luminance signal Sv is provided with a simple circuit configuration. The set potential Vr can be inserted, and the structure of the reproduction system for improving the luminance fluctuation during special reproduction can be simplified.

Further, in the reproducing apparatus according to the first embodiment, in addition to the above configuration, the potential inserting block 21 has
During normal reproduction, the first switching circuit SW1
Since the second switching circuit SW2 for invalidating the operation of No. 1 and for enabling the operation of the first switching circuit SW1 at the time of special reproduction is provided, the set potential Vr is inserted at the time of normal reproduction. Therefore, it is possible to avoid the inconvenience that the quality of the video signal is deteriorated during normal reproduction.

Further, since the potential inserting block 21 having the above-mentioned configuration is inserted and connected in the preceding stage of the A / D converter 4 incorporated in the time base collector, the analog reproduction luminance signal before being digitally converted. On the other hand, the set potential Vr can be inserted by using a simple analog circuit. In this example, the insertion of the set potential into the reproduction luminance signal Sv is realized by simple switching by the first switching circuit SW1.

In this case, in the input stage of the time base collector, the potential inserting block 21 inserts the set potential Vr into the reproduction luminance signal Sv, and the clamp operation is performed based on the set potential Vr. Therefore, the reproduction luminance signal whose reference potential (bias level) is stabilized is supplied to the A / D converter 4, and a time deviation such as jitter or phase delay is generated from this time base collector. In addition, a luminance signal whose bias level is stabilized is extracted.

Next, the reproducing apparatus according to the second embodiment will be described with reference to the block diagram of FIG. 3 and the timing chart of FIG. In addition, the same code | symbol is described about the thing corresponding to FIG. 1, and the overlapping description is abbreviate | omitted.

As shown in FIG. 3, the reproducing apparatus according to the second embodiment has substantially the same structure as the reproducing apparatus according to the first embodiment, but is different in the following points.

That is, the second to which the reproduction luminance signal Sv is supplied.
A signal smoothing block 31 for smoothing the signal level of a predetermined period in the front porch section Fp of the horizontal blanking period Hb of the luminance signal Sv reproduced at the time of special reproduction is inserted and connected between the input terminal φ2 and the coupling capacitor 8. And that the normal clamp pulse P from the timing generator 3 is directly input to the write processor 10.

The signal smoothing block 31 removes a DC noise component from the reproduction luminance signal Sv supplied to the second input terminal φ2 on the input line extending from the second input terminal φ2 to the A / D converter 4. A coupling capacitor 32, a resistor R connected in series with the coupling capacitor 32, a capacitor C and a load resistor 33, which are connected in parallel between the input line and GND, are inserted and connected. The CR integrator circuit 34 includes the resistor R and the capacitor C.
Is configured.

A switching circuit 35 is connected between the capacitor C and GND. This switching circuit 35 has a movable contact 35 connected to GND.
a and a fixed contact 35b connected to one electrode of the capacitor C, an output signal from an AND circuit 36 described later, in this example, a high level logically indicating "1" from the AND circuit 36. The movable contact 35a and the fixed contact 35b are selectively electrically connected on the basis of the signal.

The AND circuit 36 is a 2-input AND circuit.
It is a circuit and is connected by wiring so that the signal Sh indicating the normal mode / special reproduction mode supplied to the fourth input terminal φ4 is input to one input terminal and the burst signal Sb is input to the other input terminal. ing.

Here, the burst signal Sb has a different generation system from the burst signal Sb in the reproducing apparatus according to the first embodiment, and the reproducing luminance signal Sv is different in the reproducing apparatus according to the second embodiment. The trigger pulse is generated by the supplied synchronization signal extraction circuit 2, and more specifically, as shown in FIG. 4, the trigger pulse is generated based on the horizontal synchronization signal HD of the supplied reproduction luminance signal Sv. Similar to the burst signal Sb used in the embodiment, a trigger that rises for a predetermined time from the fall of the horizontal synchronizing signal HD in the reproduction luminance signal Sv, for example, in the front porch section Fp in the horizontal blanking period Hb of the reproduction luminance signal Sv. It is a pulse.

Therefore, the switching circuit 35 is turned on (movable) only during the period tb when the special reproduction is selected and the signal Sh indicating the normal mode / special reproduction mode is at the high level and the burst signal Sb is at the high level. Contact 3
5a and the fixed contact 35b are electrically connected), and the period t
Only the input signal b (reproduced luminance signal Sv) is smoothed by the CR integrator circuit 34, that is, the high frequency component is removed to smooth the signal level.

Next, the operation of the reproducing apparatus according to the second embodiment will be described with reference to the timing chart of FIG.

First, when the normal reproduction mode is selected by operating the operation key indicating the normal reproduction on the operation panel, the signal Sh indicating the normal mode / special reproduction mode supplied to the fourth input terminal φ4 is , As a low level signal. Therefore, the AN in the signal smoothing block 31
The D circuit 36 outputs a low level signal logically indicating "0", and in this case, the switching circuit 35 is turned off. This allows C from the input line
This is equivalent to removing the capacitor C forming the R integrating circuit 34, and the reproduction luminance signal Sv shifted down from the signal smoothing block 31 by a level corresponding to the resistance voltage division ratio of the resistance R and the load resistance 33. Will be output.

The reproduced luminance signal Sv output from the signal smoothing block 31 has its DC level corrected by the coupling capacitor 8 in the next stage, and has the DC level at the time of passing through the coupling capacitor 32 in the signal smoothing block 31. It is returned to the brightness signal Sv.

Then, the reproduced luminance signal Sv is sequentially converted into the digital luminance signal Dv by the A / D converter 4 based on the timing signal St1 from the writing processor 10, and the writing clock Pw to the writing processor 10 is further added. And the update signal Sw of the write address to the field memory 5 are input, the data is written in the field memory 5 through the write processor 10.

At this time, the write processor 10 is supplied with the clamp pulse P for performing the normal pedestal clamp from the timing generator 3, the signal level of the front porch section Fp in the horizontal blanking period Hb is taken out, and the clamp error occurs. It is supplied to the bias correction circuit 12 as a voltage signal Vc. Bias correction circuit 1
2 outputs an output signal (DC voltage signal) VDC obtained by integrating the difference between the clamp error voltage signal Vc from the write processor 10 and the pedestal potential Vp.

This output signal VDC is supplied to the preceding stage of the voltage follower circuit 9 connected to the preceding stage of the A / D converter 4 to reproduce the reproduced luminance signal Sv relating to the field extracted this time after the next field. The entire signal level is shifted so that the signal level of the front porch Fp in the luminance signal Sv becomes the pedestal potential Vp. That is, it will be clamped.

At the stage where the digital data has been written up to almost the intermediate address of the field memory 5, the digital luminance signal Dv in the field memory 5 receives the read clock Pr to the read processor 11 and the read address to the field memory 5. Based on the input of the update signal Sr, the read processor 11 sequentially reads from the head address. Simultaneously with this reading, the digital luminance signal Dv is written to the addresses after the intermediate address in the field memory 5.

The digital luminance signal Dv read via the read processor 11 is read by the read processor 11
D / A converter 6 based on the timing signal St2 from
Is sequentially converted into an analog luminance signal Sv. The brightness signal Sv is taken out from the output terminal φout via the buffer circuit 7 in the next stage.

After a series of these operations, the reproduction luminance signal S accompanying the normal reproduction supplied to the second input terminal φ2 is supplied.
v is taken out from the output terminal φout as a clean luminance signal Sv having no time deviation such as jitter and phase delay.

Next, when the special reproduction mode is selected by operating the operation key for special reproduction such as variable speed reproduction on the operation panel, the normal mode / special reproduction mode supplied to the fourth input terminal φ4. Is input as a high level signal. At this stage, the reproduction luminance signal Sv
Signal extraction circuit 2 in the front porch section Fp of
The AND circuit 36 in the signal smoothing block 31 outputs a high-level signal logically indicating "1" only during the period tb in which the burst signal Sb from the signal is high level. In this case, the switching circuit 35 is turned on, which is equivalent to connecting the capacitor C forming the CR integrating circuit 34 to the input line.

Therefore, the high frequency component of the reproduction luminance signal Sv in the period tb is removed by the CR integration circuit 34,
The signal level in the period tb is smoothed, and the reproduced luminance signal Sv in which the signal level in the period tb is smoothed is output from the signal smoothing block 31.

The reproduced luminance signal Sv output from the signal smoothing block 31 has its DC level corrected by the coupling capacitor 8 in the next stage, and has the DC level at the time of passing through the coupling capacitor 32 in the signal smoothing block 31. It is returned to the brightness signal Sv.

The reproduction luminance signal Sv is sequentially converted into a digital luminance signal Dv by the A / D converter 4 based on the timing signal St1 from the writing processor 10, and the writing clock Pw to the writing processor 10 is further added. And the update signal Sw of the write address to the field memory 5 are input, the data is written in the field memory 5 through the write processor 10.

At this time, the write processor 10 is supplied from the timing generator 3 with the clamp pulse P for performing the normal pedestal clamp, and the signal level of the front porch section Fp in the horizontal blanking period Hb is taken out to cause a clamp error. It is supplied to the bias correction circuit 12 as a voltage signal Vc. Bias correction circuit 1
2 outputs an output signal (DC voltage signal) VDC obtained by integrating the difference between the clamp error voltage signal Vc from the write processor 10 and the pedestal potential Vp.

This output signal VDC is supplied to the preceding stage of the voltage follower circuit 9 connected to the preceding stage of the A / D converter 4, and the reproduction of the reproduced luminance signal Sv relating to the field extracted this time is reproduced in the fields subsequent thereto. The entire signal level is shifted so that the signal level of the front porch Fp in the luminance signal Sv becomes the pedestal potential Vp. That is, it will be clamped.

At the stage where the digital data has been written up to almost the intermediate address of the field memory 5, the digital luminance signal Dv in the field memory 5 receives the read clock Pr to the read processor 11 and the read address to the field memory 5. Based on the input of the update signal Sr, the read processor 11 sequentially reads from the head address. Simultaneously with this reading, the digital luminance signal Dv is written to the addresses after the intermediate address in the field memory 5.

The digital luminance signal Dv read via the read processor 11 is read by the read processor 11
D / A converter 6 based on the timing signal St2 from
Is sequentially converted into an analog luminance signal Sv. The brightness signal Sv is taken out from the output terminal φout via the buffer circuit 7 in the next stage.

After a series of these operations, the reproduction luminance signal S accompanying the special reproduction supplied to the second input terminal φ2 is supplied.
v is taken out as a clean luminance signal Sv having no time deviation such as jitter or phase delay.

As described above, in the reproducing apparatus according to the second embodiment, during variable speed reproduction, the video signal is lost due to azimuth loss, and the pedestal clamp section of the reproduction luminance signal Sv, in particular, the normal clamp pulse P is generated. Even if the noise component due to the lack thereof is superimposed on the reproduction luminance signal Sv in the previous stage of the clamp operation in the write processor 10 based on the normal clamp pulse P.
Front porch section F in the middle and horizontal blanking period Hb
Since the signal level of p is smoothed by the signal smoothing block 31 and the potential change of the section Fp is suppressed low, the write processor 10 clamps the signal level of which the potential change is suppressed as a reference potential. It will be possible.

As a result, the reference potential related to the clamp operation during special reproduction such as variable speed reproduction can be stabilized, and the fluctuation in luminance during special reproduction can be eliminated, and as a result, the quality of reproduced image can be improved. Can be improved.
Also, if there is a brightness variation during special reproduction, the viewer looking at the reproduced image will be very tired, but in the reproducing apparatus according to the second embodiment, the brightness variation during special reproduction will occur. As the result is improved, it also has a health effect of suppressing eye fatigue of the viewer.

Further, in the reproducing apparatus according to the second embodiment, since the signal smoothing block 31 is inserted and connected in front of the A / D converter 4 incorporated in the time base collector, digital conversion is performed. It is possible to smooth the signal level of the reproduced luminance signal Sv before being processed, particularly in the front porch section Fp of the horizontal blanking period Hb by a simple analog circuit. In this example, smoothing of the signal level is realized by a simple CR integrating circuit 34.

In this case, the signal level of the front porch section Fp is smoothed at the input stage of the time base collector, and the clamp operation is performed based on this smoothed signal level. A /
The reproduction luminance signal Sv whose reference potential (bias level) is stabilized is supplied to the D converter 4, and there is no time deviation such as jitter or phase delay from this time base collector, and the bias is applied. A luminance signal whose level is stabilized is extracted.

In particular, in the reproducing apparatus according to the second embodiment, the signal smoothing block 31 having a simpler structure than the potential inserting block 21 of the reproducing apparatus according to the first embodiment is provided in the preceding stage of the A / D converter 4. Insert and connect, and timing generator 3
Since the normal clamping pulse P is directly supplied from the write processor 10 to the write processor 10, the structure is simpler than that of the reproducing apparatus according to the first embodiment, and the manufacturing cost is advantageous.

Here, the criteria for adopting the reproducing apparatus according to the first embodiment or the reproducing apparatus according to the second embodiment to the VTR will be described.

First, the noise level generated during special reproduction is a noise level when a voltage much higher than the input level assumed due to the relationship between the tape pattern and the head of the rotary drum is applied as noise. It is preferable to employ the reproducing apparatus according to the first embodiment, which has a very high canceling effect.

On the other hand, when the level of noise applied to the luminance signal has a peak value that is acceptable to some extent, the signal waveform of the pedestal clamp target, particularly the high frequency component, is removed rather than adding a new voltage. If the signal waveform of the clamp error voltage signal associated with the pedestal clamp is smoothed by making the waveform of the large undulation uniform, the effect of the clamping is sufficiently stabilized (the potential in the front porch section Fp of the luminance signal Sv is stabilized. Effect).

From the above, if the entire waveform is undulated, the signal waveform of the clamped portion is naturally also undulated. Therefore, the A / D converter 4 and the write processor 10
And the first embodiment depending on the image quality of the video signal based on the luminance signal Sv when the digital signal is processed by the field memory 5 and returned to the analog signal by the D / A converter 4 in the first embodiment. Is such a playback device good?
Alternatively, it is determined whether the reproducing apparatus according to the second embodiment is suitable.

For example, in the case of a commercial 8 mm VTR, it is preferable to adopt the reproducing apparatus according to the first embodiment from the standpoint of image quality priority.

The reproducing apparatus according to the first embodiment and the second embodiment has been shown as an example in which the reproducing apparatus is applied to a part of the tom-based collector mounted on the VTR. However, in addition to this, a disk-shaped recording medium as a record carrier. , It can be applied to a reproducing apparatus for reproducing information signals for a reproduction-only optical disk or a writable magneto-optical disk, and displays a video signal transmitted by radio waves or optical communication on a display screen of a television receiver. It can also be applied to a playback device for playing.

[0148]

As described above, according to the video signal reproducing apparatus according to the present invention, the normal reproduction or the variable speed reproduction of the video signal recorded on the recording medium is performed by selectively switching the normal mode or the speed change mode. In the video signal playback device,
At least a potential inserting means for inserting a clamp potential for variable speed reproduction at a predetermined timing of the video signal reproduced when the shift mode is selected, and a clamp potential for the variable speed reproduction as a reference potential of the video signal during the variable speed reproduction. Since the clamp means for performing the special reproduction is provided, the reference potential related to the clamp operation during the special reproduction such as variable speed reproduction can be stabilized, and the fluctuation of the brightness during the special reproduction can be eliminated. The image quality of images can be improved. Also, if there is a brightness change during special playback, the viewer looking at the reproduced image will be very tired of the eyes. It also exerts a health effect of suppressing eye fatigue of people.

The video signal reproducing apparatus according to the present invention is
The time point when the clamp potential for variable speed reproduction is inserted by the potential inserting means is set to the back porch section in the horizontal blanking period, so that the color synchronizing signal (color burst signal) is not affected and the clamp potential changes It is possible to avoid the inconvenience of degrading the quality.

The video signal reproducing apparatus according to the present invention is
As the potential inserting means, a selecting means for selecting an arbitrary time point in the back porch section in the horizontal blanking period, a setting means for setting an output width of the variable speed clamp potential, and a reproduced video signal are selected. Since the switching means for switching the clamp potential for variable speed reproduction by the output width set by the setting means from the time point selected by the means is provided, the horizontal blanking of the reproduced video signal can be performed with a simple circuit configuration. The clamp potential for variable speed reproduction can be inserted in the back porch section during the period, and the structure of the reproduction system for improving the luminance fluctuation during special reproduction can be simplified.

Further, the video signal reproducing apparatus according to the present invention is
In addition to the above configuration, the potential inserting means is provided with the second selecting means for invalidating the operation of the switching means during the normal reproduction and for enabling the operation of the switching means during the variable speed reproduction. In this case, the clamp potential for variable speed reproduction is not inserted, and it is possible to avoid the inconvenience that the quality of the video signal during normal reproduction deteriorates.

Further, the video signal reproducing apparatus according to the present invention is
Since the potential inserting means having the above configuration is inserted and connected in the preceding stage of the A / D converter incorporated in the time base collector, the clamp potential for variable speed reproduction is analogized to the video signal before digital conversion. Since it can be inserted by using a circuit, it is possible to realize the insertion of the clamp potential for variable speed reproduction into the video signal with a simple circuit configuration. In addition to this, the time base collector outputs a video signal which has no time deviation such as jitter or phase delay and whose bias level is stabilized.

Further, the video signal reproducing apparatus according to the present invention is
Based on a normal reproduction clamp pulse for performing a normal pedestal clamp, the clamp means outputs the variable speed reproduction clamp potential during the insertion period and extracts the variable speed reproduction clamp potential. A clamp pulse generating means for generating a clamp pulse, and the normal reproduction clamp pulse at the time of normal reproduction are selected,
Since the selecting means for selecting the clamp pulse for variable speed reproduction from the clamp pulse generating means at the time of variable speed reproduction is provided, the normal pedestal clamp is performed at the time of normal reproduction and the above-mentioned potential at the time of variable speed reproduction. Since the clamp potential inserted by the inserting means is clamped as the reference potential, the reference potential relating to the clamp operation during special reproduction such as variable speed reproduction can be stabilized, and the luminance of special reproduction can be reduced. The fluctuation can be eliminated, and as a result, the quality of the reproduced image can be improved.

The video signal reproducing apparatus according to the present invention is
The clamp pulse generation means and the selection means are inserted and connected between the timing generator incorporated in the time base collector and the write processor, and the clamp pulse generation means, the selection means, the write processor and the write processor are connected. Since the clamp means is configured by the bias correction circuit for correcting the bias of the video signal based on the clamp error signal, the normal pedestal clamp is performed during the normal reproduction, and the normal pedestal clamp is performed during the variable speed reproduction. Since the clamp potential inserted by the potential inserting means is clamped as the reference potential, it is possible to stabilize the reference potential related to the clamp operation during special reproduction such as variable speed reproduction,
It is possible to eliminate the variation in luminance during special reproduction, and as a result, it is possible to improve the image quality of reproduced images.

The video signal reproducing apparatus according to the present invention is
By selectively switching between normal mode and shift mode,
In a video signal reproducing device for performing normal reproduction or variable speed reproduction of a video signal recorded on a recording medium, smoothing the signal level of a predetermined period in the front porch section of the horizontal blanking period of the video signal reproduced when the speed change mode is selected. Since the signal smoothing means and the clamp for clamping the signal level smoothed by the signal smoothing means as the reference signal of the video signal are provided, the reference potential related to the clamp operation during special reproduction such as variable speed reproduction is provided. Therefore, it is possible to eliminate fluctuations in luminance during special reproduction, and as a result, it is possible to improve the image quality of reproduced images. Also, if there is a brightness change during special playback, the viewer looking at the reproduced image will be very tired of the eyes. It also exerts a health effect of suppressing eye fatigue of people.

Further, the video signal reproducing apparatus according to the present invention is
Since the signal smoothing means is inserted and connected in the front stage of the A / D converter incorporated in the time base collector, the front porch section in the horizontal blanking period is particularly effective for the video signal before being digitally converted. The signal level at can be smoothed, and with a simple circuit configuration,
The signal level in the front porch section can be smoothed. In addition to this, the time base collector outputs a video signal which has no time deviation such as jitter or phase delay and whose bias level is stabilized.

[Brief description of drawings]

FIG. 1 is a VT for recording and reproducing a video signal on a magnetic tape by a helical scan system in a video signal reproducing device according to the present invention.
FIG. 3 is a block diagram showing a circuit configuration of a first embodiment (hereinafter, simply referred to as a reproducing apparatus according to the first embodiment) applied to a part of a TBC (time base collector) mounted on R.

FIG. 2 is a timing chart showing a signal processing operation of the reproducing apparatus according to the first embodiment.

FIG. 3 is a VT for recording / reproducing a video signal on a magnetic tape by a helical scan system in the video signal reproducing device according to the present invention.
It is a block diagram which shows the circuit structure of the 2nd Example (it is hereafter described only as the reproducing | regenerating apparatus based on 2nd Example) applied to a part of TBC (time base collector) mounted in R.

FIG. 4 is a timing chart showing a signal processing operation of the reproducing apparatus according to the second embodiment.

[Explanation of symbols]

1 Reference sync signal extraction circuit 2 Sync signal extraction circuit 3 Timing generator 4 A / D converter 5 Field memory 6 D / A converter 10 Write processor 11 Read processor 12 Bias correction circuit 13 Integrator 21 Potential insertion block 22 Clamp pulse Generation block 23 First monostable multivibrator (first M.V.
M) 24 second monostable multivibrator (second M.M.
M) SW1 first switching circuit SW2 second switching circuit 27 third monostable multivibrator (third M.M.
M) 28 4th monostable multivibrator (4th M.
M) SW3 Third switching circuit 31 Signal smoothing block 34 CR integrating circuit 35 Switching circuit 36 AND circuit St1 and St2 Timing signal Svr REF Video signal S1 Reference sync signal S2 Sync signal Sv Playback luminance signal Pw Write clock Sw Update of write address Signal Pr Read clock Sr Read address update signal Pc Clamp pulse Vc Clamp error voltage signal Vr Set potential Vp Pedestal potential

Claims (12)

[Claims] 1. A video signal reproducing apparatus for performing normal reproduction or variable speed reproduction of a video signal recorded on a recording medium by selectively switching a normal mode or a speed change mode, wherein the image reproduced at least when the speed change mode is selected. A video having a potential inserting means for inserting a clamp potential for variable speed reproduction at a predetermined timing of a signal and a clamp means for clamping the clamp potential for variable speed reproduction as a reference potential of the video signal during the variable speed reproduction. Signal reproduction device. 2. The video signal reproducing apparatus according to claim 1, wherein the potential inserting means inserts the variable speed reproducing clamp potential into a back porch section in a horizontal blanking period. 3. The potential inserting means, selecting means for selecting an arbitrary time point in a back porch section in a horizontal blanking period, setting means for setting an output width of the variable speed reproducing clamp potential, and reproduced. 3. The switching means for switching the video signal to the clamp potential for variable speed reproduction from the time point selected by the selection means by the output width set by the setting means. Video signal playback device. 4. The potential inserting means has a second selecting means for invalidating the operation of the switching means during normal reproduction and validating the operation of the switching means during variable speed reproduction. Item 3. The video signal reproducing device according to Item 3. 5. The video signal reproduction according to claim 1, wherein the potential inserting means is inserted and connected in front of an A / D converter incorporated in the time base collector. apparatus. 6. The clamp means outputs the clamp potential for variable speed reproduction, which is output during the insertion period of the clamp potential for variable speed reproduction, on the basis of a clamp pulse for normal reproduction for performing a normal pedestal clamp. Clamp pulse generating means for generating a variable speed reproduction clamp pulse for selecting the normal reproduction clamp pulse during normal reproduction, and a selection for selecting the variable speed reproduction clamp pulse from the clamp pulse generation means during variable speed reproduction. The video signal reproducing apparatus according to claim 1, further comprising means. 7. The clamp pulse generation means and the selection means are inserted and connected between a timing generator incorporated in a time base collector and a write processor, and the clamp pulse generation means, the selection means, the write processor and 6. The video signal reproducing apparatus according to claim 5, wherein the clamp means is composed of a bias correction circuit that corrects the bias of the video signal based on a clamp error signal from the writing processor. 8. A video signal reproducing apparatus for performing normal reproduction or variable speed reproduction of a video signal recorded on a recording medium by selectively switching the normal mode or the speed change mode, wherein the video signal reproduced when the speed change mode is selected. Signal smoothing means for smoothing the signal level in a predetermined period in the front porch section of the horizontal blanking period, and clamping means for clamping the signal level smoothed by the signal smoothing means as the reference potential of the video signal. Video signal reproducing device characterized by. 9. The video signal reproducing apparatus according to claim 8, wherein the signal smoothing means is inserted and connected in front of an A / D converter incorporated in the time base collector. 10. The signal smoothing means has a selecting means for activating smoothing of a signal level of a predetermined period in a front porch section of a horizontal blanking period of the video signal during variable speed reproduction. 8 or 9
The described video signal reproducing device. 11. The clamp means sets the signal level smoothed by the signal smoothing means on the basis of a normal reproduction clamp pulse for performing a normal pedestal clamp regardless of normal reproduction and variable speed reproduction. 9. The video signal reproducing device according to claim 8, wherein the video signal is clamped as a reference potential of the video signal. 12. The clamp means comprises a write processor incorporated in a time base collector and a bias correction circuit for correcting the bias of the video signal based on a clamp error signal from the write processor. The video signal reproducing device according to claim 8 or 11, which is characterized in that.