JPH05130560A - Video signal processing device - Google Patents

Abstract

PURPOSE:To stably operate without malfunction in case of missing synchronizing signals and to reduce the circuitry by connecting line memory and N-line memory in series for each channel, reading the line memory, controlling the N-line memory writing and reading in common. CONSTITUTION:The reproduction video signals of channels A and B with the time axis fluctuation where a line sequential chrominance signal C and a luminance signal Y are time-division multiplexed are inputted from terminals A and B. The reproduction video signals of the channels A and B are inputted to an A/D converter 1A and a synchronizing information separator circuit 600A. The circuit 600A outputs vertical and horizontal synchronizing signals and burst signals separately from the video signals. The video information from the circuit 1A is successively written in a line memory 210A in the order of address. The information is read based on the reading set signal and clock from a control circuit 300. The read effective video information is inputted to the field memory 220A. The writing and reading is performed based on the writing and reading reset signals from the control circuit 300.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus for recording / reproducing a video signal on / from a recording medium, and in particular, in a high-definition television signal having a wide band, a luminance signal and a chrominance signal are time-division multiplexed and further channel-divided. The present invention relates to a video signal processing device which corrects a time-axis fluctuation of a video signal recorded by performing the demodulation and channel synthesis of a time-division multiplexed signal without causing malfunctions.

[0002]

2. Description of the Related Art In a video signal recording / reproducing apparatus such as a VTR (video tape recorder), a time base fluctuation occurs in a reproduced video signal due to a relative positional fluctuation between a signal detection medium and a recording medium. Such time-axis fluctuations appear as fluctuations and waviness in the reproduced image, and significantly impair the image quality of the reproduced image. As an example of a video signal processing device for correcting this time-axis fluctuation, an example described in a document (Japan Broadcasting Publishing Association, Broadcasting Technology Co., Ltd., Vol. 5, VTR technology, Chapter 6) is conventionally known. Further, in a recording / reproducing apparatus for recording / reproducing a wideband video signal such as a high definition television signal,
In order to reduce the signal band of a video signal to a frequency region that can be recorded on a recording medium, a method of time-division multiplexing by expanding and compressing a luminance signal and a chrominance signal respectively, or further dividing and recording into multiple channels There is. In this case, at the time of reproduction, it is necessary to perform signal processing reverse to that at the time of recording, that is, the time axis compression and expansion of the luminance signal and the color signal respectively, demodulation of the time division multiplexed signal, and further channel combination. Regarding the circuit configuration for performing this signal processing, for example, a wideband signal recording / reproducing method and apparatus disclosed in Japanese Patent Laid-Open No. 58-38091 are conventionally known.

[0003]

The video signal processing apparatus for correcting the fluctuation of the time axis is constructed by using a memory, and address control for writing and reading is required, but when a dropout occurs or when it is possible. Even when the vertical and horizontal sync signals multiplexed in the video signal are lost during variable speed reproduction, the missing vertical sync signal and horizontal sync signal are interpolated and stored in order to store the video data in a predetermined address area of the memory. It was necessary to devise a circuit considerably so that the write address control could be controlled. Particularly in the case of multi-channel recording, it is necessary to correct the missing vertical and horizontal synchronizing signals for each channel to perform address control, which causes a problem that the signal processing is complicated and the circuit scale becomes large.
Further, if the interpolation of the missing vertical and horizontal synchronizing signals fails, there is a problem that the predetermined signal processing is significantly disturbed.

Further, in the prior art described in the above-mentioned Japanese Patent Laid-Open No. 58-38091, the luminance signal and the chrominance signal are respectively compressed and expanded on the time axis at the time of reproduction to demodulate the time division multiplex signal to perform channel combination. Although the circuit configuration was performed, no consideration was given to the circuit configuration for performing time axis fluctuation correction.

It is an object of the present invention to video-record a VTR or the like in which a luminance signal and a chrominance signal are time-division multiplexed in order to record and reproduce a wide-band video signal such as a high-definition television signal and further channel-divided. In a signal recording / reproducing device, stable operation without malfunction even if a sync signal is lost during dropout occurrence or variable speed reproduction is performed.In addition to time-axis fluctuation correction, luminance signal and color signal are time-axis compressed and An object of the present invention is to provide a video signal processing device which is capable of performing high-speed signal processing with a small circuit scale that expands and demodulates a time-division multiplexed signal and also performs channel synthesis.

[0006]

The above object can be achieved as follows. That is, in each channel, a first memory capable of accumulating at least one line of video information and asynchronously performing a write operation and a read operation;
(N is an integer of 2 or more) A memory configuration in which a second memory capable of accumulating video information of a line and asynchronously performing a write operation and a read operation is connected in cascade is provided, and each channel is independently supplied from an input video signal. Sync information separating means for separating included sync information, first clock generating means for generating a clock of a predetermined frequency synchronized with the input video signal based on the separated sync information, the first clock and the above And a first control means for generating a predetermined first control signal based on the separated synchronization information. further,
As a means common to each channel, there is provided a second clock generating means for generating a clock having a stable predetermined frequency, and the second clock generating means.
Second clock signal and a signal representing the rotational phase of the magnetic head, or a second predetermined control signal which is phase-synchronized with the input video signal and is stable based on the separated synchronization information included in the input video signal. Control means, third clock generating means for generating a clock having a stable predetermined frequency, and reference signal generation for generating a stable reference clock for a predetermined reference signal and luminance signal and chrominance signal based on the third clock. And a switching circuit for switching between the luminance signal and the color signal read from the second memory based on the reference signal. Then, independently of each channel, the input video signal is sequentially written in a predetermined address area of the first memory in accordance with the first control signal, and the second channel common to each channel is written.
The video signal written in the first memory in accordance with the control signal of the second memory, and the read video signal is read by the second memory.
The image written in the second memory is written in a predetermined address area of the second memory sequentially in accordance with the control signal, and the image written in the second memory in accordance with the read clock of the luminance signal and the color signal output from the reference signal generating means. This can be realized by sequentially reading the signals and switching the video signal read by the switching circuit in line units according to the second control signal.

[0007]

The first memory of each channel sequentially writes the input video signal in units of one line based on the first clock generated in each of the channels, and inputs the written video signal in units of one line. It operates so as to sequentially read in synchronization with the video signal in phase. As a result, the first memory is 1
It functions as a line buffer memory, and even if sync information is lost or noise is mistakenly separated by the sync information separating means during dropout occurrence or variable speed reproduction, the video information of the relevant line is only disturbed. Line is not affected, and in particular, a video signal can be stably read line by line without providing a sync information correction unit for interpolating the missing sync information in each channel, and the entire device does not malfunction. It can be operated extremely stably.

The second memory of each channel is
The video signal read from the first memory of each channel in N line units is sequentially written in phase synchronization with the input video signal, and the written video signal is correctly read in N line units on a stable time axis. Operate. As a result, the second memory functions as a buffer memory for obtaining the correction amount of time axis fluctuation of maximum ± N / 2 lines.

Also in the case of multi-channel recording, since the first memory of each channel functions as a one-line buffer memory, the reading of the first memory and the writing and reading of the second memory are performed. It can be controlled by the second one control means common to each channel,
It is not necessary to provide the second control means for each channel,
The control becomes simple and the circuit scale can be reduced.

Further, even for a signal in which a luminance signal and a color signal are time-division multiplexed, the reference signal generating means outputs the luminance signal reading clock and the color signal reading clock as a clock for reading the second memory, and the second signal is output. By switching the two read clocks according to the video signal to be read when reading the memory, the read video signal can be expanded and compressed on the time axis, and the time-division multiplexed luminance signal and chrominance signal are demodulated. be able to. Further, at the time of reading, the luminance signal and the color signal are sequentially read from the second memory of each channel in units of one line in accordance with the reference signal,
By sequentially switching by the switching circuit, the time-division-multiplexed video signals recorded by being divided into multiple channels are demodulated, channel-synthesized, the time axis fluctuation is corrected, and the original high-definition television signal is restored. Can be restored.

At this time, if the first memory and the second memory are first-in first-out memories, an address signal is not required, so that the address generating circuit can be reduced and high speed writing / reading operation can be performed at high speed. Can be signal processed.

As described above, in order to record / reproduce a wide-band video signal such as a high-definition television signal, a luminance signal and a color signal are time-division-multiplexed, and further channel-divided. In the recording / reproducing apparatus, stable operation without malfunction even if a dropout occurs during reproduction or a sync signal is lost during variable-speed reproduction, and in addition to time-axis fluctuation correction, luminance signal and color signal are time-axis compressed and It is possible to configure a video signal processing device that expands and demodulates a time-division multiplexed signal and that also performs channel combining, has a small circuit scale, is simple, and is capable of high-speed signal processing.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to record / reproduce a wideband video signal such as a high definition television signal according to an embodiment of the present invention, a luminance signal and a chrominance signal are time-axis expanded and compressed, respectively, and time division multiplexed. A case where the present invention is applied to a two-channel split recording type helical scan type magnetic recording / reproducing apparatus that divides into channels and performs recording / reproduction will be described in detail as an example. FIG. 2 shows an example of the input video signal according to the embodiment of the present invention. The form of the input video signal in this embodiment in the 2-channel recording system will be described below with reference to FIG. Luminance signal Y and color signals Pb, P of a video signal such as a broadband high-definition television signal
Of r, the effective luminance signal Y excluding the sync signal and the burst and the effective color signals Pb and Pr are shown in FIGS. 2 (a), 2 (b) and 2 (c), respectively. The color signals Pb and Pr are line-sequentially processed,
As shown in FIG. 2D, line-sequential color signals C in which Pb and Pr are transmitted alternately line by line are converted. The luminance signal Y and the line-sequential color signal C are switched on a line-by-line basis.
As shown in (f), the luminance signal Y and the line-sequential color signal C are converted into two-channel signals for each line. The luminance signal Y and the line-sequential color signal C are subjected to time-axis conversion processing (luminance signal Y is time-axis expansion processing, line-sequential color signal is time-axis compression processing) via a memory, and a synchronization signal and a burst signal are obtained. The added video signals are recorded on the magnetic tape as the 2-channel recording video signals shown in FIGS. 2 (g) and 2 (h). Therefore, in this embodiment, the reproduced video signal of the above recording signal form reproduced from the magnetic tape is the input video signal of 2 channels,
Time division multiplexing and channel division are applied.

FIG. 1 is a block diagram showing an embodiment of a video signal processing device when the present invention is applied to the two-channel split recording type helical scan type magnetic recording / reproducing device, and FIGS. 3 and 4 are for explaining the operation thereof. FIG. The operation when a FIFO (First In First Out) system memory is used as the memory will be described below. From above terminal 10A
As shown in (g), the channel-divided reproduction video signal of the channel A having the time-axis fluctuation in which the line-sequential color signal C and the luminance signal Y are time-axis multiplexed (FIGS. 3A and 4A). )
However, from the terminal 10B, similarly, as shown in FIG. 2 (h), the reproduced video signal of the channel B having the time base fluctuation in which the line-sequential color signal C and the luminance signal Y are time division multiplexed is input. The signal processing of channel A will be described below. The reproduced video signal of channel A is supplied to the A / D conversion circuit 1A and the synchronization information separation circuit 600A. The synchronization information separation circuit 600A is
The vertical synchronizing signal VSA (see FIG. 4) included in the reproduced video signal.
(B)), horizontal sync signal HSA (FIG. 3 (b), FIG.
(C)), the burst signal BSTA (FIGS. 3C and 4D) superimposed in the horizontal blanking period is separated and output.

The write clock generation circuit 500A includes an AFC circuit based on the horizontal synchronization signal HSA or a horizontal synchronization signal HSA, as described in the above-mentioned document, for example.
Instead of the APC circuit based on the burst signal BSTA or a circuit using both the AFC circuit based on the horizontal synchronizing signal HSA and the APC circuit based on the burst signal BSTA, an input video signal for each channel is formed. Write clock CK1 following time axis fluctuation
A (frequency f ₁ ) is generated. Therefore, the reproduced video signal having a time base fluctuation input from the terminal 10A is sequentially converted from an analog signal to a digital signal in the A / D conversion circuit 1A in synchronization with the write clock CK1A output from the write clock generation circuit 500A. Converted and line memory 21
Supplied to 0A.

The horizontal synchronizing signal HSA output from the synchronizing information separating circuit 600A is the control signal generating circuit 100.
Supplied to A. The control signal generation circuit 100A delays the horizontal synchronizing signal HSA supplied for each channel by a predetermined time based on the write clock CK1A, and outputs the input video signal (in each line of FIGS. 3A and 4A). , Write reset signal WR indicating the start position of the effective video signal section
T1A (FIG. 3 (d), FIG. 4 (e)) is generated and supplied to the write reset terminal WR of the line memory 210A. The line memory 210A uses at least the effective video information (the number of samples) excluding redundant video information such as a horizontal blanking period in the input playback video signal of 1H (1H: 1 horizontal scanning period) of the video signal input from 10A. It is a FIFO type memory having a capacity capable of storing l) and capable of independently and asynchronously performing a write operation and a read operation.

The line memory 210A has a write reset signal WRT1A supplied to the write reset terminal WR.
By this, after the write address is initialized (preset to address 0) at the effective position of the effective video signal for each line, the write clock CK1A supplied to the write clock terminal WCK
In synchronization with the above, the video information output from the A / D conversion circuit 1A is sequentially written into a predetermined address area. As described above, since the write address is initialized at the effective video signal start position for each line, the effective video information (the number of samples 1) of each line is the timing shown in FIGS. 3 (e) and 4 (f). Therefore, the data is sequentially written in the area from address 0 to address (l-1) in units of one line.

Next, as described above, the line memory 210
The case of reading the effective video information written in every H in the predetermined address area of A will be described.

The reading of the effective video information written in the line memory 210A is performed regardless of the writing operation.
The read reset signal RRT1A (FIG. 3 (f), FIG. 4) generated at 300 and supplied to the read reset terminal RR and the read clock terminal RCK of the line memory 210A, respectively.
(g)), clock CK2'A (frequency f ₁ ; FIG. 3 (g), FIG. 4 (h)). Read reset signal RR
As will be described later in detail, T1A is an input reproduced video signal (Fig. 3 (a), Fig. 4) from the terminal 10A having a time base fluctuation.
(H) is a signal that never phases out in 1H period, which is phase-locked to (a)), and is the write reset signal WRT.
This is a signal delayed by time α (0 <α <1H) from 1A. Therefore, in the line memory 210A, after the read address is always initialized (preset to address 0) every 1H by the read reset signal RRT1A, the line memory 210A is phase-synchronized with the input reproduction video signal, and the line memory 210A shown in FIG. At the timing shown in (i), the clock CK is delayed by a time α from the writing start point.
Based on 2'A, the effective video information of each line written in the area from address 0 to address (l-1) can be sequentially read line by line stably without malfunction. Further, at this time, as shown in FIGS. 3 (g) and 4 (h), for example, by stopping the clock CK2'A, the line memory 210A detects a horizontal blanking period, a vertical blanking period, or the like. Redundant video information is not read at all, and only valid video information excluding these redundant video information is accurately read without excess or deficiency of one sample per line.

By the way, as shown in FIGS. 3 and 4, the horizontal synchronizing signal H is generated when a dropout occurs or at a variable speed reproduction.
When the SA is missing, the line memory 210A operates as follows.

When the horizontal synchronizing signal HSA is missing,
The write reset signal WRT1A based on this is not generated (FIG. 3 (d)). Therefore, in the line memory 210A, the write address is not initialized until the write reset signal RRT1A generated based on the next separated horizontal synchronizing signal HSA is newly supplied to the write reset terminal WR. Therefore, during this period, the valid video information of the line in which the horizontal synchronizing signal HSA is missing is not written in the area from the address 0 to the address (l-1) of the line memory 210A, and the valid video information already written is held. (Fig. 3 (e)). That is, the line memory 210A writes the valid video information of the line to the area from address 0 to address (l-1) when the horizontal synchronizing signal HSA is separated, and when it is missing, the valid video that has already been written. Operates to retain information.

On the other hand, as described above, the line memory 210
A is a read reset signal R regardless of the write operation.
Based on RT1A and clock CK2'A, the effective video information written in the area from address 0 to address (l-1) is phase-synchronized with the input reproduced video signal, and 1 sample is read every 1H without excess or deficiency. Works like.

Therefore, when the horizontal synchronizing signal HSA is missing, the valid image information corresponding to the line where the horizontal synchronizing signal HSA is missing is included in the valid image information of each line read from the line memory 210A as shown in FIG. As shown in, the effective video information of the immediately preceding line is repeatedly read. However, in particular, the horizontal synchronization signal HSA can be read even if the horizontal synchronization signal HSA is not devised so that predetermined signal processing is performed. Is automatically replaced with that of the previous line, and the line memory 210A does not cause an excess or deficiency of even one sample of the valid image information (the number of samples 1) of each line on a line-by-line basis. Can be read.

Further, as shown in FIG. 3 (b), the synchronization information separation circuit of FIG.
At 600A, if the noise N is erroneously separated along with the horizontal sync signal HSA, the line memory 210A operates as follows.

When the noise N is erroneously separated together with the horizontal synchronizing signal HSA, the erroneous write reset signal NRTA (FIG. 3) generated by the control signal generating circuit 100A of FIG.
(d)) is generated. Therefore, the line memory 210A
3E, since the write address is initialized by the wrong write reset signal NRTA at a position other than the effective video signal start position, the video information is sequentially written from address 0 again. , The valid video information (sample number 1) of the line cannot be written in a predetermined area in the area from address 0 to address (1-1).
However, in the next line, the horizontal sync signal HSA
When the line is separated, the line memory 210A again operates so as to write the valid video information of the line in the area from the address 0 to the address (l-1) in a predetermined manner.

Therefore, if the noise N is erroneously separated,
Of the effective image information of each line read from the line memory 210A, the effective image information of the line in which the noise N is erroneously separated is not correct image information as shown in FIG. By passing through 210A, the malfunction due to noise N is limited to the line concerned and has no effect on the write operation and read operation of other lines. From the line memory 210A, the effective image information of each line is incremented by 1H. (Sample number 1) can be read without any excess or deficiency of one sample.

As is clear from the above description, the line memory 210A functions as a buffer memory for one line, and by providing the line memory 210A, even if dropout occurs or variable speed reproduction occurs, dropout, noise in, etc. Causes the horizontal sync signal HSA to drop,
Even if the noise N is mistakenly separated together with the horizontal synchronizing signal HSA, the effective video information of the relevant line is replaced with or disturbed by that of the previous line, and the effect is suppressed only to the relevant line, and the other lines are suppressed. There is no effect on the effective video information of, and the signal processing or the reproduced image is not significantly disturbed. Therefore, by thus passing through the line memory 210A, even if the horizontal synchronizing signal HSA is missing or the noise N is erroneously separated, predetermined signal processing is performed by supplementing the missing horizontal synchronizing signal HSA. Even if the circuit is not devised, the effective image information excluding the redundant image information such as the vertical blanking period and the horizontal blanking period is removed from the line memory 210A in units of one line by a simple circuit and simple signal processing. One sample can be stably read without excess or deficiency, and the entire apparatus can be operated extremely stably.

Next, control for generating the above-mentioned read reset signal RRT1A for channel A, clock CK2'A, etc., for reading only valid video information from the line memory 210A stably in one line unit without excess or deficiency. Circuit 3
An example of 00 will be described.

In FIG. 1, a head switching signal SW for controlling the head switching timing of the channel A generated in synchronization with the rotation of the magnetic head is input from the terminal 110 and supplied to the control circuit 300. In addition, the control circuit 300 is supplied with the reference clock CK2 output from the crystal oscillation circuit 60. The read reset signal RRT1A and the clock CK2'A for controlling the channel A are generated based on the head switching signal SW and the reference clock CK2. FIG. 5 shows a specific example of the control circuit 300. FIG. 6 is a waveform diagram for explaining the operation.

In FIG. 5, a terminal 301 is an input terminal for the head switching signal SW, and a terminal 302 is an input terminal for the reference clock CK2. The reference clock CK2 has a frequency of f ₁ (the same frequency as the write clock CK1A) and is a stable and continuous clock (FIG. 6 (e)). Further, the head switching signal SW (FIG. 6B) is generated based on the tack pulse detected by the magnet on the rotary head on which the magnetic head is mounted and the fixed tack head. Therefore, the head switching signal SW is a signal indicating the rotation phase of the magnetic head, and is a reproduced video signal (FIG. 3 (a), FIG. 4 (a), FIG.
FIG. 6 (a)) shows the phase-locked signal.

The head switching signal SW (FIG. 6 (b)) input from the terminal 301 is supplied to the double-edge detection circuit 310.
The both-edge detection circuit 310 is a circuit that detects both edges of the head switching signal SW, and outputs a both-edge detection signal EP that is phase-synchronized with both edges of the head switching signal SW, as shown in FIG. 6C. To do. The both-edge detection signal EP is delayed by a predetermined time τ ₁ by the delay circuit 320 and supplied to the clear terminal CR of the counter 330 as a clear signal CR1 (FIG. 6 (d)). On the other hand, the reference clock CK2 input from the terminal 302 is supplied to the clock terminal CLK of the counter 330. The clear signal CR1 is a reproduced video signal (FIG. 3 (a), FIG.
(a) and FIG. 6 (a)), the counter 330 is phase-synchronized with the video signal by the clear signal CR1. Therefore, the counter 330 is phase-synchronized with the video signal by 1V (1V: 1 vertical scanning line period). After the count value is initialized, the reference clock CK2 is counted. The decoder A 340 has a count output C of the counter 330.
P1 is supplied, but the decoder A340 outputs this count output CP
1 becomes a predetermined value, the decode signal DP1 (see FIG.
(f)) is output. The decoder A 340 has a decode value set so as to output the decode signal DP1 when the counter 330 counts the number of clocks corresponding to one line. The decode signal DP1 is supplied to the terminal 303 and the counter 330 is preset. It is supplied to the terminal LD. The counter 330 presets the count value to a predetermined set value by the decode signal DP1 supplied to the preset terminal LD, and then counts the reference clock CK2 supplied to the clock terminal CLK again. If the set value is set to zero, the counter 330 causes the clear signal CR1
After the count value is initialized by every 1V, the count value is preset to a set value (zero) in one line cycle by the decode signal DP1. Therefore, as shown in FIG. 6 (f), the decode signal DP1 becomes a signal of one line period which is phase-synchronized with the video signal at every 1V by the clear signal CR1. That is, the decode signal DP1 is the read reset signal RRT1A shown in FIGS. 3F and 4G, and is output from the terminal 303A to the read reset terminal RR of the line memory 210A. still,
Read reset signal RRT1A (FIG. 3 (f), FIG. 4 (g))
Is a signal delayed by time α from the write reset signal WRT1A (FIGS. 3D and 4E), which can be realized by adjusting the delay time τ ₁ of the delay circuit 320. That is, the initialization timing of the counter 330 can be adjusted by adjusting the delay time τ ₁ (in other words, the decode signal DP with respect to the video signal).
1 output timing can be adjusted), the read reset signal RRT1A is longer than the write reset signal WRT1A by time α.
The delay time τ ₁ may be set so that the signal becomes delayed.

As described above, the read reset signal RRT
1A is a signal that is stably generated based on the head switching signal SW (FIG. 6B) and is in phase with the video signal (FIG. 6A). Therefore, the read reset signal RRT1A
The phase relationship (time α delay) between the write reset signal WRT1A and the write reset signal WRT1A is kept stable, and the write operation and read operation of the line memory 210A can be stably performed as specified. Even if a phase variation occurs between the read reset signal RRT1A and the video signal, the time α is set to 0.5.
If it is set to H, a phase fluctuation of ± 0.5H at maximum can be allowed, so that there is no practical problem in performing the writing operation and the reading operation of the line memory 210A in a predetermined stable manner.

Returning again to FIG. 5, the count output CP1 of the counter 330 is the decoder B3 in addition to the decoder A340.
Also supplied to 41. The decoder B341 outputs the count output C
When P1 is less than or equal to a predetermined value, the decode signal DP2 (FIG. 6 (g)) is output. That is, the decoder B341 decodes until the counter 330 counts the number of clocks required to read the valid video information written in the area from address 0 to address (l-1) of the line memory 210A in FIG. It operates so as to output the signal DP2, and the decode signal DP2 is supplied to the first input terminal of the AND circuit 360.

The decode signal DP1 (that is, the read reset signal RRT1, FIG. 6 (f)) of one line cycle output from the decoder A340 is supplied to the clock terminal CLK of the counter 331. In addition, counter 331
The clear signal CR1 (FIG. 6 (d)) is supplied from the delay circuit 320 to the clear terminal CR. The clear signal CR1 causes the counter 331 to synchronize with the video signal in phase by 1V.
After the count value is initialized every time, the decode signal DP1 of one line cycle is counted. The count output CP2 of the counter 331 is supplied to the decoder C350.
Operates to output the decode signal DP3 (FIG. 6 (h)) when the count output CP2 is within the predetermined range. That is, the decoder C350 operates so as to output the decode signal DP3 while the counter 331 counts the clock (decode signal DP1) corresponding to the vertical blanking period, and the polarity of the decode signal DP3 is inverted by the inverter circuit 351. (Decode signal DP3), and the AND circuit 360
Is supplied to the second input terminal of. Further, the third input terminal of the AND circuit 360 is connected to the reference clock CK2.
(FIG. 6E) is supplied. As a result, the reference clock CK2 is gated by the decode signals DP2 and DP3, and the AND circuit 360 does not read any redundant video signal such as the vertical blanking period and the horizontal blanking period, and these redundant video signals are not read. A clock CK2 ′ (FIG. 3 (g), FIG. 4 (h), FIG. 6) that has only the minimum number of clocks necessary to read only the effective video signal excluding all video information.
(i)) is output and supplied to the terminal 304A.

The count output CP2 of the counter 331 is also supplied to the decoder D370. The decoder D370 uses the count output CP2 to decode the decode signal DP4 (FIG. 6 (j)) indicating the first valid line of each field. Is output. A
The ND circuit 380 has the decode signal DP4 and the decode signal DP1 (that is, the read reset signal RRT).
1A, FIG. 6 (f)) is supplied. Therefore, the AND circuit 38
0 indicates only the decode signal DP1 of the first valid line of each field among the above-mentioned decode signals DP1.
It is output to the terminal 306A as T2A (FIG. 6 (k)). This signal WRT2A is used as a write reset signal WRT2A for the field memory 220A (FIG. 1) described later.

An embodiment of the control circuit 300 has been described above with reference to FIGS. 5 and 6. As is clear from the above description, the control circuit 300 operates based on the head switching signal SW and the reference clock CK2 regardless of the input reproduction video signal, so that the read reset signal RRT1A and the clock CK are used.
2′A and the like can be generated extremely stably, and the reading operation of the line memory 210A can be performed extremely stably without malfunction. In the above embodiment, the head switching signal SW
However, the present invention is not limited to this, and if the signal indicating the rotational phase of the magnetic head is used instead of the head switching signal SW, the use thereof does not deviate from the gist of the present invention. ..

As is clear from the above description, from the line memory 210A of FIG. 1, based on the read reset signal RRT1A and the clock CK2'A generated as described above, the vertical blanking period or horizontal blanking period is performed. Redundant video signals such as periods are not read at all, and only valid video information excluding these redundant video information is stably read in phase synchronization with the input video signal without excess or deficiency of one sample per line. Be done.

Referring again to FIG. 1, the effective video information read from the line memory 210A as described above is supplied to the field memory 220A. The write and read operations of the field memory 220A will be described below with reference to the waveform chart for explaining the operation of FIG. In FIG.
(a) is an input reproduction video signal from the terminal 10A in FIG. 1, (b)
Is effective video information read from the line memory 210A,
(c) is a write reset signal WRT2A (FIG. 6 (k)) generated by the control circuit 300. Field memory 22
0A is a memory having a capacity capable of storing all valid video information (the number of samples L) within at least 1V, and capable of independently and asynchronously performing a writing operation and a reading operation. The read clock terminal RC of the line memory 210A is connected to the write clock terminal of the field memory 220A.
The same clock CK2'A that was supplied to K is supplied. The write reset signal WRT2A (FIGS. 6 (k) and 7 (c)) generated by the control circuit 300 is supplied to the write reset terminal WR of the field memory 220A. Therefore, the field memory 220A receives the input reproduction video signal (see FIG. 7) in response to the write reset signal WRT2A.
After the write address is initialized (preset to address 0) at the beginning of each field in phase synchronization with (a)), in phase synchronization with the input video signal, at the timing shown in FIG.
Simultaneously with reading from the line memory 210A, only the effective video information within 1V is applied to the clock CK in a predetermined address area in a signal form in which a luminance signal Y and a color signal C are time-division multiplexed.
It operates to sequentially write based on 2'A. For example, as shown in FIG. 8, it operates so as to sequentially write to the area from address 0 to address (l-1). Therefore, even if the horizontal sync signal HSA is dropped due to dropout or noise in, or the noise N is erroneously separated together with the horizontal sync signal HSA, the horizontal sync signal HSA can be
The effective video information in V can be accurately and stably written in a predetermined address area (for example, address 0 to address (l-1)).

Next, reading of the effective video information within 1V written in the field memory 220A in phase synchronization with the input video signal as described above will be described. The field memory 220A is read based on the read reset signal RRT2A and the clock CK3A supplied to the read reset terminal RR and the read clock terminal RCK, respectively. These read reset signals RRT2A and clock C
K3A is generated by the reference signal generation circuit 800. Like the control circuit 300, the reference signal generation circuit 800 is composed of a counter or the like, and appropriately divides the reference clock CK3 (frequency f ₃ ) supplied from the crystal oscillation circuit 60 ′ to obtain the read reset signal. RRT2A, clock CK
Generate 3A. The read reset signal RRT2A is a stable reference signal having a 1V cycle, as shown in FIG. 7 (e).

The video signal (FIG. 9 (a)) written in the field memory 220A has the luminance signal Y and the line-sequential color signal C time-division multiplexed. When reading from the field memory 220A, FIG. ), The luminance signal Y is compressed in the time axis, the line-sequential color signal C is expanded in the time axis, and both the luminance signal Y and the color signal C are in one line of the original video signal such as a broadband high-definition television signal. It is necessary to read during the effective video signal period of 1 to demodulate the time division multiplexed signal. Therefore, at the time of reading, as shown in FIG. 9C, when reading the line sequential color signal C, the line sequential color signal read clock CK3A ₁ is
When reading the luminance signal Y, the luminance signal reading clock C
K3A ₂ is selectively supplied to the field memory 220A as the clock CK3A. Field memory 220 here
The line sequential color signal period in one line before writing to A is t ₁
(FIG. 9A), the effective video signal period of the original wideband video signal such as a high-definition television signal after being read is t ₀
In FIG. 9 (e), since the write clock is CK2′A, the frequency f ₃₁ of the read clock CK3A ₁ of the color signal C is set to CK2′A × t ₁ / t ₀ . Similarly, assuming that the luminance signal period before writing is t ₂ (FIG. 9A), the frequency of the read clock CK3A ₂ of the luminance signal Y is CK2′A.
Set to × t ₂ / t ₀ . First, the line sequential color signal C of one line is read using the clock CK3A ₁ , and then the clock C
Switch to K3A ₂ and read the luminance signal Y for one line. At this time, by setting the frequencies of the clocks CK3A ₁ and CK3A ₂ to f ₃₁ and f ₃₂ respectively as described above, the line-sequential color signal C is time-axis expanded to t ₀ / t ₁ , and the luminance signal Y is t. It can be read from the field memory 220A after time-axis compression to ₀ / t _2, and can demodulate a time division multiplexed signal into a luminance signal Y of a wideband video signal such as a high definition television signal and a line sequential color signal C. it can. As shown in FIG. 9E, the line-sequential color signal C and the luminance signal Y are output alternately line by line. As described above, in the field memory 220A, the read address is initialized (preset to address 0) for each 1V by the read reset signal RRT2A, and then the field memory 220A of FIG.
At the timing shown in (f), the valid video information written in a predetermined address area (for example, an area from address 0 to address (L-1) as shown in FIG. 8) in synchronization with the clock CK3A. Is sequentially read, and line-sequential color signals C and luminance signals Y are alternately output for each line.
Therefore, the time-sequential conversion such as time-axis expansion and compression is performed to demodulate the time-division multiplexed signal to obtain the line-sequential color signal C of the original broadband video signal such as a high-definition television signal.
The luminance signal Y is alternately output line by line.

Although the signal processing in the channel A has been described above, the signal processing in the channel B is similarly performed. Returning to FIG. 1, the A / D conversion circuit 1B in the channel B, the synchronization information separation circuit 600B, the write clock generation circuit 500B, the control signal generation circuit 100B, and the line memory 210.
B and the field memory 220B are respectively the A / D conversion circuit 1A and the synchronization information separation circuit 600 in the channel A.
A, write clock generation circuit 500A, control signal generation circuit 1
Channel B which is the same as 00A and is supplied from the terminal 10B as described in the signal processing of channel A above.
It operates in exactly the same way for the reproduced video signal of. Therefore, the reproduced video signal of the channel B supplied from the terminal 10B is the write clock CK1B that follows the time base fluctuation of the reproduced video signal generated by the write clock generation circuit 500B.
Then, the analog signal is sequentially converted into a digital signal.
Further, in the sync information separation circuit 600B, the horizontal sync signal HSB and the vertical sync signal VS are reproduced from the reproduced video signal of channel B.
B and the burst signal BSTB are separated, and the write reset signal WRT1B is generated by the control signal generation circuit 100B based on the horizontal synchronizing signal HSB and the write clock CK1B. The reproduced video signal of channel B is sequentially written in the line memory 210B in units of one line based on the write reset signal WRT1B. The effective video information written in the line memory 210B is read in phase with the input reproduction video signal based on the read clock CK2′B (frequency f ₁ ) generated by the control circuit 300 and the read reset signal RRT1B. Done.

In the two-channel divided recording rotary drum device, the magnetic head of channel B and the magnetic head of channel A are used.
The magnetic head and the magnetic head are attached with a small angle ψ with respect to the center of the rotary drum device. Therefore, channel B
Of the magnetic head for scanning the track on the tape is later than the timing for the magnetic head of channel A to scan the track on the magnetic tape, and the reproduced video signal of channel B is smaller than the reproduced video signal of channel A by a minute angle ψ. Playback is delayed by time τ. Therefore, the control signal of channel B from the control circuit 300 also needs to be delayed by the time τ. Explaining with reference to FIG. 5, each control signal PRT
1A, CK2'A and WRT2A are delayed by a delay τ by delay circuits 390, 391 and 392, and are output as control signals PRT1B, CK2'B and WRT2B of channel B to terminals 303B, 304B and 306B, respectively.

The effective video information read from the line memory 210B is supplied to the field memory 220B, and the control circuit 3
Writing is sequentially performed based on the write clock CK2'B (frequency f ₁ ) generated at 00 and the write reset signal WRT1B. The effective video information written in the field memory 220B is read by the read clock CK3B generated by the reference signal generation circuit 800 and the read reset signal PR.
It is performed based on T2B. Field memory at this time
The video signal (FIG. 9 (b)) written in 220B includes a luminance signal Y and a line-sequential color signal C which are time-division-multiplexed. As shown in FIG. 9 (f), the luminance signal Y is compressed on the time axis, and the line-sequential color signal C is expanded on the time axis so that the luminance signal Y and the color signal C are both original video signals such as a wide-band high-definition television signal. It is necessary to read during the effective video signal period of 1 line to demodulate the time division multiplexed signal. Therefore, when reading the line sequential color signal C, as shown in FIG. 9D, when reading the line sequential color signal C, the line sequential color signal read clock CK3B
_{When 1} reads the luminance signal Y, the luminance signal read clock CK3B ₂ is selectively supplied to the field memory 220B as the clock CK3B. Like the read clock CK3A for channel A, clock CK3B has the minimum number of clocks required to read all valid video signals in 1V. Thus, the clock CK3B ₁ is the same number of clocks as the number of samples of the written valid line sequential color signal C in the field memory 220B, also the clock CK
3B ₂ has the same number of clocks as the number of samples of the effective luminance signal Y written in the field memory 220B. Here, the frequency f ₃₁ of the read clock CK3B ₁ of the color signal C is
CK as well as read clock CK3A _{1 on} channel A
Set to 2'B × t ₁ / t ₀ . Further, the frequency f ₃₂ of the read clock CK3B ₂ of the luminance signal Y is set to CK2′B × t ₂ / t ₀ like the read clock CK3A ₂ of the channel A. First, the line-sequential color signal C for one line is read using the clock CK3B ₁ , and then the luminance signal Y for one line is read by switching to the clock CK3B ₂ . At this time, by setting the frequencies of the clocks CK3B ₁ and CK3B ₂ to f ₃₁ and f ₃₂ , respectively, the line-sequential color signal C is time-axis expanded to t ₀ / t ₁ , and the luminance signal Y is t. _The time-division-compressed signal can be read from the field memory 220B after time-axis compression to ₀ / t ₂ , and the time-division multiplexed signal is demodulated into a luminance signal Y of a wideband video signal such as a high-definition television signal and a line-sequential color signal C, As shown in FIG. 9 (f), the line-sequential color signal C and the luminance signal Y of the original broadband video signal such as a high-definition television signal are output alternately line by line. The video signal thus read from the field memory 220B is supplied to the channel switching circuit 900.

The video information read from the field memories 220A and 220B in this manner is supplied to the channel switching circuit 900. As described above, the field memories 220A and 220B are connected to the channel A respectively.
And when reading the video signal of channel B,
As shown in (e) and (f), the video signals of channel A and channel B alternately output the luminance signal Y and the line-sequential color signal C,
In addition, the reading is controlled with a phase difference of one line. For this reason, the channel switching circuit 900 sequentially and selectively switches the video signals of the channel A and the channel B for each line, so that the luminance signal Y and the line synthesized by the channel combination as shown in FIGS. The color signals C can be sequentially obtained. At this time, switching is performed during the blanking period of the video signal according to the switching timing control signal CH (FIG. 9 (i)) from the reference signal generation circuit 800. Line sequential color signal C
, Which has been line-sequentially processed at the time of recording, interpolates the color signals of the lines not transmitted by the interpolation circuit 70 to restore the two original color signals Pb and Pr. The luminance signal Y and the color signals Pb and Pr thus restored are respectively D / A conversion circuit 3,
The stable reference clock CK3 supplied to
In synchronism with, the digital signal is sequentially converted into an analog signal. Therefore, it is possible to restore the original luminance signal Y and the color signals Pb and Pr from which the time division multiplexed signal is demodulated, the channels are combined, and the time base fluctuation of the input reproduction video signal is removed.

In the reference signal generation circuit 800, the reference clock CK3 is appropriately divided to divide the reference clock CK3 into an input video signal (HS, VS in FIG. 4A) and a reference synchronization signal RCS having the same format and frequency, The reference vertical synchronizing signal RVS is generated.

As described above, the field memory 220
Since only valid video information within 1V is sequentially read from the A and 220B, the horizontal synchronizing signal HS, the vertical synchronizing signal VS, the horizontal synchronizing signal HS and the vertical synchronizing signal VS are added to the video signals output from the D / A converting circuits 3, 4 and 5. Vertical blanking is not included.
Synchronous insertion adder circuit to restore the same signal form as the original wideband video signal such as high definition television signal
In 400, 401 and 402, the reference sync signal RC from the reference signal generation circuit 800 is output to the outputs from the D / A conversion circuits 3, 4 and 5.
S is added and added.

The reference vertical synchronizing signal RVS from the reference signal generating circuit 800 is output as a reference signal of a servo control device (not shown) via the terminal 50.

This servo control device controls the relative phase of the magnetic head and the magnetic tape in a magnetic recording / reproducing device such as a VTR applied to the video signal processing device based on the embodiment of FIG. It is composed of a tracking control system for correct reproduction, and a conventionally known one is used.

By inputting the reference vertical synchronizing signal RVS from the terminal 50 to the servo control device,
The input video signal from 10A is the reference vertical sync signal RV.
Servo control is performed so as to be phase-synchronized with S. More specifically, with respect to the phase of the vertical synchronizing signal of the input video signal,
Servo control is performed so that the reference vertical synchronization signal RVS is phase-synchronized with a phase delay.

By this servo control, as shown in FIG. 7E, the read operation from the field memory 220A (or the field memory 220B) is controlled to be delayed by the time β from the write operation. If the time β is set to 0.5 V, the time base fluctuation amount of the input video signal can be allowed to be ± 0.5 V at maximum with respect to the reference vertical synchronizing signal RVS, and the video signal processing apparatus according to the embodiment of FIG. Field memory 220A
(Or field memory 220B), ± 0.5V maximum
It is possible to obtain a time axis fluctuation correction amount. For this reason,
The valid video signals written in the field memories 220A and 220B are correctly read on a stable time axis with no fluctuations, even if there is no excess or deficiency of even one sample, and the blanking and synchronization information deleted are synchronously inserted and added. In circuits 400, 401 and 402, the same stable time base reference sync signal RCS as the reading is supplemented. Therefore, terminals 20, 21 and
From 22, the time-division multiplexed signal is demodulated, the channels are combined, and the stable video signal from which the time base fluctuation of the input video signal is removed is correctly restored and output.

In the above embodiment, the reference clock CK3
(f ₁ ) is individually generated by the crystal oscillation circuit 60 ′ and the reference synchronization signal RCS is generated inside the device by the reference signal generation circuit 800. This reference synchronization signal RCS is referenced from the outside. The PLL circuit shown in FIG. 10 may be used to obtain a reference clock similar to the above in order to perform synchronous coupling with the synchronization signal, which does not depart from the gist of the present invention. That is, in FIG. 10, reference numeral 800 denotes the same reference signal generation circuit as that in FIG. 1, which is denoted by the same reference numeral, is supplied with the output clock from the voltage controlled oscillator circuit 950, and is supplied with the reference synchronization signal RCS, the reference vertical synchronization signal RVS, The read reset signal RRT2 and the clock CK3 are generated. Terminal 910
A reference sync signal from the outside is input to the, and the vertical sync separation circuit 920 separates and outputs the vertical sync signal. The external reference vertical sync signal from the vertical sync separation circuit 920 and the internal reference vertical sync signal RVS from the reference signal generation circuit 800.
Are compared in phase by the phase comparison circuit 930, an error voltage corresponding to the phase difference between the two is output from the phase comparison circuit 930, and the error voltage corresponding to the voltage controlled oscillator circuit 95 is output via the phase compensation circuit 940. Output from 930, phase compensation circuit 940
Is supplied as a control voltage for the voltage controlled oscillator circuit 950. A PLL circuit is configured by the above circuits, and the internal reference vertical synchronization signal RVS from the reference signal generation circuit 800 is generated.
Is phase-synchronized with a reference vertical sync signal from the outside. An output of the same frequency (f ₃ ) as the reference clock CK3 from the crystal oscillation circuit 60 of FIG. 1 is obtained from the voltage controlled oscillation circuit 950 and output from the terminal 960. The voltage controlled oscillator circuit 950 based on the embodiment of FIG. 10 is used as the crystal oscillator circuit 60 ′ of FIG.
If used instead of, the above video signal processing device can be operated in external synchronization.

As is clear from the above description of the operation, the line memory 210A (210B) and the field memory 220A (220B) are connected in cascade for each channel, so that the line memory 210A (210B) becomes one line buffer memory. If the horizontal sync signal HSA (HSB) is dropped due to dropout or noise in, or the noise N is mistakenly separated together with the horizontal sync signal HSA (HSB), the effect is suppressed only to the line concerned. Since the operation is performed so as not to affect other lines, the entire apparatus can be operated without malfunction even if the circuit is not devised so as to compensate for the missing horizontal synchronizing signals HSA and HSB for each channel and perform predetermined signal processing. It can be operated extremely stably. Further, even in the case of multi-channel recording, it is not necessary to provide a control circuit for reading the line memories 210A and 210B of each channel and writing to the field memories 220A and 220B independently for each channel, and only one control circuit 300 can be used. Therefore, the control becomes simple and the increase in the circuit scale can be suppressed.

As is clear from the above description of the operation, the read clocks of the field memories 220A and 220B can be switched according to the type of the video signal to be read, so that the functions of demodulating the time division multiplexed signal and channel synthesis can be provided. Further, a field memory 220 capable of independently and asynchronously performing a write operation and a read operation.
By using A and 220B, it is possible to have a time axis fluctuation correction function having a time axis fluctuation correction amount of 0.5 V.

In addition, the FIFO line memories 210A and 210A
In the B, FIFO field memories 220A and 220B, the write address and the read address are automatically updated in synchronization with the clock supplied by the built-in address counter, and therefore an address generation circuit is not required as an external circuit. In addition, even if the horizontal synchronizing signals HSA and HSB are lost due to dropout or the like, it is not necessary to devise a circuit to compensate for this and perform predetermined signal processing.
Therefore, the memory control circuit can be simplified, and at the same time, the signal processing can be simplified. Further, since the FIFO type memory is generally capable of high speed writing / reading operation,
This has the effect of enabling high-speed signal processing.

Next, a dropout compensating method for compensating for video information missing due to dropout in the embodiment of FIG. 1 will be described. Although not shown, the dropout signal DOPA of the channel A generated by detecting the envelope of the reproduction high frequency (RF) signal and determining that the amplitude has dropped to a predetermined level or less is judged from the terminal 120A. Is entered.

In general, the memory has a write enable terminal WE for instructing the writing of data to the memory. For example, when the signal supplied to the write enable terminal WE is at the "L" level, the data is written. However, at the "H" level, the data is not written and the already written data is held. Therefore, basically, by supplying the dropout signal DOPA to the write enable terminal WE of the field memory 220A, the video information in which the dropout period is missing is replaced with the video information of the previous field which has already been written. Field memory without increasing the circuit scale
Dropout compensation can be done on the 220A. However, as described above, since the writing of data to the field memory 220A is performed via the line memory 210A, it is delayed by time α with respect to the input video signal. For this reason,
As shown in, the write enable terminal WE of the field memory 220A is supplied with a signal obtained by delaying the dropout signal DOP input from the terminal 120A by the delay circuit 700A by time α, so that the circuit scale is not increased. As described above, dropout compensation can be performed on the field memory 220A, and a good reproduced image can be obtained. The dropout compensation method for channel A has been described above, but the dropout compensation for channel B can be performed in exactly the same manner. That is, the channel B dropout signal DOPB supplied from the terminal 120B.
Is delayed by time α in the delay circuit 700B, and the field memory 2
It may be supplied to the write enable terminal WE of 00B. In addition, noise N caused by dropout, noise in, etc.
To the horizontal synchronization signal H by the synchronization information separation circuits 600A and 600B.
FIG. 11 shows a signal processing circuit 610 which prevents erroneous separation together with the synchronization information such as S and the vertical synchronization signal VS. Figure 1
2 is a waveform diagram for explaining the operation.

The synchronous information separation circuits 600A and 600B shown in FIG.
This is a conventionally known synchronization information separating circuit, which separates and outputs the synchronization information by comparing the amplitudes of the input video signals (FIG. 12A) with a predetermined threshold value Vr, for example. Therefore, as shown in FIG. 12A, when noise N is generated due to dropout, noise in, or the like, the synchronization information separating circuits 600A and 600B erroneously separate and output the noise N together with the synchronization information (FIG. 12).
(Dashed line in (d)). A circuit that prevents this is the signal processing circuit 610 shown in FIG.

In FIG. 11, from terminal 601 to terminal 1 of FIG.
Input playback video signal of channel A from 0A (Fig. 12 (a))
Is input and supplied to the input terminal of the buffer amplifier 605. The dropout signal DOPA (FIG. 12B) from the terminal 120A of FIG. 1 is input from the terminal 603, and is supplied to the control terminal C of the analog switch 604. Analog switch 6
The terminals a and b of 04 are the power supply Vcc and the buffer amplifier 605, respectively.
Of the dropout signal DOPA is open when the dropout signal DOPA is at "H" level and open when it is at "L" level. Therefore, if a dropout occurs, the input terminal of the buffer amplifier 605 will be the analog switch 6
Since it is connected to the power supply Vcc via 04, a buffer amplifier
The video signal output from 605 is a signal fixed to the power supply Vcc level during the dropout period, as shown in FIG. Therefore, if the output of the buffer amplifier 605 is supplied to the conventionally known synchronization information separation circuit 600A, the noise N caused by the dropout is always fixed at the power supply Vcc level even if a dropout occurs, so that the predetermined threshold value is set. Even if the amplitudes are compared by Vr, the noise N is not erroneously separated and output, and only the correct synchronization information (solid line in FIG. 12D) is separated and output from the synchronization information separation circuit 600A. As a result, the write operation of the line memory 210A of FIG. 1 is not disturbed by the noise N as described above, and the predetermined signal processing can be stably performed. Similarly, also in the channel B, the signal processing circuit 610 is connected to the synchronization information separation circuit 6
Since the line memory 210B of the channel B operates in exactly the same manner by connecting in cascade to the preceding stage of 00B, the predetermined signal processing can be stably performed without being disturbed by the noise N. And 22 can obtain a better reproduced image.

By the way, in the above embodiment, FIG.
As described above, the read reset signal RRT1A of the line memory 210A and the like are generated by the control circuit 300 based on the head switching signal SW, but may be generated based on the input reproduced video signal. That is, even if the signal VS2 obtained by dividing the vertical synchronization signal VS separated by the synchronization information separation circuit 600A in FIG. 1 by 1/2 is supplied to the terminal 301 in FIG. 5 instead of the head switching signal SW, the input video signal The read reset signal RRT1 and the like, which are phase-synchronized with, can be similarly generated.
At that time, the vertical sync signal VS is dropped due to dropout or the like.
If the signal VS2 is missing, the signal VS2
Needs to be generated. FIG. 13 shows an embodiment of a circuit 350 which compensates for the missing vertical synchronizing signal and stably generates the signal VS2. FIG. 14 is a waveform diagram for explaining the operation.

In FIG. 13, the vertical synchronizing signal VS separated and output from the terminal 351 by the synchronizing information separating circuit 600A (see FIG. 14).
(a)) is input and supplied to the leading edge detection circuit 353. The leading edge detection circuit 353 is a circuit for detecting the leading edge of the vertical synchronization signal VS, and outputs the leading edge detection signal FE shown in FIG. 14 (b). The leading edge detection signal FE becomes a clear signal CR2 (FIG. 14 (d)) via the OR circuit 365 and is supplied to the clear terminal CR of the counter 354. On the other hand, the reference clock CK2 from the crystal oscillation circuit 60 of FIG. 1 is input from the terminal 352 and supplied to the clock terminal CLK of the counter 354.

Therefore, when the vertical synchronizing signal VS is separated, the counter 354 initializes the count value at the leading edge of the vertical synchronizing signal VS by the clear signal CR2 based on the leading edge detection signal FE, and then the clock. Count CK2.
The count output CP3 of the counter 354 is supplied to the decoder E355, and the decoder E355 operates to output the decode signal DP5 (FIG. 14 (c)) when the count output CP3 reaches a predetermined value. In the decoder E355, the counter 354 is 1
When the number of clocks corresponding to the time V + Δτ ₂ (Δτ ₂ << 1V) is counted, the decode value is set to output the decode signal DP5. Therefore, when the vertical synchronization signal VS is separated, the counter 354 Since the count output CP3 of 3 does not reach the decode value, the decode signal DP5 is not output. However, when the vertical sync signal VS is missing, as shown in FIG.
The decode signal DP5 is output near the leading edge of S.
Then, the decode signal DP5 becomes a clear signal CR2 via the OR circuit 356 and is supplied to the clear terminal of the counter 354, and the counter 354 has its count value initialized by the clear signal CR2 based on the decode signal DP5. The clock CK2 is counted. Therefore, the clear signal CR2 output from the OR circuit 356 (FIG. 14 (d))
Is a signal indicating the leading edge of the vertical synchronizing signal VS, which is supplemented by the decode signal DP5 when the vertical synchronizing signal VS is missing. Therefore, if the clear signal CR2 is divided by 1/2 by the 1/2 divider circuit 357, even if the vertical synchronizing signal VS is lost due to dropout or the like, the vertical synchronizing signal V
The signal VS2 (FIG. 14 (e)) obtained by dividing S by 1/2 can be stably generated.

As is clear from the above description, the signal VS2 generated based on the vertical synchronizing signal VS of the input reproduced video signal is a signal corresponding to the head switching signal SW and is phase-synchronized with the input video signal. It is a signal. Therefore, instead of the head switching signal SW, the signal VS
Even if 2 is supplied to the control circuit 300, the read reset signal RRT1A or the like that is phase-synchronized with the input video signal can be similarly generated, which does not depart from the gist of the present invention.

Further, the memory system of the embodiment shown in FIG. 1 has a line memory 210A and a field memory 220A.
However, the present invention is not limited to this. For example, instead of the field memory 220A, a frame memory (a memory having a capacity capable of storing all valid video information in at least one frame) may be used, and this frame memory is written for each frame by a write reset signal and a read reset signal. If the write address and the read address are initialized and the read operation is performed with a time delay of β ₁ (0 <β ₁ <1 frame period, 1 frame period = 2V), the time axis fluctuation is similarly corrected. If dropout occurs, it is possible to obtain a good reproduction image that is dropout-compensated with the video information of one frame before. In this case, the video signal processing device according to the present invention has a time axis fluctuation compensating field capability of up to ± 1 V when the time β ₁ is 1 V.

In general, the memory system according to the present invention has a structure in which a 1-line memory and a memory having a capacity capable of storing N (N ≧ 2) lines of effective video information (hereinafter referred to as N-line memory) are connected in series. At this time, the write address and the read address of this N line memory are initialized for each N line by the write reset signal and the read reset signal, and the time β ₂ (0 <
β ₂ <N line, N line = N × H) If the reading operation is performed with a delay, the time axis fluctuation can be similarly corrected. When the time β _{2 is set} to N × H / 2, the maximum is obtained. ± N
It is possible to configure the video signal processing device according to the present invention having the ability to correct the time base fluctuation of × H / 2.

Further, the present invention can be similarly applied to a helical scan type segment recording type magnetic recording / reproducing apparatus which divides a video signal of one field into a plurality of tracks for recording. As a specific example, as shown in FIG. 15 (two-channel divided two-segment recording system), even when a video signal is recorded and reproduced in a recording signal format in which a segment synchronization signal is inserted at the beginning of each segment instead of the vertical synchronization signal. , Can be applied without causing any problems. At this time, as the -N line memory, a segment memory (a memory of a system having a capacity capable of storing all effective video information in at least one segment) may be used, and this segment memory is subjected to a write reset signal and a read reset signal. The write address and read address are initialized for each segment by
₃ (0 <β ₃ <1 segment period; 1 segment period = 1
If it is operated so as to be read with a delay, the time axis fluctuation can be similarly corrected, and the video signal processing device according to the present invention has a maximum ± S when the time β ₃ is S / 2. The time axis correction capability is / 2.

At this time, for example, as shown in FIG.
An original wideband video signal such as a high-definition television signal of one field of the video signal of each field is supplied to each channel A (see FIG.
15 (a)) and channel B (FIG. 15 (b)), each channel is further divided into two segments, and the first segment of channel A has the first line of the original video signal,
The fifth line, the ninth line, ..., The second segment of the original video signal, the sixth line,
The 10th line ..., The second segment of channel A has the 3rd line, 7th line, 11th line of the original video signal.
, And the second segment of channel B, even if the video signal is recorded and reproduced in a recording signal format in which the fourth line, the eighth line, the twelfth line of the original video signal are arranged. The invention can be applied without causing any problems.

That is, for example, the field memory 220A of the channel A and the field memory 220B of the channel B of FIG. 1 are respectively stored in the first segment memory and the signal of the second segment for storing the signal of the first segment as shown in FIG. And a second segment memory for storing The signal of each segment is stored in the line memories 210A and 2A.
Through the 10B, the changeover switches 911 and 912 are used to change over each segment, and the data is written in a predetermined address area of the corresponding segment memory in segment units. At this time, the first line, the fifth line, the ninth line of the original video signal (luminance signal Y, color signal C) ... (FIG. 17 (a)) are stored in the first segment memory 220A ₁ of the channel A. Channel A second
3rd line, 7th line, 11th line ... (Fig. 17 (b)) of the original video signal in the segment memory 220A _{2 of the same,} and the original video signal in the first segment memory 220B ₁ of the channel B. 2nd line, 6th line, 10th line ... (Fig. 17
(c)) to the second segment memory 220B ₂ of channel B
The fourth line, the eighth line, the twelfth line, ... (Fig. 17 (d)) of the original video signal are sequentially written in. And channel A
From the first segment memory of channel A, the second segment memory of channel A, the first segment memory of channel B, and the second segment memory of channel B (FIG.
(e)), (FIG. 17 (f)), (FIG. 17 (g)), and (FIG. 17 (h)) are read. Data read by channel A (Fig. 17
(e)) and (FIG. 17 (f)) are shown in FIG.
Each line is sequentially selected by the segment switching signal SEA as shown in (i), and the luminance signal Y and the color signal C are alternately output every line as shown in FIG. 17 (k). Similarly, the data (FIG. 17 (g)) and (FIG. 17 (h)) read from channel B are sequentially selected line by line at the changeover switch 922 by the segment changeover signal SEB as shown in FIG. 17 (j). Figure
As shown in 17 (l), the luminance signal Y and the color signal C are output alternately line by line. Next, using the channel switching circuit 900, see FIG.
By performing the channel switching by the channel switching signal CH as shown in (m), the signals of each line can be returned to the original order and the original video signal can be restored as shown in (n) and (o) of FIG. .. In addition, like the non-segment recording method, the functions of time-division multiplexed signal demodulation, channel synthesis, and time-axis fluctuation correction can be combined without increasing the circuit scale, and the entire device operates extremely stably in any case. be able to.

Furthermore, the memory system (the above line memory, N line memory) in the present invention is not limited to the FIFO type memory, and any type of R type memory can be used.
The use of AM does not depart from the spirit of the present invention. In this case, for example, by the address control circuit,
By controlling the address of the memory and writing to and reading from the memory, a device similar to the above embodiment can be constructed. Specifically, in FIG. 1, the line memories 210A and 210B and the field memories 220A and 220B are configured by a general RAM, and the control signal generation circuits 100A and 100B are included.
The address signal may be generated by each of the control circuit 300 and the reference signal generation circuit 800. At this time, the control signal generation circuits 100A and 100B generate write address signals for the line memories 210A and 210B and supply them to the write address control terminals of the line memories 210A and 210B. The control circuit 300 generates read address signals for the line memories 210A and 210B and write address signals for the field memories 220A and 220B, and controls read address control terminals for the line memories 210A and 210B and write address control for the field memories 220A and 220B, respectively. Supply to the terminal. The reference signal generation circuit 800 generates read address signals for the field memories 220A and 220B and supplies the read address signals to the read address control terminals of the field memories 220A and 220B. The generation of the address signal will be specifically described below.

In the control signal generation circuit 100A shown in FIG. 1, a specific embodiment for outputting an address signal is shown in FIG.
Shown in. The clock terminal of the counter 101 is supplied with the write clock CK1A output from the write clock generation circuit 500A of FIG. Further, the reset terminal CR of the counter 101 is supplied with the horizontal sync signal HSA output from the sync information separation circuit 600A of FIG. The horizontal synchronizing signal H
Since SA is a signal for every 1H that is phase-synchronized with the reproduced video signal, the counter 101 is phase-synchronized with the video signal by this horizontal synchronization signal HSA and the count value is initialized every 1H, and then the reference clock is used. Count CK1A and count output C
Output P0. The coefficient output CP0 of the counter 101 is supplied to the address control terminal of the line memory 220A as a write address signal of the line memory 210A. The video signal is written to the line memory 220A based on the write address signal CP0 and the write clock CK1A.
The same applies to channel B.

FIG. 19 shows a specific example of generating the address signal in the control circuit 300 shown in FIG. Figure
19 is partly common to FIG. 5, and the common parts are denoted by the same reference numerals and detailed description thereof will be omitted. The operation of the circuit shown in FIG. 19 will be described below.

In FIG. 19, a terminal 301 is an input terminal for the head switching signal SW, a terminal 302 is an input terminal for the reference clock CK2, and the reference clock CK2 and the head switching signal SW are the reference clock CK2 and the head switching signal SW in FIG. Is the same as The reference clock CK2 input from the terminal 302 is the read / write clock C as it is.
It is supplied to the terminal 304A as K2'A. The head switching signal SW input from the terminal 301 is applied to the double-edge detection circuit 310.
And outputs the both-edge detection signal EP. The both-edge detection signal EP is delayed by the delay circuit 320 for a predetermined time τ ₁ and supplied to the clear terminal CR of the counter 330 as the clear signal CR1. By adjusting the above delay time τ ₁ ,
The initialization timing of the counter 330 can be adjusted. On the other hand, the reference clock CK2 is supplied to the clock terminal CLK of the counter 330. Since the clear signal CR1 is a signal for each 1V which is phase-synchronized with the reproduced video signal, the counter 330 is phase-synchronized with the video signal by the clear signal CR1 and is counted for each 1V (1V: 1 vertical scanning line period). After the numerical value is initialized, the reference clock CK2 is counted and the count output CP1 is output. The coefficient output CP1 of the counter 330 is the read address signal RA of the line memory 210A.
1A is supplied to the terminal 307A. Line memory 210A
Is read in phase synchronization with the video signal based on the read clock CK2'A and the address signal RA1A.

The output CP1 is supplied to the decoder 340. The decoder 340 operates to output the decode signal DP1 when the count output CP1 reaches a predetermined value. The decoder 340 has a decode value set so as to output the decode signal DP1 when the counter 330 counts the number of clocks corresponding to one line, and the decode signal DP1 is supplied to the preset terminal LD of the counter 330. The counter 330 presets the count value to a predetermined set value by the decode signal DP1 supplied to the preset terminal LD, and then counts the reference clock CK2 supplied to the clock terminal CLK again. If the set value is set to zero, the counter 330 is set to 1 by the clear signal CR1.
After the count value is initialized for each V, the decode signal D
P1 operates to preset the count value to a set value (zero) in one line cycle. Therefore, the decode signal D
P1 becomes a signal of one line period which is phase-synchronized with the video signal for each 1V by the clear signal CR1.

The decode signal DP1 of one line cycle output from the decoder 340 is supplied to the clock terminal CLK of the counter 331. In addition, the clear signal CR from the delay circuit 320 is applied to the clear terminal CR of the counter 331.
1 is supplied. The counter 331 uses this clear signal CR1
As a result, the count value is initialized every 1 V in phase synchronization with the video signal, and then the decode signal DP1 of one line cycle is counted and the count output CP2 is output. Therefore, the coefficient output CP2 is a signal indicating the line address in the field, and is combined with the address signal CP1 in the line to be the signal CP3, which is supplied to the terminal 308A as the write address signal WR2A of the field memory 220A.
Writing into the field memory 220A is performed in phase synchronization with the video signal based on the read clock CK2'A and the address control signal WR2A.

As in the case of using the FIFO memory, the reproduced video signal of channel B is reproduced with a delay of time τ from the reproduced video signal of channel A. Therefore, the control signal of channel B from the control circuit 300 also needs to be delayed by the time τ. Explaining with reference to FIG. 19, each control signal RA1A, CK2′A and WA2A is delayed by τ.
Only by the delay circuits 390, 391 and 392, and the read address control signal R of the channel B line memory 210B is delayed.
A1B, clock CK2'B and field memory 220
As the write address WA2B of B, the terminals 307
B, 304B and 308B, line memory 210B
Is read and the field memory 220B is written.

Next, as described above, the effective video information within 1V written in the field memory 220A in phase synchronization with the input video signal is read by the read address signal RA2A,
It is performed based on the clock CK3A. The read address signal RA2A and the clock CK3A are generated by the reference signal generation circuit 800. Like the control circuit 300, the reference signal generation circuit 800 is composed of a counter or the like, and appropriately counts and divides the reference clock CK3 supplied from the crystal oscillation circuit 60 'to obtain the read address signal RA2A and the clock. Generate CK3A. Similarly, for the channel B, the read address signal RA2B and the clock CK3B are generated and the field memory 220B is read.

The specific embodiment of generating the address signal has been described above with reference to FIGS. 18 and 19. As is clear from the above description, the control circuit 300 controls the head switching signal SW and the reference clock CK2 regardless of the input reproduction video signal.
Read address signal RA1A,
RA1B and write address signals WA2A, WA2B
Etc. can be generated extremely stably, and the line memory 21
The reading and writing operations of 0A, 210B and 210A, 210B of the field memory can be performed extremely stably without malfunction. Although the head switching signal SW is used in the above-described embodiment, the present invention is not limited to this, and any signal indicating the rotational phase of the magnetic head may be used instead of the head switching signal SW. It does not depart from the gist of the present invention.

[0077]

As described above, according to the present invention, a line memory and an N line memory are connected in cascade for each channel, and line memory writing is controlled independently for each channel.
By performing line memory reading and N line memory writing and reading by a control circuit common to each channel, stable operation is possible without malfunction even if the sync signal is lost during dropout occurrence or variable speed reproduction, Simple and high-speed signal with a small circuit scale that has a sufficient amount of time-axis fluctuation correction, performs time-division multiplexed signal demodulation by compressing and expanding the luminance signal and chrominance signal respectively, and also performs channel synthesis. A processable video signal processing device can be configured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining a form of an input signal according to the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the embodiment according to the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the embodiment according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a control circuit according to the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the control circuit.

FIG. 7 is a waveform diagram for explaining the operation of the embodiment according to the present invention.

FIG. 8 is a diagram showing a written state of the memory according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating the operation of the exemplary embodiment of the present invention.

FIG. 10 is a block diagram showing another embodiment for operating the video signal processing device of the present invention in external synchronization.

FIG. 11 is a block diagram showing an embodiment of a signal processing circuit for preventing noise N from being mistakenly separated in the synchronization information separation circuit in the embodiment according to the present invention.

FIG. 12 is a waveform diagram for explaining the operation of the signal processing circuit.

FIG. 13 is a block diagram showing another embodiment of the control circuit.

FIG. 14 is a waveform diagram for explaining the operation of the control circuit.

FIG. 15 is a schematic diagram showing another video signal format according to the present invention.

FIG. 16 is an example of another video signal format according to the present invention.

FIG. 17 is a waveform diagram for explaining the operation of the embodiment in another video signal format according to the present invention.

FIG. 18 is a block diagram showing an embodiment of a control circuit according to the present invention.

FIG. 19 is a block diagram showing an embodiment of a control circuit according to the present invention.

[Explanation of symbols]

 1A, 1B ... A / D conversion circuit 3, 4, 5 ... D / A conversion circuit 210A, 210B ... Line memory 220A, 220B ... Field memory 300 ... Control circuit 500A, 500B ... Write clock generation circuit 800 ... Reference signal generation circuit .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masakazu Hamaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Hitachi Media Imaging Laboratory

Claims (5)

[Claims] 1. A video signal recording / reproducing apparatus for time-division-multiplexing a luminance signal and a chrominance signal of an input signal and dividing a video signal of one field into M (M is an integer of 2 or more) channels for recording. First memory means (210A, 210B) for each channel having a capacity capable of accumulating video information of one line of the input video signal and capable of asynchronously writing and reading the input video signal
And a capacity for accumulating video information of N (N is an integer of 2 or more) lines of the input video signal, and the first memory means (210
A, 210B) second memory means (220A, 220B) for each channel capable of asynchronously writing and reading the video signal, and each channel for separating the synchronization information contained therein from the input video signal Synchronization information separation means (600A, 600B)
And a first clock generation means for each channel for generating a clock of a predetermined frequency synchronized with the input video signal based on the synchronization information for each channel separated by the synchronization information separation means (600A, 600B). 500A, 500B), the first clock for each channel generated by the first clock generating means (500A, 500B) and the synchronization for each channel separated by the synchronization information separating means (600A, 600B). First control means (100A, 100B) for each channel that generates a predetermined first control signal based on information, second clock generation means (60) that generates a clock of a predetermined frequency, and A second clock generating means (60) for generating a predetermined second control signal based on the second clock generated by the second clock.
Control means (300), third clock generation means (60 ') for generating a clock of a predetermined frequency, and reference signal generation means (800) for generating a predetermined reference signal based on the third clock. A switching circuit (900) capable of performing channel switching in arbitrary units based on a third control signal generated by the reference signal generating means (800), and the input video signal for each channel is Writing to a predetermined address area of the first memory means (210A, 210B) sequentially according to the first control signal, and to a predetermined address area of the first memory means (210A, 210B) according to the second control signal. The written video signal is sequentially read, and the read video signal is sequentially written in a predetermined address area of the second memory means (220A, 220B) in accordance with the second control signal to perform the third control. The second memory means according to a signal
(220A, 220B) Sequentially reading the video signal written in the predetermined address area to correct the time base fluctuation and
A video signal processing device characterized in that the time-division-multiplexed luminance signal and chrominance signal are returned to the original signals on the time axis, and channel switching is performed by a switching circuit (900). 2. The second control means (300), by injecting a signal representing the rotational phase of the signal detection medium,
The video signal processing device according to claim 1, wherein the video signal processing device is configured to generate the second control signal in phase synchronization with the signal. 3. The configuration according to claim 1, wherein the second control means (300) is configured to generate the second control signal by injecting the separated synchronization information in phase synchronization with the synchronization information. The described video signal processing device. 4. Dropout detection means for each channel for detecting the occurrence of dropouts, and signal processing for each channel that makes the input video signal a signal of a predetermined level according to the output from the dropout detection means. The video signal processing device according to claim 1, further comprising: means (610), wherein an output from the signal processing means (610) is used as an input video signal of the synchronization information separating means (600). 5. A delay means (700) for each channel that delays the output from the dropout detection means for a predetermined time, and the first memory means (210) is provided by the output from the delay means (700). The video signal processing apparatus according to claim 1, wherein writing of a video signal read from the second memory means (220) is controlled.