JPH07219745A - Data conversion circuit and its conversion method - Google Patents

Abstract

PURPOSE:To provide a data conversion method by which the chip area of a semiconductor integrated circuit device is not increased. CONSTITUTION:In data conversion circuit/data conversion method, plural data latch circuits 7 connected to a common line 3 through switching elements 5 whose opening/closing are controlled by a switch controller 9 are provided, one of the switching elements 5 is sequentially set to a closed state in synchronizing with the bit transfer period of serial data and the signal of the common data line 3 is latched or latch data is outputted to the common data line 3 according to whether the data latch circuit 7 connected to the switching element 5 in the closed state is in an input operation or an output operation. Thus, the data conversion circuit can be constituted by the element of a small circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion circuit in a semiconductor integrated circuit device for serially inputting / outputting data to / from an external device and internally processing the data in parallel, and a conversion method thereof. It is a thing.

[0002]

2. Description of the Related Art There are many semiconductor integrated circuit devices such as a serial memory that input / output data to / from an external device serially and internally process the data in parallel.

In such a semiconductor integrated circuit device, an operation of converting input serial data into parallel data or converting internal parallel data into serial data and outputting the serial data is performed. It is essential to have a parallel-serial data conversion circuit.

Since such a data conversion circuit is a mere logic circuit, there are many kinds of details of the circuit system. However, conventionally, the basic conversion method is common to any conversion circuit. Yes, something like this:

That is, in the case of input, after serial data is stored in the shift register bit by bit, the output of each bit of the shift register is collectively transferred to the internal circuit as parallel data, and in the case of output, the internal parallel data is output. Is stored in the shift register all at once and then output as serial data bit by bit.

In other words, in both input and output,
The use of shift registers is the basis of data conversion. FIG. 3 is a block circuit diagram showing a configuration based on the data conversion method in the conventional example.

FIG. 3 shows an example of a serial memory, and the input / output terminal 1 is connected to a command shift register 25, an address shift register 27 and a data shift register 29. The command shift register 25 is connected to the command decoder 11, the address shift register 27 is connected to the address decoder 13, and the data shift register 29 is connected to the data selector 15.

The command decoder 11 is connected to all three shift registers in order to control the operation of the three shift registers. Further address decoder 1
3 and the data selector 15 are directly connected to the memory 17.

The data conversion method in the conventional example shown in FIG. 3 will be described below. Command data is input from the input / output terminal 1, data is stored in the command shift register 25 bit by bit, and when all the command data is input, the data stored in the command shift register 25 is
The data is collectively transferred to the command decoder 11.

The command decoder 11 decodes the command data, and if the command is a read command, the command decoder 11 sends a serial data acceptance signal to the address shift register 27 to send the address data from the input / output terminal 1 to the address shift register. The data stored in the address shift register 27 is stored at 27
The data is collectively transferred to the address decoder 13.

Next, the information stored in the memory 17 is read into the data selector 15, and the data shift register 29 is collectively read.
The data shift register 29 outputs the stored information to the input / output terminal 1 bit by bit.

As described above, in the read instruction, the command shift register 25 converts the command serial data into parallel data, the address serial data is converted into parallel data by the address shift register 27, and the storage information in the memory 17 is parallelized. The data shift register 29 converts the data into serial data.

Although the read instruction has been described above as an example, the data conversion by the shift register is the same for other instructions, and detailed description thereof will be omitted.

FIG. 4 is a circuit diagram of a data flip-flop which constitutes a shift register used by the command shift register 25, the address shift register 27 and the data shift register 29 shown in FIG.

The data flip-flop of FIG. 4 has four transmission gates 41, two 2-input NAND circuits 42, two inverters 43, and a reset terminal R.
B, a data input terminal D, a clock terminal O, a clock terminal OB which is an inverted output of the clock terminal O, and an output terminal Q.

One such data flip-flop corresponds to one bit of data in the shift register. Therefore, in order to configure the shift register, as many data flip-flops as the number of data to be processed in parallel are required.

The command shift register 25 shown in FIG.
The description of the clock terminals of the address shift register 27 and the data shift register 29 is omitted.

[0018]

The data flip-flop shown in FIG. 4 is an example corresponding to the minimum circuit scale as a circuit constituting a shift register, but it is still constituted by a large number of transistors. A shift register using a large number of such data flip-flops has a large circuit scale.

Therefore, when the circuit configuration of FIG. 3 is to be configured by a semiconductor integrated circuit device, there is a problem that the chip area is increased.

An object of the present invention is to solve the above problems and to provide a data conversion circuit and a conversion method thereof that do not increase the chip area of a semiconductor integrated circuit device.

[0021]

In order to achieve the above object, the data conversion circuit according to the present invention has the following configuration.

That is, one common data line connected to the input / output terminal, a plurality of switching elements connected to this common data line, a data latch circuit connected to each switching element, and these switching elements. A switch controller for controlling opening / closing is provided.

The data conversion method according to the present invention is the method described below.

That is, in synchronism with the bit transfer cycle of serial data, one of the switching elements is sequentially closed by a signal from the switch controller, and at the same time, the switching element is switched depending on the data input operation or the data output operation. Is closed, the data latch circuit connected to the switching element latches the signal on the common data line and outputs the latched data to the common data line.

Further, even if the number of data to be processed in parallel is very large, the data conversion circuit according to the present invention has the structure described below in order to perform the data conversion at high speed.

That is, at least one common output data line connected to the input / output terminal, at least one buffer circuit having its input connected to this input / output terminal, and at least one buffer circuit connected to the output of this buffer circuit. Input common data line, multiple switching elements connected to these output common data line and input common data line, data latch circuit connected to each switching element, and control of opening and closing of these switching elements And a switch controller that operates.

The data conversion method in this configuration is the method described below.

That is, in synchronism with the bit transfer cycle of serial data, one of the switching elements is sequentially closed by a signal from the switch controller, and at the same time, depending on whether the data input operation or the data output operation is performed, the switching element is switched. The data latch circuit connected to the switching element latches the signal on the input common data line and outputs the latched data to the output common data line while the switch is in the closed state. And

[0029]

In the data conversion method according to the present invention, the data conversion is not collectively performed, but which data latch circuit is connected to the common data line is controlled by selecting the switching element to be closed by the switch controller. , The data latch circuit connected to the common data line latches the signal on the common data line during the input operation, and outputs the latched data to the common data line during the output operation, thereby substantially serializing -Parallel or parallel-serial data conversion is performed.

[0030]

[Embodiment 1] Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.
Will be described in detail. First Embodiment FIG. 1 is a block circuit diagram showing a circuit configuration based on a data conversion method according to a first embodiment of the present invention.

As shown in FIG. 1, one common data line 3 is connected to the input / output terminal 1, and switching elements 5 corresponding to the number of parallel data are connected to the common data line 3, and each switching element is connected. A data latch circuit 7 is connected to each of 5. Then, the data latch circuit 7 is connected to the command decoder 11, the address decoder 13, and the data selector 15, respectively. Address decoder 1
3 and the data selector 15 are directly connected to the memory 17. The switch controller 9 outputs the switch control signal S and controls the opening and closing of the switching element 5.

In the example shown in FIG. 1, the command is 3 bits,
Each of the address and the data has a structure of 8 bits, and the total number of the switching elements 5 and the data latch circuits 7 is 19, respectively.

Next, the operation of the circuit shown in FIG. 1 will be described.

In FIG. 1, when command data is input from the input / output terminal 1 to the common data line 3 bit by bit,
At the input of the first bit, the switch controller 9 closes the first switching element 5 so that the first data latch circuit 7 connected to the command decoder 11 latches the data.

Next, at the time of the second bit, the switch controller 9 opens the first switching element 5 and closes the second switching element 5, so that the second data latch circuit 7 is connected to the common data line 3. Latch the data. At the time of the third bit, the switch controller 9 opens the second switching element 5 and closes the third switching element 5, whereby the third data latch circuit 7 latches the data on the common data line 3. .

When all the command data are input, the third switching element 5 is opened and the command data input to the command decoder 11 is replaced with the command data latched by the three data latch circuits 7. .

The command decoder 11 decodes the input command data, and if the command is a read command, the command decoder 11 will switch the switch controller 9
Send a read operation signal to. Then, every time the address data is input from the input / output terminal 1 to the common data line 3 bit by bit, the switch controller 9 sends the switch control signal S from the first address between the address decoder 13 and the common data line 3. The opening / closing of the eighth switching element 5 is controlled.

The first to eighth data latch circuits 7 connected to the address decoder 13 latch the address data in order, and when the address data are all input, the eighth switching element 5 is opened and the address decoder The data of 13 is replaced with the data latched by the eight data latch circuits 7.

Next, the information stored in the memory 17 is read by the data selector 15, and the data is latched by the eight data latch circuits 7 connected to the data selector 15,
The switch controller 9 sends a switch control signal S and outputs 1 between the data selector 15 and the common data line 3.
Controls the opening and closing of the 8th to 5th switching elements 5,
The data latched by the eight data latch circuits 7 is
The data is sequentially output from the first data latch circuit 7 to the common data line 3.

As described above, in the input / output terminal 1 for inputting / outputting with the external device, data processing is always serial, while the command decoder 11 and the address decoder 13 are used.
In such internal circuits, since data processing is performed in parallel, it is obvious that data conversion can be substantially performed by a configuration in which a switching element and a data latch circuit are combined as shown in FIG.

The read instruction has been described above as an example, but it is clear that other instructions can also be used for data conversion using the configuration shown in FIG. 1, and detailed description thereof will be omitted.

As described above, in the data conversion method according to the present invention, the data conversion is not performed all at once, but the data latch circuit for exchanging data with the common data line 3 is selected.
This is performed by the switch controller 9 selecting which switching element is to be closed, thereby substantially performing data conversion.

An alternative to the shift register used in the conventional example is the combination of the switching element and the data latch circuit in the present invention. FIG. 5 is an example showing a switching element and a data latch circuit used in the present invention.

The circuit configuration of FIG. 5 is composed of one transmission gate 51, two inverters 52, a clock terminal O, a clock terminal OB which is an inverted output of the clock terminal O, and an output terminal Q. .

As is clear from the comparison between FIG. 4 and FIG. 5, the switching element and the data latch circuit have a much smaller circuit scale than the shift register. Therefore, by using the data conversion method of the present invention, It is possible to prevent the chip area of the integrated circuit device from increasing.

The description of the clock terminal in FIG. 1 is omitted.

[0047]

Second Embodiment A second embodiment of the present invention will be described below with reference to the drawings.
Will be described in detail. FIG. 2 is a block circuit diagram showing a circuit configuration based on the data conversion method according to the second embodiment of the present invention.

As shown in FIG. 2, the output common data line 23 and the input of the buffer circuit 19 are connected to the input / output terminal 1, and the input common data line 21 is connected to the output of the buffer circuit 19.
Connect.

The input common data line 21 is connected in parallel with eight circuit means for connecting the switching element 5 and the data latch circuit 7 in series to be connected to the input circuit A31, and further connected to another switching element 5. Eight circuit means for connecting the data latch circuit 7 in series are connected in parallel and connected to the input circuit B33.

The output common data line 23 is connected in parallel with eight circuit means for connecting the switching element 5 and the data latch circuit 7 in series to be connected to the output circuit C35, and further connected to another switching element 5. Eight circuit means for connecting the data latch circuit 7 in series are connected in parallel and connected to the output circuit D37.

The switch controller 9 controls opening / closing of all the switching elements 5.

This structure has the common data line 3 in FIG.
Is output by the buffer circuit 19 to the common data line 23 for output.
And the input common data line 21 are separated, and the signal is exactly the same as when there is only one common data line. Other configurations are basically the same as in FIG.

Therefore, the operation of serial-parallel data conversion in FIG. 2 is basically the same as that in FIG.
Detailed description thereof will be omitted.

The description of the clock terminal in FIG. 2 is omitted.

The advantage of the configuration in FIG. 2 is that by separating the common data line for input and output, the data line 1
Since the stray capacitance per line is reduced, the load on the drive circuit for the data line is reduced, and the speed of data conversion can be increased.

Although the present invention has been described in detail with reference to the embodiments shown in FIGS. 1 and 2, the present invention is not limited to the embodiments shown in FIGS. 1 and 2, and various modifications are possible without departing from the spirit of the present invention. Needless to say, it is possible to change.

For example, in FIG. 2, there is one input common data line and one output common data line.
Increase the number according to the number of input circuits and output circuits,
The stray capacitance may be further dispersed to increase the speed.

Whatever the change, if a data conversion method using a combination of a switching element and a data latch circuit is used instead of the conventional shift register,
It is possible to prevent an increase in the chip area of the semiconductor integrated circuit device.

[0059]

As described above, by adopting the data conversion method using the data latch circuit connected to the common data line through the switching element, it becomes possible to configure the data conversion circuit with an element having a small circuit scale. Therefore, the increase of the chip area of the semiconductor integrated circuit device can be prevented, and the effect is very large.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a circuit configuration based on a data conversion method according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a circuit configuration based on a data conversion method according to a second embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a circuit configuration based on a data conversion method in a conventional example.

FIG. 4 is a circuit diagram of a data flip-flop that constitutes a shift register used in a conventional data conversion circuit.

FIG. 5 is a circuit diagram of a switching element and a data latch circuit used in the embodiment of the present invention.

[Explanation of symbols]

 1 I / O terminal 3 Common data line 5 Switching element 7 Data latch circuit 9 Switch controller

Claims (4)

[Claims] 1. A common data line connected to an input / output terminal, a plurality of switching elements connected to the common data line, a data latch circuit connected to each of the switching elements, and a switching element for each of these switching elements. A data conversion circuit comprising: a switch controller that controls opening and closing. 2. A single common data line connected to an input / output terminal, a plurality of switching elements connected to the common data line, a data latch circuit connected to each of the switching elements, and a switching element of these switching elements. It is equipped with a switch controller that controls opening and closing, and in synchronization with the bit transfer cycle of serial data, one of the switching elements is sequentially closed by a signal from the switch controller, and at the same time, whether data input operation or output operation is performed. Accordingly, while the switching element is in the closed state, the data latch circuit connected to the switching element may latch the signal on the common data line or output the latched data to the common data line. Characteristic data conversion circuit conversion method. 3. At least one output common data line connected to an input / output terminal, at least one buffer circuit connecting an input to this input / output terminal, and at least one buffer circuit connected to an output of this buffer circuit. An input common data line, a plurality of switching elements connected to these output common data line and input common data line, and a data latch circuit connected to each of the switching elements,
A data conversion circuit comprising: a switch controller that controls opening and closing of these switching elements. 4. At least one output common data line connected to an input / output terminal, at least one buffer circuit having an input connected to this input / output terminal, and at least one buffer circuit connected to the output of this buffer circuit. An input common data line, a plurality of switching elements connected to these output common data line and input common data line, and a data latch circuit connected to each of the switching elements,
A switch controller that controls the opening and closing of these switching elements is provided, and at the same time, one of the switching elements is sequentially closed by a signal from this switch controller in synchronization with the bit transfer cycle of serial data, and at the same time, data input. Depending on the operation or output operation, while the switching element is in the closed state, the data latch circuit connected to the switching element latches the signal on the input common data line or outputs the latched data for output. A conversion method for a data conversion circuit, which outputs to a common data line.