JP2000036738A - Rewritable logic circuit and latching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rewritable logic circuit which uses not a transfer gate switch, but a reconstitutable wiring logic element. SOLUTION: Cells 1 are connected through signal paths Pw, Pn, Pe, and Ps, and have rewritable logic memories Mw, Mn, Me, and Ms having a tristate output function, set the signal paths for input or output, when the tristate output function is set, and read previously stored values out of the logic memory by accessing the memory by using as addresses values inputted through the signal path set for input, thereby outputting them to the signal path set for output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reconfigurable wiring logic element (FPGA: Field Programmable Gate Array).
And a latch circuit configured using the logic circuit.

[0002]

2. Description of the Related Art In a conventional reconfigurable wired logic element, even when a logic memory is used to realize a logic function, these logic functions are interconnected by transfer gate switches arranged between signal lines. On / off. That is, a logic circuit is realized by a combination of different types of the logic memory and the transfer gate switch.

[0003]

However, the logic memory and the transfer gate switch have completely different structures, which hinders further high integration and improvement in flexibility.

The present invention has been made in view of the above points, and a first object of the present invention is to realize logic gates necessary for realizing a logic circuit and their connections with a structure as uniform as possible. An object of the present invention is to provide a rewritable logic circuit that solves the problem. A second object is to provide a latch circuit using this logic circuit.

[0005]

According to a first aspect of the present invention, there is provided a logic circuit comprising a plurality of cells connected to an adjacent cell by a signal path, wherein each of the cells comprises a corresponding one of the cells. Means for setting the signal path connected to the input or the output for the input, and each cell has a rewritable logic address as a value input through the signal path set for the input as an address. , The value stored in advance is read and output to the signal path set for the output.

In a second aspect of the present invention, in the first aspect, the means for setting the signal path for input or output is realized by a tristate output function of the logic memory.

A latch circuit according to a third aspect of the present invention includes the first or second latch circuit.
The address values of the first and second logic memories each composed of two logic memories of the logic circuit according to the invention of the present invention are set to two-input NO.
R, and connect the first input of each of the first and second logic memories to a separate signal path set for input, and connect the second input of the first logic memory to the Connecting to the signal path set for the output of the second logic memory,
The second input of the logical memory is connected to a signal path set for the output of the first logical memory.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a diagram showing a basic configuration of a cell structure of the present invention, FIG. 2 is a diagram showing an example in which a plurality of cells 1 of FIG. 1 are arranged, FIG. 3 is a diagram showing the configuration of the logical memory.

The cell 1 shown in FIG. 1 has a total of four adjacent cells, one for each of the four directions named w, n, e, and s. For example, cell 1A in FIG.
It has four neighboring cells C, 1D and 1E. The cell 1 has four signal paths Pw, Pn, Pe, and Ps for connecting to each adjacent cell. The signal path Pw can function as an output signal path for the logic memory Mw, and can function as an input signal path for the other logic memories Mn, Me, and Ms. The signal path Pn serves as an output signal path for the logical memory Mn, and the other logical memories Me, Ms,
It can serve as an input signal path for Mw. The signal path Pe can serve as an output signal path for the logic memory Me and an input signal path for the other logic memories Ms, Mw, Mn. Signal path Ps
Can function as an output signal path for the logical memory Ms and as an input signal path for the other logical memories Mw, Mn, and Me.

Each of the logic memories Mw, Mn, Me, Ms has a tri-state output function of turning on / off (enable / disenable) an output to the corresponding signal path Pw, Pn, Pe, Ps. By turning on the output function, an address can be specified by input from three signal paths other than the signal path set for output. In other words, the logical memory Mw includes the signal paths Pn, Pe,
With the input value from Ps, the logical memory Mn is stored in the signal paths Pw, Pw.
e, the input values from Ps, the logical memory Me
w, Pn, Ps, and the logical memory Ms
Are input values from the signal paths Pw, Pn, and Pe, and each can set an address.

Then, each of the logical memories Mw, Mn, Me,
Ms can read out a value stored in advance in the storage element at the designated address, and determines whether or not to output the value to the corresponding signal path by turning on / off the tristate output function. Can be set. That is, whether to output the output of the logical memory Mw to the signal path Pw, whether to output the output of the logical memory Mn to the signal path Pn, whether to output the output of the logical memory Me to the signal path Pe, Whether to output the output of the logic memory Ms to the signal path Ps can be individually set.

Since each of the logical memories Mw, Mn, Me, Ms has the same configuration, the internal configuration of the logical memory Me will be described as a representative here. This logical memory Me is shown in FIG.
, A selector 2 that performs a switching operation using a signal from the signal path Pn, selectors 3 and 4 that perform a switching operation using a signal from the signal path Pw, and selectors 5 and 5 that perform a switching operation using a signal from the signal path Ps. 8 and a tri-state buffer 9 for realizing the above-described tri-state output function of determining whether to output the output of the selector 2 to the signal path Pe. Further, 8-bit data to be selected by the selectors 2 to 8 is written to the storage elements 10 to 17, and 1-bit data for setting on / off of the tristate buffer 9 is written to the storage element 18. That is, 9-bit data is written in the logical memory Me. In the writing of the 9-bit data, each of the storage elements 10 to 18 is configured as a shift register, and is sequentially shifted from the storage element 10 and written. For example, when the output of the tri-state buffer 9 is set to ON and the data to be selected by the selectors 2 to 8 is set to “0”, “0000000001” may be set in the shift register. , A bit string “10000000” is sent. In this way, the required number of signal lines can be reduced.

The selectors controlled by the signals on the signal paths Pn, Pw, and Ps are not limited to the above combinations. The signal on the signal path Pn controls the selectors 3 and 4, and the signal on the signal path Pw controls the selectors 5 to 8. Even if the signal on the signal path Ps controls the selector 2, the signal on the signal path Pn controls the selectors 5 to 8, the signal on the signal path Pw controls the selector 2, and the signal on the signal path Ps controls the selectors 3 and 4. You may make it control.

When each of the storage elements 10 to 18 is provided independently, a specific storage element is designated and the data is written in the same manner as when writing data to storage elements in a normal matrix arrangement. You can also.

In the above description, four logic memories each having one output are used in accordance with the number of signal paths to the adjacent cells. However, the number of logic memories is arbitrary. For example, a method using one multi-output logic memory having a plurality of tri-state output functions is also conceivable.

Further, by setting in advance the value stored in the storage element at the address of each logical memory, the output value of the logical memory can be used as an arbitrary logical function using the input value of the logical memory as a variable. it can. For example, by setting the bit width of each signal path, the value of data stored in each logical memory, etc. as 1 bit and appropriately setting the value stored in the storage element of each address, An arbitrary combinational logic circuit having three inputs and one output can be expressed.

[Second Embodiment] FIG. 4 is a diagram showing an example in which a combinational logic circuit is constructed using the structure of the cell 1 shown in FIGS. Here, each signal path P of cell 1
w, Pn, Pe, Ps, logical memory Mw, Mn,
The value stored in Me and Ms is 1 bit.

First, the four logical memories M shown in FIG.
Of the w, Mn, Me, and Ms, the tri-state output function is turned on so that only the output of the logical memory Me can be output to the corresponding signal path Pe, and the other logical memories Mw, Mn, The output of Ms is the corresponding signal path P
It is set so as not to output (off: high impedance) for w, Pn, and Ps.

The value stored in the storage element at each address of the logical memory Me is expressed as a logical product of Pw and Pn among Pw, Pn and Ps which are three inputs to the logical memory Me. Set in advance. The values stored in the storage elements at the respective addresses of the logical memories Mw, Mn, and Ms other than the above may be set to arbitrary values, but usually all are initialized to 0.

The above settings are performed for each of the logic memories Mw, Mn, Me, and Ms in the cell 1, so that the logical product of the values given from the signal paths Pw and Pn of the cell 1 is obtained. A function of outputting the signal to the signal path Pe is provided. FIG.
Is an equivalent circuit of the contents set in FIG.

[Third Embodiment] FIG. 6 is a diagram showing an example in which a signal transfer path is formed using the structure of the cell 1 shown in FIG. Here, each signal path P of the cell 1 shown in FIG.
w, Pn, Pe, Ps, each logical memory Mw, Mn, M
The value stored in e and Ms is 1 bit.

First, of the four logic memories Mw, Mn, Me and Ms provided in FIG. 1, the tri-state output function is turned on so that only the output of the logic memory Me can be output to the corresponding signal path Pe. , And the outputs of the other logic memories Mw, Mn, Ms are set to the corresponding signal paths P
It is turned off so as not to output w, Pn, and Ps.

The value stored in the storage element at each address of the logical memory Me is set to the same value as the value of the signal path Ps among the signal paths Pw, Pn, and Ps which are the three inputs to the logical memory Pe. It is set in advance to output a value. The values stored in the storage elements at the respective addresses of the logical memories Mw, Mn, and Ms other than the above may be set to arbitrary values, but usually all are initialized to 0.

The above settings are made for each of the logic memories Mw, Mn, Me, and Ms in the cell 1 so that the value given from the signal path Ps of the cell 1 is output to the signal path Pe. Function is provided. FIG. 7 is an equivalent circuit of the contents set in FIG.

[Fourth Embodiment] FIG. 8 shows an example in which a plurality of cells 1 having the structure shown in FIGS. 1 to 7 are used to form a full adder (full adder). FIG. By setting each cell as a combinational logic circuit and a signal transfer path shown in FIGS. 4 to 7 for a plurality of cells having the structure shown in FIG. 1, the following equation (1) is obtained.
A full adder that performs the operation shown in (2) can be configured. Here, ex represents exclusive OR, and represents AND, and or represents OR. A and B are inputs, S is an addition output, CI is a carry input, and CO is a carry output.

S = A ex B ex CI (1) CO = (A and B) or (B and CI) or (CI and A) (2) In FIG. 8, cells 21 and 22 are exclusive ORs. A circuit, cells 23 and 24 constitute an AND circuit, a cell 25 constitutes an OR circuit, cells 26 to 30 constitute a signal transfer path, and a cell 31 constitutes an inverter.

[Fifth Embodiment] By the way, digital circuits include "combinational circuits" and "sequential circuits".
The former has no time element and the output is uniquely determined for the input signal, but the latter has a latch function that saves the value of the signal in the circuit, and is based on the time element of the control signal such as a clock. The output value depends.

However, conventionally, only a combinational circuit can be realized under the condition that it does not have a latch function, and when a sequential circuit is realized, a latch mechanism must be provided exclusively.

Therefore, in the fifth embodiment, it is not necessary to provide a dedicated latch mechanism.

FIG. 9 is a diagram showing a cell 1 constituting this latch circuit. Here, the tri-state output function of the two logic memories Mn and Me in the cell 1 is turned on, and the tri-state output function of the remaining logic memories Mw and Ms is turned off. In the logic memory Mn, the value stored in the storage element at the address is set in advance so as to express the NOR logic of the signals on the signal paths Pw and Pe input to the logic memory Mn. Further, the logic memory Me presets the value stored in the storage element at the address so as to express the NOR logic of the signals on the signal paths Pn and Ps which are input to the logic memory Me. Signals arrive from other cells on the signal paths Ps and Pw, the result of the logical processing of the logical memory Me appears on the signal path Pe, and the result of the logical processing on the logical memory Mn appears on the signal path Pn. Note that other logical memories M
The value stored in the storage element at each address of w and Ms may be set to an arbitrary value.
Initialize to

By performing each of the above settings for each of the logic memories Mw, Mn, Me, and Ms of the cell 1, the value given from the signal path Pw of the cell 1 is used as the reset signal R, A value given from Ps is set as a set signal S, a signal Q is output on a signal path Pn, and a signal Q is output on a signal path Pe.
, An SR latch circuit that outputs an inverted signal of.
FIG. 10 is an equivalent circuit of the setting contents of FIG. 9, and FIG.
This is a logic circuit representing an R latch circuit.

FIG. 12 shows a configuration in which the logical memories Me and Mw are provided with a function of performing NOR logic and an RS latch circuit is similarly formed. In this case, the tri-state output function of the logical memories Me and Mw is turned on. To the logical memory M
Set the tri-state output function of n and Ms to off.

In this embodiment, the latch circuit is constituted by using two logic memories in one cell.
It is also possible to configure a latch circuit using logic memories of different cells.

[0034]

As described above, according to the rewritable logic circuit of the present invention, a rewritable logic circuit using a reconfigurable wired logic element using only a logic memory can be constructed without using a transfer gate switch. Therefore, there is an advantage that high integration is easy and the flexibility of the configuration of the logic circuit is improved. Further, according to the latch circuit of the present invention, there is an advantage that a sequential circuit can be realized without providing a special latch mechanism.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cell according to a first embodiment.

FIG. 2 is a diagram in which a plurality of cells of FIG. 1 are arranged.

FIG. 3 is a block diagram showing an internal configuration of a logical memory.

FIG. 4 is a block diagram of a cell configured as a logical combination circuit of logical products;

FIG. 5 is an equivalent circuit of FIG.

FIG. 6 is a block diagram of a cell configured as a signal transfer path.

FIG. 7 is an equivalent circuit of FIG.

FIG. 8 is a diagram in which a full adder is configured by a plurality of cells.

FIG. 9 is a block diagram of a cell configured as a latch circuit.

FIG. 10 is an equivalent circuit of FIG. 9;

FIG. 11 is a logic circuit of FIG. 9;

FIG. 12 is a block diagram of another example of a cell configured as a latch circuit.

[Description of Signs] 1, 1A, 1B, 1C, 1D: cells 2 to 8: selector 9: tristate buffer 10 to 18: storage element 19: input terminal 21 to 31: cell Mw, Mn, Me, Ms: logic Memory Pw, Pn, Pe, Ps: signal path

Continuing on the front page (72) Inventor Ryusuke Konishi 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Kenji Ishii 3-192-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Telephone Co., Ltd. F term (reference) 5B016 AA10 GA01 5J042 AA10 BA01 BA08 BA19 CA00 CA13 CA14 CA15 CA19 CA20 CA22 CA23 CA25 CA26 CA27 CA28 DA01 DA04 DA06 5J043 AA00 AA05 BB04 DD00 DD06 DD07 JJ01 JJ10 KK01

Claims (3)

[Claims] 1. A logic circuit comprising a plurality of cells connected to adjacent cells by a signal path, wherein each cell has means for setting the signal path connected to each cell for input or output. Each cell is set for the output by reading a pre-stored value by accessing a rewritable logic memory using a value input through the signal path set for the input as an address. A rewritable logic circuit, which outputs the signal to a signal path. 2. The logic circuit according to claim 1, wherein said means for setting said signal path for input or output is realized by a tri-state output function of said logic memory. 3. The logic circuit of claim 1 or 2, wherein the address values of the first and second logic memories comprising two logic memories are respectively set to the logic function of the two-input NOR, and
Connecting a first input of each of the second logic memories to a separate signal path configured for the input;
An input is connected to a signal path set for output of the second logic memory, and a second input of the second logic memory is connected to a signal path set for output of the first logic memory. A latch circuit comprising: