JPH07218581A - Processing apparatus and processing method for semiconductor device - Google Patents

Abstract

PURPOSE:To improve cost performance in a testing for a test handler system which carries out a product testing of semiconductor element packages using a sub-board provided with a plurality of sockets. CONSTITUTION:Each handler 121, 122,... which composes, for example, a test part 12 is provided with a sub-loader 12a and a sub-unloader 12d. A loader part 11 to mount a semiconductor element package on each socket on a sub- board and an unloader part 13 to take the semiconductor element package out of each socket on the sub-board and to classify packages based on the results by the test part 12 are respectively separated from the test part 12. Consequently, the test part 12 is so composed as to alter corresponding to the test time of a tester 12c by separating each part of the apparatus independently in this way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor device processing apparatus for performing a predetermined processing on a semiconductor device and a processing method thereof, and is particularly used for a test handler system for performing a characteristic test of a semiconductor device. It is a thing.

[0002]

2. Description of the Related Art In recent years, a test handler system for conducting a product test such as a temperature test on a semiconductor element package (product under test) assembled into a package has been put into practical use as a device for performing a characteristic test of a semiconductor device. Has been done.

FIG. 8 shows a schematic configuration of a test handler system for carrying out a product test. In this test handler system, for example, a loader unit 1, a test unit 2, and an unloader unit 3 are integrally formed, and a robot 1a of the loader unit 1 takes out a semiconductor element package from a tray 4 and places it on a sub-board 5. After being transferred, the sub-board 5 is conveyed in the direction of the arrow in the drawing by a conveyor and sent into one of the chambers (constant temperature baths) 2a and 2b of the test section 2, where a temperature test is performed by a tester (not shown), Further, it is conveyed in the direction of the arrow shown.

The robot 3 of the unloader unit 3
The semiconductor element packages are taken out from the sub-board 5 by a, sorted according to the test results, and stored in a plurality of different trays 6.

The empty sub-board 5 from which the semiconductor device package has been taken out is further conveyed in the direction of the arrow in the figure, collected by the loader unit 1 and used repeatedly for subsequent product tests.

In this case, the test unit 2 has two chambers 2
The sub-substrate 5 is transferred in parallel to the two chambers 2a and 2b, which have a and 2b and are controlled to the same temperature, thereby increasing the processing capacity of the test unit 2 and performing efficient processing ( Simultaneous parallel processing).

For example, a maximum of 16 semiconductor element packages can be mounted on one sub-board 5, and 64 semiconductor element packages can be subjected to a product test at one time. There is.

Further, in the case of an integrated test handler system (integrated handler) in which the loader unit 1 or the unloader unit 3 is arranged on both sides of the test unit 2 as in this system, for example, as shown in FIG. In addition, one chamber 2a of the test unit 2 is set to a low temperature (LT chamber) and the other chamber 2b is set to a high temperature (HT chamber) so that the sub-board 5 is serially transferred between the two chambers 2a and 2b. By doing so, it is possible to continuously perform the low temperature test and the high temperature test on the semiconductor element package on the sub-board 5.

However, the above test handler system has the following problems. That is, the conventional test handler system includes loader units 1 and 2
Since the tester 2 having the two chambers 2a and 2b and the unloader 3 have an integrated structure, there is a drawback that the operating rate of the system is not good.

For example, if the configuration of the test unit 2 cannot be changed, that is, the number of testers cannot be increased, the loader unit 1 and the unloader unit 3 operate when the time required for the product test (test time) becomes long. The rate drops.

Further, when the test time becomes short, the processing capacity of the entire system is restricted by the processing capacity of the loader section 1 or the unloader section 3, and for example, the loader section 1 transfers the semiconductor element package onto the sub-board 5. Also, there is a limit to the ability of the unloader unit 3 to classify the semiconductor element packages taken out from the sub-board 5, and the tester cannot be operated beyond this.

Therefore, even if the test time becomes short, the operating rate of the test section 2 (tester) cannot be improved (see FIG. 7). Further, when the loader unit 1 or the unloader unit 3 fails, the operation of the test unit 2 stops, that is, the operation rate of the tester decreases even when either the loader unit 1 or the unloader unit 3 fails. Such surplus capacity (decrease in operating rate) of the test unit 2 or the loader unit 1 or the unloader unit 3 results in excessive capital investment, resulting in an increase in test cost.

[0013]

As described above, in the related art, there is a problem in that the operating rate is apt to decrease, which leads to an excessive capital investment and an increase in test cost. Therefore, according to the present invention, it is possible to make a capital investment according to the processing capacity and reduce the facility cost.
An object of the present invention is to provide a semiconductor device processing apparatus and a processing method thereof, which can improve the operation rate and reduce the processing cost.

[0014]

To achieve the above object, in a semiconductor device processing apparatus according to the present invention, a receiving section for receiving a semiconductor device to be processed, and the semiconductor device received by the receiving section. And a transfer mechanism section configured to transfer the semiconductor substrate to the processing substrate, a transfer mechanism section configured to supply the processing substrate on which the semiconductor device is transferred by the transfer section, and the supply section of the transfer mechanism section. A processing unit that sequentially receives the processing substrates supplied by the processing unit, a processing unit that sequentially performs a predetermined process on the semiconductor device transferred onto the processing substrate that is captured by the processing unit, Of several processing mechanism units each including a discharge unit configured to discharge the processed substrate after the processing of the semiconductor device is completed, a receiving unit configured to receive the processed substrate discharged by the discharge unit of the processing mechanism unit, and the receiving unit Department The semiconductor device on the processed substrate received is provided with a sorting mechanism unit configured to sort the semiconductor device according to the processing result of the processing unit of the processing mechanism unit, and each of the mechanism units is configured independently. The number of the processing mechanism units can be increased or decreased according to the processing capacity of the processing units.

According to the semiconductor device processing method of the present invention, the semiconductor device to be processed is received by the receiving section of the transfer mechanism section, and the semiconductor device received by this receiving section is transferred by the transfer mechanism section. While being transferred onto the processing substrate in the mounting part,
The processing substrate on which the semiconductor device has been transferred by the transfer unit is supplied by the supply unit of the transfer mechanism unit, and the processing substrate supplied by the supply unit of the transfer mechanism unit is processed by any of the processing mechanism units. Are sequentially taken in by the take-in unit, and the semiconductor device transferred onto the processing substrate taken in by the take-in unit is subjected to predetermined processing by the processing unit of the processing mechanism unit, and the processing unit The processing substrate for which the processing for the semiconductor device has been completed is discharged by the discharging unit of the processing mechanism unit, and the processing substrate discharged by the discharging unit of the processing mechanism unit is received by the receiving unit of the sorting mechanism unit, The semiconductor devices on the processing substrate received by the receiving unit are classified by the classification unit of the classification mechanism unit according to the processing result of the processing unit of the processing mechanism unit.

[0016]

According to the present invention, each of the mechanical units is independently configured by the above-mentioned means, and the number of the processing mechanical units can be increased or decreased according to the processing capacity, so that the cost performance for the processing can be improved. It will be.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 conceptually shows a schematic configuration of a test handler system according to the present invention.

That is, this test handler system includes, for example, a loader section (transfer mechanism section) for transferring a semiconductor element package (semiconductor device) as a product under test onto a sub-board (SUB board) as a processing board described later. 1
1. A test unit 12 that executes a predetermined product test on the semiconductor element package transferred onto the sub-board, and an unloader unit that takes out the semiconductor element package from the sub-board and classifies it according to the test result ( A classifying mechanism section 13 and a block computer (B / C) 14 as a management means for managing each section are composed of four independent devices.

The loader section 11 is a loader (LD) 11a as a receiving section for receiving a semiconductor element package from a tray or a magazine (not shown), and a transfer for transferring the semiconductor element package received by the loader 11a onto a sub-board. And a sub-unloader (SUB UD) 11c as a supply unit for supplying the sub-substrate on which the semiconductor element package is transferred by the transfer unit 11b to the test unit 12.

The test section 12 supplies the semiconductor element package on the sub-board supplied from the loader section 11 to the semiconductor element package.
Multiple handlers (processing mechanism parts) that perform specified product tests, such as characteristic tests such as low temperature tests or high temperature tests
It is composed of 121, 122 ,.

Each of the handlers 121, 122, ... Includes a sub loader (SUB LD) 12a as a loading unit for sequentially loading the sub substrates supplied by the sub unloader 11c of the loader unit 11, and in this sub loader 12a. The tester 12 as a processing unit for sending the taken-in sub-board into the chamber (constant temperature bath) 12b and testing the semiconductor element package in the temperature atmosphere.
c, a sub-unloader 12d as a discharging section for discharging the sub-board, which has been tested by the tester 12c, toward the unloader section 13 in the subsequent stage.

The handlers 121, 122, ... Can be appropriately increased or decreased in accordance with the processing capacity of the test section 12 (test time of the tester 12c).

The unloader section 13 is a sub-unloader 12d of each handler 121, 122, ... of the test section 12.
The sub-loader 13a as a receiving section for receiving the sub-boards respectively discharged by the above, the semiconductor element package on the sub-board received by the sub-loader 13a is taken out, and the handlers 121, 12 of the test section 12 are taken out.
2, a classifier 13b as a classifying unit that classifies according to the test results by the tester 12c at
Unloader (UD) 1 for storing semiconductor device packages classified in b in a tray or magazine not shown
3c etc.

The block computer 14 has a CPU 1
Under the control of 4a, for example, based on the unique identification information (described later) given to each sub-board, the product name of the semiconductor element package, the lot number, the test result by the tester 12c, and this test. The classification instruction to the classifier 13b of the unloader unit 13 corresponding to the result is managed.

The sub-board used for the product test by the above-mentioned test handler system will be described below. FIG. 2 schematically shows the structure of the sub-board. Note that FIG. 11A is a plan view of the sub-board, and FIG. 9B is a side view of the same.

The sub-board 21 for handling the semiconductor element package is, for example, a SOJ (Small Outline) used for a product test on a printed board 21a on which a circuit pattern (not shown) is wired.
J-leaded Package) or TSOP
(Thin Small Outline Packa
ge) for mounting semiconductor device packages such as
A plurality of (here, 16) sockets 22 are provided.

Further, one end of the sub-board 21 is provided with, for example, bar code information 23 which records the above-mentioned unique identification information for each sub-board 21. That is, by supplying such a sub-board 21 to each handler 121, 122, ... of the test section 12, each tester 12c tests 16 semiconductor device packages at a time.

FIG. 3 schematically shows the structure of the socket 22. It should be noted that FIG. 11A is a top view of the socket 22, and FIG. 11B is a side view showing a part of the same.

The contactor 2 of the socket 22 is brought into contact with each electrode lead of the semiconductor element package mounted in the socket 22 by pushing down the cap 22a.
The contact terminal portion 22c of 2b is configured to spread outward, and in this state, after mounting the semiconductor element package in the socket 22, by returning the cap 22a to the original position, each electrode of the semiconductor element package The lead and the contact terminal portions 22c of the contactor 22b are in contact with each other.

The contactor 22b of the contactor 22b, which is opposite to the contact terminal portion 22c, is projected to the outside (on the side of the sub-board 21) from the bottom surface of the socket 22 and is contacted by a test head (not shown) of the tester 12c. External terminal part 2
It is 2d.

The socket 22 is adapted to be attached and fixed on the sub-board 21 by a screw 24. The tray used in the present embodiment is for accommodating a large number of semiconductor element packages for which a product test is performed and a large number of semiconductor element packages for which a product test has been completed by arranging them in a plane, and the magazine includes a large number of semiconductor elements. The packages are stored in a stacked state.

In the test handler system having the above configuration, first, the loader 11 of the loader unit 11 is
The semiconductor element package stored in the tray or the magazine is received by a, and the semiconductor element package is transferred to the socket 22 on the sub-board 21 by the transfer machine 11b.
Will be implemented in.

In this way, the sub-board 21 on which a large number of semiconductor element packages have been transferred is, in order, the sub-unloader 11
The handlers 121, 122 of the test unit 12 are processed by c.
, To, respectively.

The sub-board 21 from the loader section 11 is sequentially loaded into the sub-loaders 12a of the handlers 121, 122 ,.
After being taken in by the sub loader 12a, it is sent into each chamber 12b by this sub loader 12a.

Then, in the predetermined temperature atmosphere, the tester 12c performs a product test on each semiconductor element package. After this, the tester 12c
The sub-board 21 for which the product test for the semiconductor element package by the above is completed is discharged toward the unloader unit 13 by each sub-unloader 12d.

The sub-boards 21 from the handlers 121, 122, ... Are received by the sub-loader 13a, so that the sockets 2 on the sub-boards 21 are received.
The semiconductor device package mounted in 2 is the classifier 13
taken out by b.

In this case, each semiconductor device package has a classification instruction from the block computer 14,
For example, it is taken out according to the product name, lot number, test result, etc. based on the bar code information 23.

The semiconductor element packages respectively taken out by the sorter 13b are sorted and stored in a plurality of different trays or magazines by the unloader 13c.

The empty sub-board 21 from which the semiconductor device package has been taken out is returned to the loader section 11,
Used repeatedly for subsequent product testing. in this way,
Between the loader unit 11 and the unloader unit 13, a plurality of handlers 121, 1 are provided depending on the processing capacity of the test unit 12.
It is possible to easily construct a system in which 22 and ... are arranged.

That is, in consideration of the test time of the tester 12c, the test unit 12 is configured to match the processing capabilities of the loader unit 11 and the unloader unit 13. For example, the processing capacities of the loader unit 11 and the unloader unit 13 are set to "1", and the handlers 121, 122, ...
When the tester 12c of the above requires a test time which is four times as long as that of the tester 12c, the test section 12 is provided with four handlers 121 to 124.
With this configuration, even when the test time is long, each unit can be operated without waiting time, and the operation rate of each unit can be improved.

On the other hand, for example, the processing capacity of the loader unit 11 and the unloader unit 13 is set to "1", and each handler 121
, 122, ..., the tester 12c requires a test time that is twice as long as the tester 12c, the test unit 12 has two handlers 1
With the configuration of 21 and 122, each unit can be operated without waiting even when the test time is short and the operating rate of each unit can be improved.

Moreover, by eliminating the waiting time of each section and allowing each section to operate efficiently, the surplus capacity can be eliminated. For this reason, although an increase in cost due to a slight configuration change is unavoidable for each part, it is still possible to prevent excessive capital investment as a result.

Further, in the test handler system of the present invention, since the sub-board 21 can be taken in and taken out for each handler 121, 122, ..., the handlers 121, 122, ..., as shown in FIG.
It is also possible to construct such that a plurality of sub-boards 21 can be collectively supplied to each of the above.

FIG. 4 is constructed so that a low temperature test and a high temperature test of a semiconductor device package are continuously performed.
It shows an example of construction of a test handler system. This test handler system has four independent units, that is, the above-mentioned units, that is, the loader unit 11, the test unit 12, the unloader unit 13, and the block computer 14.
For example, two devices are arranged around the cassette automatic transport path 31.

In this case, the cassette automatic transfer path 31
Is a sub-board 2 on which the semiconductor element package is transferred.
1 is carried in a unit of a plurality of sheets, and is mainly composed of a belt conveyor or the like for carrying a sub-board cassette 32 in which a plurality of sub-boards 21 are stored, as shown in FIG. 5, for example.

The loader section 11 receives a semiconductor device package stored in, for example, a tray or a magazine (not shown) and takes out the semiconductor device package received by the loader 11a from the sub-board cassette 32. The transfer machine 11b for transferring the transferred sub-board 21 onto the sub-board 21, the sub-unloader 11c for storing the sub-board 21 on which the semiconductor element package is transferred by the transfer machine 11b in the sub-board cassette 32, and the cassette automatic It comprises a cassette handler 11d for carrying the sub-board cassette 32 to and from the carrying path 31.

The test section 12 carries out, for example, a low temperature test or a high temperature test on the semiconductor device package on the sub-board 21 stored in the sub-board cassette 32, which is carried through the cassette automatic carrying path 31. Multiple handlers 121, 122, 123, 124 for testing
, ~.

Usually, the high temperature test is performed after the low temperature test, but the high temperature test takes a longer time than the low temperature test. Therefore, the handler 121 for the low temperature test is several times as large as that of the low temperature test handler 121. Handlers 122, 123, 124 for high temperature test are prepared.

For example, in the case of a semiconductor device package having a long test time such as a 16M DRAM, it is 10
20 to 20 handlers are prepared. Also, in the case of a semiconductor device package having an extremely short test time, for example, when the test time at high temperature is twice as long as the test time at low temperature, three handlers (one for low temperature and two for high temperature) are used.
Stand).

The handlers 121, 122, 123, 1
Each of the sub-boards 24, ..., Sub loader 12a that sequentially takes in the plurality of sub-boards 21 stored in the sub-board cassette 32, and sequentially sends the sub-boards 21 that are taken in by the sub-loader 12a into the chambers 12b and 12b. A tester 12c for testing a semiconductor device package in a temperature atmosphere, and the sub-board 21 for which the test by the tester 12c has been completed, the sub-board cassette 3
2 includes a sub unloader 12d to be stored in the cassette 2, a cassette handler 12e for carrying the sub substrate cassette 32 to and from the automatic cassette carrying path 31, and the like.

Further, each handler 121, 122, 123
, 124, ... have two chambers 12b, 12b respectively. For example, of the above handlers 121, 122, 123, 124, ..., the handler 121 for low temperature test has two LT chambers (constant temperature bath controlled to low temperature) 12b, 12b, and handler for high temperature test. Each of 122, 123, 124, ... has two HT chambers (constant temperature bath controlled to high temperature) 12b, 12b.

As a result, the handlers 121, 122, 1
By supplying the sub-boards 21 on which, for example, 16 semiconductor element packages are transferred, to 23, 124, ..., 32 semiconductor element packages can be tested at one time.

The unloader unit 13 takes out the sub-loader 13a for receiving the plurality of sub-boards 21 stored in the sub-board cassette 32, the semiconductor element package on the sub-board 21 received by the sub-loader 13a, and takes it out as described above. A classifier 13b for classifying according to a classification instruction (test result etc.) from the block computer 14, an unloader 13c for storing the semiconductor element packages classified by the classifier 13b in a tray or a magazine (not shown), and the cassette. It comprises a cassette handler 13d for carrying the sub-board cassette 32 to and from the automatic carrying path 31.

The block computer 14 additionally controls the transfer of the sub-board cassette 32 transferred on the cassette automatic transfer path 31, and
The test result from the low temperature test handler 121 and any of the high temperature test handlers 122, 123, 124
, By combining the test results from
It is configured to have an algorithm for classifying the semiconductor device package.

Here, the above-mentioned automatic cassette transport path 31 is used.
An outline of a cassette handler for carrying the sub-board cassette 32 between and will be described. FIG. 6 schematically shows the structure of the cassette handler 11d. In addition,
9A is a top view showing the movement of the sub-board cassette 32 in the cassette handler 11d, and FIG.
Is also a side view.

The cassette handler 11d, for example, takes in a sub-board cassette 32 which is carried on the cassette automatic carrying path 31, and a plurality of sub-boards 21 stored in the cassette 32 are transferred to the transfer machine 11b. The sub-board loader 41 that sequentially ejects the sub-boards 21 onto which the semiconductor element packages are transferred by the transfer machine 11b are returned to the cassette 32 in order, and the sub-board cassette 32 in which all the sub-boards 21 are stored. To the cassette automatic transfer path 31
And are integrally formed.

That is, the sub-board cassette 32 is shown as A in the figure.
It is taken into the cassette handler 11d from the position (1) (on-machine state) and sequentially moved inside. Then, the vertical position thereof is controlled by the elevator 43, and the sub-boards 21 are paid out one by one in the direction of B in the drawing.

The sub-board cassette 32 from which all the sub-boards 21 have been delivered is sent to the elevator 44. Then, the sub-board 21 on which the semiconductor element package is transferred from the direction of C in the figure, while controlling its vertical position.
Are returned one by one and stored in order.

The sub-board cassette 32, in which all the sub-boards 21 are stored, is sent to the elevator 45, then sequentially moved inside and sent out from the position D in the figure onto the cassette automatic carrying path 31 (of the off-machine). Status).

In the case of this embodiment, the cassette handler 11d
Is a sub-board loader 41 and a sub-board unloader 42.
Both can accommodate 10 sub-board cassettes 32 at a time.

Therefore, by using the cassette handler 11d as a buffer, even if a trouble occurs in the loader unit 11 or the unloader unit 13 during the operation, the test unit 12 can be used while the trouble is released. Can be operated, test unit 1
The operation rate of each tester 12c in 2 can be improved.

Here, the cassette handler 11d is used.
Although the configuration has been described with reference to the above, the cassette handlers 12e and 13d have the same configuration. In this way, in the case of constructing a test handler system capable of supplying a plurality of sub-boards 21 at once,
For example, as shown in FIG. 7, when the test time is short, the throughput can be significantly improved.

That is, according to the present system, the throughput can be improved when the test time is shorter than 56 seconds, compared to the conventional system, and about 1.60 times when the test time is set to 30 seconds. Efficiency can be improved.

In addition, in the case of this system, labor can be saved by automating the transportation, and since the test for the same lot is shared by a plurality of handlers, simultaneous parallel processing is possible, which shortens the construction period. Can be achieved.

As described above, the loader section, the test section, and the unloader section are independently configured so that the number of handlers in the test section can be increased or decreased according to the test time of the tester.

That is, in a test handler system for performing a product test of a semiconductor device package using a sub-board provided with a plurality of sockets, a loader and an unloader are prepared for each handler constituting the test section, and this test section is prepared. Separates the loader section that mounts the semiconductor element package into each socket on the sub-board and the unloader section that takes out the semiconductor element package from each socket on the sub-board and classifies it according to the test result in the test section. It is designed to have the same structure.

As a result, the optimum test section can be constructed according to the test time of the tester, so that the cost performance for the test can be improved.

Therefore, it is possible to prevent an unnecessary increase in equipment cost, improve the operation rate of each part, and significantly reduce the test cost.

In the above embodiment, the case where the product test is performed by the high / low temperature test has been described as an example, but the present invention is not limited to this, and can be easily applied to, for example, another characteristic test. Of course, various modifications can be made without departing from the scope of the invention.

[0070]

As described above in detail, according to the present invention, it is possible to make an equipment investment according to the processing capacity, reduce the equipment cost, improve the operating rate, and reduce the processing cost. It is possible to provide a semiconductor device processing apparatus and a processing method thereof.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a schematic configuration of a test handler system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a sub-board used in the test handler system in the same manner.

FIG. 3 is a configuration diagram schematically showing a socket arranged on the sub-board.

FIG. 4 is a block diagram showing a construction example of a test handler system.

FIG. 5 is a perspective view schematically showing a sub-board cassette used in the test handler system.

FIG. 6 is a configuration diagram schematically showing a cassette handler used for carrying a sub-board cassette.

FIG. 7 is a diagram showing the processing capacity of this system in comparison with a conventional system.

FIG. 8 is a perspective view showing the configuration of a test handler system shown for explaining the conventional technique and its problems.

FIG. 9 is a block diagram schematically showing another construction example of the conventional system.

[Explanation of symbols]

11 ... loader section, 11a ... loader, 11b ... transfer machine, 1
1c ... sub-unloader, 11d ... cassette handler, 1
2 ... Test unit, 121, 122, ... Handler, 12a
... Sub loader, 12b ... Chamber, 12c ... Tester, 1
2d ... Sub-unloader, 12e ... Cassette handler, 1
3 ... Unloader section, 13a ... Subloader, 13b ... Sorting machine, 13c ... Unloader, 13d ... Cassette handler,
14 ... Block computer, 21 ... Sub-board, 22
... socket, 23 ... bar code information, 31 ... cassette automatic transport path, 32 ... sub-board cassette.

Claims (5)

[Claims] 1. A receiving unit for receiving a semiconductor device to be processed, a transfer unit for transferring the semiconductor device received by the receiving unit onto a processing substrate, and the semiconductor device transferred by the transferring unit. A transfer mechanism section including a supply section for supplying a processing substrate, a loading section for sequentially loading the processing substrates supplied by the supply section of the transfer mechanism section, and the processing substrate on the processing substrate sequentially loaded by the loading section. Some processing mechanism sections including a processing section for performing a predetermined process on the semiconductor device transferred to the semiconductor device, and an ejecting section for ejecting the processed substrate on which the semiconductor device has been processed by the processing section. And a receiving unit that receives the processing substrate discharged by the discharging unit of the processing mechanism unit, the semiconductor device on the processing substrate received by the receiving unit, the processing result of the processing unit of the processing mechanism unit. Therefore, a classifying unit including a classifying unit for classifying is provided, each of the mechanical units is configured independently, and the number of the processing mechanical units can be increased or decreased according to the processing capacity of the processing unit. A characteristic semiconductor device processing apparatus. 2. The processing substrate is provided with unique identification information, respectively, and further includes a management unit that manages each of the mechanical units based on the identification information. Semiconductor device processing equipment. 3. The management unit of a plurality of processing mechanism units that perform different processing on the semiconductor device on the processing substrate,
3. The semiconductor device processing apparatus according to claim 2, further comprising an algorithm for classifying the semiconductor device by combining processing results from the processing units. 4. The semiconductor device processing apparatus according to claim 1, further comprising a transfer unit that transfers a plurality of processing substrates collectively between the respective mechanical units. 5. A semiconductor device to be processed is received by a receiving section of a transfer mechanism section, and the semiconductor device received by this receiving section is transferred onto a processing substrate by the transfer section of the transfer mechanism section, and at the same time, The processing substrate on which the semiconductor device has been transferred by the transfer unit is supplied by the supply unit of the transfer mechanism unit, and the processing substrate supplied by the supply unit of the transfer mechanism unit is supplied to one of the processing mechanism units. The processing section of the processing mechanism section sequentially performs a predetermined process on the semiconductor device transferred onto the processing substrate, which is sequentially captured by the capturing section. Of the semiconductor device, the processed substrate is discharged by the discharge unit of the processing mechanism unit, and the processed substrate discharged by the discharge unit of the processing mechanism unit is received by the receiving unit of the sorting mechanism unit. Accepted by the receiving department The semiconductor device of the serial processing on a substrate, processing method of a semiconductor device is characterized in that so as to classify the classification of the classification mechanism in accordance with the processing result in the processing section of the processing mechanism.