JPH0721358A - Picture acquisition device - Google Patents

Abstract

PURPOSE:To provide an inexpensive and simple picture acquisition device. CONSTITUTION:This device is provided with a sampling means 7 for sampling analog picture signals, a storage means 8 for acquiring the analog picture signals sampled by the sampling means by at least one horizontal scanning line and a PLL circuit 11 for generating sampling clocks synchronized with the analog picture signals. The PLL circuit is provided with a frequency divider capable of optionally setting a frequency division value corresponding to the display period of one picture element of the picture signal and the frequency divider generates addresses when the analog picture signals are written in the storage means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image capturing device such as a printer which supports image signal input.

[0002]

2. Description of the Related Art Computer graphics (hereinafter referred to as CG
In a workstation for CAD, a high-definition television (hereinafter referred to as HDTV) specification output device, and a device for capturing image data from an image signal output from the output device.
It was necessary to use a large amount of high-speed semiconductors such as ECL in order to capture one frame of an image signal in which a dot clock exceeding several tens to 100 MHz was output in real time. However, high-speed semiconductors such as ECL are expensive, and it is not realistic to use a large amount of this kind of semiconductor.
For this reason, conventionally, a method has been performed in which, for each frame, the image signal is written in a line buffer in the unit of N lines in the vertical direction or in the unit of N lines in the horizontal direction and further transferred from the line buffer to a large-capacity frame memory. There is.

[0003]

At this time, in the vertical direction, N
In the line capturing method, the sampling position is shifted and written for each frame. Therefore, it is necessary to accurately control the sampling position with respect to the image display start position of the input image signal and to latch the corresponding pixel at high speed. Further, in the method of fetching N lines in the horizontal direction, it is necessary to control the write address to the line buffer. In either case, the circuit was composed of a complicated and expensive circuit using a high-speed device such as ECL.

An object of the present invention is to provide an image capturing device which is cheaper and simpler than conventional ones.

[0005]

To achieve the above object, the present invention provides a sampling means 7 for sampling an analog image signal, and a storage means for taking in at least one horizontal scanning line of the analog image signal sampled by the sampling means. 8 and a PLL circuit 11 for generating a sampling clock synchronized with the analog image signal, the PLL circuit has a frequency divider 5 capable of arbitrarily setting a frequency division value, and the analog image signal sampled in the storage means is The divider is configured to generate the address when it is written.

[0006]

According to the present invention, since the address is generated from the frequency divider which constitutes a part of the PLL circuit, it is not necessary to separately provide a circuit for generating an address for writing to the storage means.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, 1 is a horizontal sync signal input terminal, 2 is a phase comparator for comparing the phases of the horizontal sync signal and a signal following the horizontal sync signal, and 3 is a low-pass for smoothing the output of the phase comparator. A filter 4, a voltage controlled oscillator (hereinafter referred to as VCO) that generates a sampling clock according to the control voltage output from the low-pass filter, 5 is a frequency divider that divides the sampling clock output from the VCO, and 6 is an analog image A signal input terminal, 7 is an A / D converter that samples an image signal with a sampling clock, 8 is a line buffer that stores the image signal quantized by the A / D converter, and 9 is temporarily stored in the line buffer. A frame buffer for freezing the generated image signal as one screen, 10 a system control unit for controlling the entire apparatus, 11 a PLL circuit, 12 A keyboard.

The period of the horizontal synchronizing signal input from the terminal 1 differs depending on the device that outputs the image signal, and even if the period of the horizontal synchronizing signal is the same, the display period of one pixel may differ. In general, an image signal having different specifications is obtained depending on the device connected to the terminal 1, for example, the model of the workstation, so that the system control unit 10 appropriately controls the parameters necessary for image capturing. The parameters are set in the system control unit 10 by the keyboard 12. The parameter set in the frequency divider 5 is the total number of pixels corresponding to one cycle of the horizontal synchronizing signal.

Here, the frequency divider 5 is composed of presettable counters 52, 53 and 54, a preset control section 55 and an address path selector 58 as shown in the example of FIG. A sampling clock is supplied from the VCO 4 to the input terminal 51, and the sampling clock is supplied to the presettable counters 52, 53 and 54.
The count is performed so as to be equal to the number corresponding to the total number of pixels set by 0. Presettable counter 52,
When 53 and 54 count the total number of pixels, the preset control unit 55 causes the presettable counters 52, 53 and 5 to operate.
4 is preset, and the pulse for comparison of the phase comparator 2 is output to the terminal 56. The selector 58 is an address bus that switches the signals from the presettable counters 52, 53 and 54 to the signals from the system control unit 10 and supplies them to the line buffer via the terminal 59.

The operation of the frequency divider 5 will be described with reference to FIGS. 3 and 4. FIG. 3 shows a signal waveform of one standard horizontal scanning period such as CG and CAD, which has an effective display area Hdisp of 1280 horizontal pixels. 3 and 4 show the case where the synchronization signal and the image signal are superimposed for convenience of explanation. Sync indicates the width of the horizontal synchronizing signal, BP indicates the back porch of the horizontal synchronizing signal, and FP indicates the front porch of the horizontal synchronizing signal. In FIG. 3, one horizontal scanning period (hereinafter 1
The total number of pixels corresponding to (H) is 1600 dots, and the frequency divider 5 is preset in the system control unit 10 to count 1600. Here, the line buffer 8 shown in FIG. 1 has a capacity of 2 Kbytes, and the A / D
It is assumed that the converter 7 has a quantized 8-bit precision. The word length of the line buffer 8 is 2K.
This is because the effective display area Hdisp of 1H exceeds 1K (1024) words.

In FIG. 4, (a) is an enlarged view of a part of 1H of FIG. 3, (b) is a sampling clock output by the VCO 4, and (c) is a preset pulse output of the preset control unit 55. Yes, (d) is a presettable counter 5
The count outputs from 2, 53 and 54 are shown, and in FIG. 2 as well, the same symbols as the above-mentioned signals are shown. See also FIG.
Then, the width of Sync and BP corresponds to 100 pixels. The presettable counters 52, 53, and 54 are set by the system control unit 10 to n satisfying the following formula 1.

[0012]

## EQU00001 ## 2048--n = 1600 The presettable counters 52, 53 and 54 start counting from the set n = 448. The preset control unit 55 causes the preset pulse (c) to fall when the count values of the presettable counters 52, 53 and 54 reach 2047, and raises the preset pulse (c) when the count value reaches 2048. Presettable counter 52,
53 and 54 are preset at the rising edge of the preset pulse (c).

With the above configuration, the frequency divider 5 is preset by the preset pulse (c) which coincides with the falling edge of the horizontal synchronizing signal input from the terminal 1, and 1H = 1600
The operation of counting the sampling clock corresponding to dot is repeated to operate as a part of the PLL circuit 11. On the other hand, when the system control unit 10 allows the writing of the line buffer, the preset one line can be written, and the output of the frequency division counter and the write signal shown in FIG. 4D are supplied to the line buffer. . In the writable state, the line buffer uses the counter output as an address, starts writing from the address “n”, and ends the writing at the address “2048”. When the writing to the line buffer is completed, the system control unit 10 switches the line buffer address selector to transfer the image data of the line buffer to the frame buffer. At this time, the system controller 10 sends the address "n"
The reading starts from +100 "and the address" n + 12 "
The reading ends at 99 ". That is, the reading from the line buffer is always only the effective image area.

As described above, in the image capturing device intended for various image signal output devices having different specifications as in the present embodiment, a variable variable loop circuit that composes a sampling clock by following a wide range of frequencies. The output of the frequency divider can be used. In this embodiment, 1 is set in the line buffer.
Although only horizontal scanning lines are stored, a plurality of horizontal scanning lines may be stored. Furthermore,
In the present embodiment, a general non-interlaced image signal for CG and CAD has been described as an example, but it can be applied to the case of outputting an interlaced high-band image signal such as an output device of HDTD specification. Is. Further, the image signal in the present invention includes both moving images and still images.

[0015]

As described above, according to the present invention, a dedicated timing generation circuit or address control circuit for writing an analog image signal in a line buffer is not required, and an expensive device such as an ELC is conventionally used. The cost can be reduced by simplifying the complicated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a frequency divider according to the present invention.

FIG. 3 is a diagram showing a horizontal synchronizing signal and an image signal according to the operation of the present invention.

FIG. 4 is a timing chart showing the operation of the present invention.

[Explanation of symbols]

 5 Frequency divider 7 A / D converter 8 Line buffer 9 Frame buffer 11 PLL circuit

Claims (1)

[Claims] 1. A sampling means for sampling an analog image signal, a storage means for taking in at least one horizontal scanning line of the analog image signal sampled by the sampling means, and a sampling clock synchronized with the analog image signal. PLL
The PLL circuit includes a frequency divider that can arbitrarily set a frequency division value according to a display period of one pixel of an image signal,
An image capturing device, wherein the frequency divider generates an address when an analog image signal is written in the storage means.