JPH07212215A - Level converting circuit, semiconductor integrated circuit and control method for them - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit which eliminates the loss of power consumption caused by an internal power source circuit, makes possible small amplitude data transfer and extremely reduces current consumption even when multi-bit data lines are parallelly operated. CONSTITUTION:During the first half term of one cycle of a clock signal., capacitors la and lb are charged at an intermediate potential VM (=(Vcc-Vss)/2) between both the precharge potentials of two level converting circuits. Afterwards, during the latter half term of one cycle of the clock signal, the capacitor 1a is connected to an output node (Vout 1, for example,) on the side to be changed to the low potential side by the upper step level converting circuit, and a power supply line Vcc is connected to an output node (XVout 1, for example,) on the side to be changed to the high potential side. At the same time, the capacitor lb is connected to an output node (XVout 2, for example,) on the side to be changed to the high potential side by the lower step level converting circuit, and a ground line Vss is connected to an output node (Vout 2, for example,) on the side to be changed to the low potential side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory, a synchronous dynamic random access memory (SDRAM), a static random access memory (SDRAM) in which a large number of data lines operate in parallel on a semiconductor chip in synchronization with a clock signal. SRAM) and other memory circuits, level conversion circuits used in microprocessors that perform parallel data processing, and semiconductor integrated circuits using the level conversion circuits,
It also relates to improvements in these control methods.

[0002]

2. Description of the Related Art Conventionally, a level conversion circuit for converting the amplitude level of an output signal into a level different from the amplitude level of an input signal is disclosed in, for example, Japanese Patent Application Laid-Open No. 42-111515 (Nakagome et al.
Hitachi Ltd.) has been disclosed. Hereinafter, this conventional technique will be described.

The conventional technique will be described with reference to FIGS. 27 and 28.

27 (a) and 27 (b) show a clock-synchronous level conversion circuit and its operation explanatory diagram. In FIG. 3A, CLK (3) and XCLK (2) are synchronization signals (clock signals),
Vin (11) is an input signal before level conversion, VH (90) is a high level power source after level conversion, and VL (91) is a low level power source after level conversion. VM (9) is a precharge power supply, and its power supply potential is an intermediate potential between the high level potential VH and the low level potential VL.

Next, the operation will be described with reference to FIG.
With PMOSFET (5) controlled by clock signals CLK and XCLK
When the NMOSFET (6) is turned on, the inverter operation becomes possible and the input Vin (11) is inverted and taken in. For example, if Vin (11) is the power supply potential Vcc level, the output is V
It becomes the low level value of L (91). Next, when the clock signals CLK and XCLK are inverted, the PMOSFET (5) and the NMOS FE
With T (6) turned off, PMOSFET (12) and NMOSFET (9)
Are turned on, the output is connected to the precharge power source VM (9), and precharged to an intermediate potential. The above operation is set to one cycle, and the same operation is repeated thereafter, and the input Vin (1
If 1) is inverted every cycle, the output is also inverted. In the above operation, the change width of the output level is (VH-VM), (VM-V
L), which is smaller than the change in input level (Vcc-Vss). That is, the amount of charge that charges and discharges the parasitic capacitance CD (10) of the output node Vout can be small. This charge amount is determined by the product of the change amount of the potential of the capacitance and the capacitance value. Therefore, if the ratio of the amplitude level between the input and the output becomes 1/10, the charge / discharge of the output node is performed by this level conversion circuit. 1/10 charge
Since it is enough, compared with the case where level conversion is not performed, 1 /
10 low power consumption is possible.

Next, the level-converted power supply VH (90)
, VL (91) generating circuit is shown in FIG. This generation circuit is built in the same chip.Generally, as shown in the figure, a power supply circuit with a current mirror type output using the potential divided by resistors R1, R2 and R3 as a reference potential. The method of controlling the output transistor of is adopted. The voltage level of the power supply VH (90), VL (91) is the resistance mentioned above.
It can be arbitrarily selected by adjusting the ratio of R1, R2 and R3.

However, in the internal power supply circuit shown in FIG. 28, it is necessary to supply the power supply current of the driver for driving the wiring having a large capacity with a low resistance, so that the size of the current mirror and the output transistor becomes large, The resistors R1, R2, R3, and R4 that generate the reference potential cannot be selected to have high resistance values.As a result, the through currents IDC1 and IDC2
Has a drawback that the current consumption is unnecessarily increased because the total sum of the above becomes as large as several mA.

Looking at the above-mentioned conventional drawback in terms of power consumption, the power consumption of the level conversion circuit of FIG. 27 is Ptoal = P1 +
It becomes P2. Here, P2 is determined by the product of the current consumption when the wiring capacitance is driven with the amplitude after level conversion and the amplitude voltage after level conversion. The P1 is power wasted when the internal power supply circuit drops the voltage to generate the internal voltages VH and VL. The power consumption P1 is the amplitude after the level conversion of the wiring capacitance. The current consumption when driven and the voltage amount (Vcc
-VH + VL), and when the amount of voltage that has caused this voltage drop is large, that is, when the output amplitude value is to be made smaller, useless power consumption P2 is further increased.

Further, in image memory, etc., 64 bits, 128
Since bits or 256 bits are simultaneously operated in parallel on the same chip, there is a drawback that the above-mentioned power consumption is multiplied by the number of bits and power is consumed as a whole.

Moreover, in the level conversion circuit of FIG. 27 (a), the delay time from the change of the input Vin (11) in synchronization with the clock signal to the output thereof is td1 in FIG. 27 (b).
This delay time td1 is mainly with respect to the power supply potentials VH (90) and VL (91) which are the source potentials of the PMOSFET (4) and the NMOSFET (7) which are the input gates. , The input is determined by the time required for the threshold voltage of the PMOSFET (4) and the NMOSFET (7) to become lower or higher, respectively, but the power supply potential VH (90) is set to further reduce the output amplitude. When the value is set lower and the value of power supply potential VL (91) is set higher, the input becomes lower potential Vss or higher potential Vcc.
If it is not close to, the PMOSFET (4) and the NMOSFET (7) do not turn on, and the delay time td1 increases.

Therefore, in order to avoid the power loss of the internal power supply circuit described above, Japanese Patent Application Laid-Open No. 4-302463 (Takashima et al.
The technology disclosed by Toshiba is proposed. As shown in FIG. 29 (a), this technique uses a circuit 500 having the same power supply current change characteristic with respect to time, that is, the same ON resistance.
Is connected in series between the power supply Vcc and the ground line Vss, and the terminal voltage effectively applied to each circuit is set to 1/2 of the power supply Vcc. In other words, this technique is shown in FIG.
As shown in (b), the power supply current is the same at each point of time change, that is, by connecting each circuit in series with the same internal on-resistance of the circuit as shown in FIG. While operating, it causes a voltage drop to perform the same function as the internal power supply circuit of the first conventional example.

[0012]

However, in the prior art shown in FIG. 29, if the power supply current of each circuit is not equal to each time, the voltage determined by the resistance division fluctuates, and the effective voltage of each circuit is changed. It has the drawback that the terminal voltage varies. In addition, since the power supply current of each circuit needs to be supplied by the ground current of the circuit that is one stage above itself,
9 (b), that is, if the power supply current and ground current (I1 and I1X) and (I2 and I2X) of each circuit 500 are not equal at each time, the current cannot be reused. DRAM
Considering the sense amplifier operation that performs parallel operation and restores the bit line potential that consumes a large amount of current, in general, in order to prevent a shoot-through current between the power supply of each circuit and ground, Because the size and wiring resistance of the transistors that perform each function are changed so that there is a time difference automatically between the charging operation that flows and the discharging operation that the ground current flows,
It is impossible to make the charge current and the discharge current of each circuit equal at each time without increasing the through current. Therefore, in order for the upper and lower circuits 500 and 500 to perform the same operation, it is necessary to supply a current from the additional circuit to the lower circuit 500, and even with this conventional technique, it is still necessary to drive the wiring capacitance. There is a drawback that wasteful current consumption other than the necessary current consumption is required.

The present invention has been made in view of the problems of the first and second prior arts, and an object thereof is to provide a conventional wiring capacitance regardless of the number of level conversion circuits operating simultaneously. The wiring capacitance on the output side of the level conversion circuit is driven at low speed and at high speed without unnecessary power consumption other than the current consumption required to drive the It is to improve.

[0014]

In order to achieve the above object, the present invention uses a capacitor or the like to store electric charges and reuses the stored electric charges for changing the potential of an output node of a level conversion circuit. By doing so, it is possible to eliminate wasteful power consumption as in the past.

That is, the concrete structure of the level conversion circuit according to the first aspect of the present invention is such that a signal that changes to two different values is input and it operates in synchronization with a clock signal.
An inverter-type level conversion circuit for converting an amplitude value of the input signal into another amplitude value and outputting the amplitude value from a single output node, the first charge supply means being precharged to a first potential, A second charge supply unit that is precharged to a second potential different from the first potential and one of the two charge supply units are selected according to the input signal,
Discharge means for discharging the charge accumulated in the selected charge supply means to the output node.

According to a second aspect of the present invention, there is provided a concrete configuration of the level conversion circuit, wherein a signal which changes to two different values is input and the level conversion circuit operates in synchronization with a clock signal, and the amplitude value of the input signal. Is a complementary level conversion circuit that converts the signal to another amplitude value and outputs it from two output nodes, and a first charge supply unit that is precharged to a first potential,
Second charge supply means precharged to a second potential different from the first potential, and charge accumulated in the first charge supply means according to the input signal is output to the two outputs. The discharge means discharges to one of the nodes and discharges the charges stored in the second charge supply means to the other output node.

Further, in the invention according to claim 3, in the level conversion circuit according to claim 1 or 2, the output node is connected to the first potential of the first charge supply means and the second charge supply means. Is configured to include a precharge circuit for precharging to a third potential between the second potential and the second potential.

In addition, the invention according to claim 4 is the level conversion circuit according to claim 3, wherein in the complementary level conversion circuit, the precharge circuit is configured to short-circuit two output nodes. .

In addition, according to a fifth aspect of the present invention, there is provided a concrete configuration of the control method of the level conversion circuit, wherein the output node is set to the third potential by the precharge circuit in the first period within one cycle of the clock signal. And precharge the first charge supply means and the second charge supply means to a first potential and a second potential, respectively, during a second period within one cycle of the clock signal, In the third period after the first period and the second period within one cycle of the signal, the discharge unit discharges the charge precharged in the charge supply unit to the output node.

According to the invention of claim 6, claim 2
In the level conversion circuit described above, the first charge supply unit or the second charge supply unit is configured by a high-potential power supply line.

Further, in the invention according to claim 7, in the level conversion circuit according to claim 2, the first charge supply means or the second charge supply means is constituted by a low potential power supply line. is there.

In addition, the concrete constitution of the invention described in claim 8 specifies the charge supply means of the invention described in claim 1, 2 or 5, and the charge supply means is constituted by a capacitor, and The ratio between the capacitance value of the capacitor and the parasitic capacitance value of the output node is the potential difference between the potential of the output node desired to be realized and the second potential which is the precharge potential of the output node, and the precharge potential of the capacitor. 1
And the potential difference between the potential of the output node and the potential of the output node.

In addition, the semiconductor integrated circuit according to a ninth aspect of the present invention has a specific configuration in which a signal that changes to two different values is input and the signal operates in synchronization with a clock signal. A plurality of level conversion circuits for converting an amplitude value into another amplitude value and outputting it from the output node are provided, and electric charge transfer at the output node is performed between two level conversion circuits of the plurality of level conversion circuits. Charge amount change characteristic equalizing means for setting charge amount change characteristics having opposite directions and the same absolute value of charge with respect to time and two level change circuits having the same charge amount change characteristics. And a charge redistribution means for moving the electric charges.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit according to the ninth aspect, the plurality of level conversion circuits each have a complementary level having two output nodes whose outputs are complementary. The configuration is a conversion circuit.

Further, the invention according to claim 11 is the semiconductor integrated circuit according to claim 10, wherein the plurality of level conversion circuits are one level conversion circuit according to claim 6.
It comprises one level conversion circuit according to claim 7, wherein the two level conversion circuits are arranged in series between a high-potential power supply line and a low-potential power supply line.

Further, the invention according to claim 12 is the semiconductor integrated circuit according to claim 10, wherein the plurality of level conversion circuits are the one or more level conversion circuits according to claim 2. One level conversion circuit according to item 6;
A single level conversion circuit according to claim 7, wherein the plurality of level conversion circuits are arranged in series between a high-potential power line and a low-potential power line.

According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit according to the tenth, eleventh or twelfth aspect,
The transistor of the level conversion circuit that outputs a higher potential from the output node than the potential of the intermediate value between the potential of the high-potential power line and the potential of the low-potential power line is composed of a P-type MOSFET and has a low potential. The transistor of the level conversion circuit which outputs from the output node is composed of an N-type MOSFET.

Further, in the invention described in claim 14, in the semiconductor integrated circuit according to claim 10, 11, 12 or 13, the charge amount change characteristic equalizing means has two outputs whose parasitic capacitance values are substantially the same. It is composed of a precharge means for precharging the node to the same potential, a charge storage means for storing charges, and a charging means for charging the charge storage means to a potential different from the predetermined potential.

In addition, in the invention described in claim 15, in the semiconductor integrated circuit according to claim 14, the charging means is:
The charge storage means is configured to be charged to a potential between the respective precharge potentials of the two level conversion circuits that perform charge redistribution.

Further, the invention according to claim 16 is the semiconductor integrated circuit according to claim 15, wherein the charge storage means is shared by two level conversion circuits for performing charge redistribution. Is.

According to a seventeenth aspect of the present invention, in the semiconductor integrated circuit according to the sixteenth aspect, the charge storage means is shared by two level conversion circuits for redistributing charges, and the charging means is charge. The charge is alternately charged in the vicinity of the precharge potential of one level conversion circuit and the vicinity of the precharge potential of the other level conversion circuit for redistributing, and the inputs of the two level conversion circuits are signal changes. This is a configuration in which the cycles are set to be shifted from each other by a half cycle.

Further, the invention according to claim 18 is the semiconductor integrated circuit according to claim 14 or 15, wherein the charge redistribution means is one of both charge storage means of the two level conversion circuits for redistributing charges. , One of the two level conversion circuits is connected to the output node on the side that changes to the high potential side, and the other charge storage means is connected to the output node on the side that changes to the low potential side on the other level conversion circuit. This is a configuration that is connected to an output node.

Further, in the invention described in claim 19, in the semiconductor integrated circuit according to claim 10, the charge amount change characteristic equalizing means is provided with two parasitic capacitance values which are substantially the same in each level conversion circuit. The output node is precharged to a predetermined potential, and the potential difference between the precharge potentials of the respective level conversion circuits is set to the same value or the ratio of the reciprocal of the parasitic capacitance value of each of the level conversion circuits. .

According to a twentieth aspect of the present invention, in the semiconductor integrated circuit according to the nineteenth aspect, the charge redistribution means is a level conversion circuit in which two precharge potentials are adjacent to each other to perform charge redistribution. The configuration is such that one level conversion circuit short-circuits the output node that changes to the low potential side in response to the input and the other level conversion circuit the output node that changes to the high potential in response to the input.

Further, in the semiconductor integrated circuit control method according to the present invention, the two output nodes in each level conversion circuit are precharged to the same potential in the first period within one cycle of the clock signal. , Between the two precharge potentials of the two level conversion circuits for redistributing the charge in the respective charge storage means of the two level conversion circuits for redistributing the charge in the second period within one cycle of the clock signal. Both charge storages of the two level conversion circuits that are charged to a predetermined potential and then redistribute the charges in a third period after the first period and the second period within one cycle of the clock signal. One of the means is connected to the output node on the side that changes to the high potential side in one of the level conversion circuits of the two level conversion circuits for redistributing charges, and the other charge storage means is connected to the other level conversion circuit. Change to low potential side It is configured to connect to the output node of the side to be.

According to a twenty-second aspect of the present invention, in the method for controlling a semiconductor integrated circuit according to the twenty-first aspect, a potential for charging two charge storage means in a second period within one cycle of a clock signal. Is a potential between both precharge potentials of the two level conversion circuits for redistributing charges.

In addition, the invention according to claim 23 is the method for controlling a semiconductor integrated circuit according to claim 21, wherein two charge accumulating means are charged in a second period within one cycle of the clock signal. The electric potential is
The precharge potential of one of the two level conversion circuits for redistributing charges is approximately the same as the precharge potential of the other level conversion circuit, and the charge storage unit of the other is approximately the same potential as the other precharge potential of the two level conversion circuits for redistributing charges. It is a structure that is.

According to a twenty-fourth aspect of the invention, in the control method of the level conversion circuit or the semiconductor integrated circuit according to the fifth, 21, 22 or 23, the first period and the second period are the same period. It is a structure that is.

Further, a twenty-fifth aspect of the present invention is a control method for controlling the semiconductor integrated circuit according to the nineteenth or twentieth aspect, wherein each level conversion circuit has a predetermined period within one cycle of the clock signal. Two output nodes are precharged to the same potential, and then the charge is redistributed during a period after the predetermined period within one cycle of the clock signal.
One of the level conversion circuits has a configuration in which one level conversion circuit connects the output node on the side that changes to the high potential side and the other level conversion circuit connects the output node on the side that changes to the low potential side.

In addition, the invention according to claim 26 is the semiconductor integrated circuit according to claim 9 or 10,
It is a structure that is provided between two power supply terminals and has a through current prevention unit that controls so that a through current does not flow between the two power supply terminals.

According to a twenty-seventh aspect of the present invention, in the semiconductor integrated circuit of the twenty-sixth aspect, the through current preventing means is composed of a plurality of transistors, and controls so that the plurality of transistors are not simultaneously turned on. It is a structure that is one.

Further, the invention according to claim 28 is the semiconductor integrated circuit according to claim 27, wherein the plurality of transistors are controlled by independent control signals different from the input to the level conversion circuit.

In addition, the invention according to claim 29 is the level conversion circuit according to any one of claims 1, 2, 3, 4, 5, 6, 7 or 8, wherein the level conversion circuit is controlled. Are provided in plural, and the output nodes respectively provided in some of the plurality of level conversion circuits are connected in parallel with each other, and the plurality of output nodes connected in parallel are the first charge supply means or the second charge supply means. It is connected to the electric charge supply means.

According to a thirtieth aspect of the present invention, in the level conversion circuit or the level conversion circuit control method according to the first, second, third, fourth, fifth, sixth, seventh or eighth aspect, a plurality of level conversion circuits Output nodes that are individually provided and provided in a part of the plurality of level conversion circuits are connected in series to each other, and each of the plurality of output nodes connected in series is the first charge supply unit or the second charge supply unit. It is connected to the electric charge supply means.

The thirty-first aspect of the invention is the level conversion circuit according to the sixth aspect, wherein the high-potential power supply line is a high-potential external power supply line.

In addition, a thirty-second aspect of the present invention is the level conversion circuit according to the sixth aspect, wherein the high-potential power supply line is a high-potential internal power supply line.

Further, the invention of claim 33 is the level conversion circuit according to claim 7, wherein the low-potential power supply line is a low-potential external power supply line.

According to a thirty-fourth aspect of the present invention, in the level conversion circuit according to the seventh aspect, the low potential power supply line is a low potential internal power supply line.

Furthermore, a thirty-fifth aspect of the present invention is the semiconductor integrated circuit or the method for controlling a semiconductor integrated circuit according to the nineteenth, twenty-eighth or twenty-fifth aspect, wherein the plurality of level conversion circuits include a first power supply and Among the plurality of level conversion circuits, the level conversion circuit, in which the degree of change of the output node with time is large, is arranged in series with the second power supply having a potential different from the potential of the first power supply, It is arranged at a position closer to the first power supply or the second power supply than the remaining level conversion circuit.

In addition, according to the invention of claim 36, in the semiconductor integrated circuit or the method of controlling a semiconductor integrated circuit according to claim 35, the level conversion circuit constituted by a P-type MOSFET is close to a power supply having a high potential. It is a structure arranged on the side.

Further, in the invention described in Item 37, in the method for controlling the semiconductor integrated circuit or the semiconductor integrated circuit according to Item 35, the level conversion circuit constituted by an N-type MOSFET is a power source having a low potential. It is a structure arranged on the near side.

According to a thirty-eighth aspect of the present invention, in the semiconductor integrated circuit of the ninth aspect, the plurality of level conversion circuits are provided, and among the plurality of level conversion circuits, a plurality of level conversion circuits having the same degree of change of the output node with respect to time are provided. Circuit comrades are the first
And a second power source having a potential different from the potential of the first power source.

Further, in the semiconductor device of the present invention according to claim 39, in the semiconductor integrated circuit according to claim 38, the plurality of level conversion circuits are grouped by level conversion circuits having the same degree of change of the output node with respect to time. The level conversion circuits belonging to each group are arranged in series between the first power supply and the second power supply.

In addition, in the invention according to claim 40, in the level conversion circuit according to claim 39, a group of level conversion circuits having a large degree of change of the output node with respect to time and a degree of change of the output node with respect to time. In the group of level conversion circuits having a small value, the operation clock cycle is different.

In addition, the invention according to claim 41 is the semiconductor integrated circuit according to claim 19, 20 or 25, or the method for controlling a semiconductor integrated circuit, wherein the charge amount change characteristic equalizing means is one of the plurality of level converters. In this configuration, the connection with the power supply is controlled in a cycle that is an integral multiple of the cycle of the operation clock of the circuit.

The invention described in Item 42 is the semiconductor integrated circuit according to any one of Items 9 to 41, wherein
Potential detecting means for detecting the potential of the corresponding output node is connected to the output nodes of the plurality of level conversion circuits arranged in series between the second power source and the second power source. Among the potential detection means, the potential detection means corresponding to the output node of the level conversion circuit on the side where the precharge potential of the output node of the level conversion circuit is higher than the intermediate potential between the first power supply and the second power supply is , N-type MOSFETs, and the potential detecting means corresponding to the output node of the level conversion circuit on the side lower than the intermediate potential is a P-type MOSFET.

Furthermore, the invention of claim 43 is the semiconductor integrated circuit of claim 42, wherein the output of the potential detecting means composed of N-type MOSFETs is an N-type pair of CMOS flip-flop circuits. The output of the potential detection circuit, which is connected to each source part of the transistor and is composed of a P-type MOSFET, is connected to each source part of the P-type pair transistor of the CMOS flip-flop circuit.

In addition, the invention described in Item 44 is a control method for controlling the semiconductor integrated circuit according to Item 9,
The output from each output node of the plurality of level conversion circuits is
The two or more pieces of parallel data are transferred to the outside as two or more pieces of parallel data, and each of the two or more pieces of parallel data is divided into a plurality of ranges within a finite potential difference between the potential of the first power supply and the potential of the second power supply. The voltage is transferred to the outside by using the voltage range.

Further, the invention of claim 45 is the control method of the semiconductor integrated circuit according to claim 44, wherein the number of divisions of the finite potential difference is the same as the number of parallel data transfers.

According to a forty-sixth aspect of the invention, in the semiconductor integrated circuit of the ninth aspect, the plurality of level conversion circuits apply a first power source and a potential different from the potential of the first power source. Is arranged in series with a second power source that has,
A decoupling capacitor having a relatively large capacity is connected between the first power source and the second power source. To do.

Further, the invention according to claim 47 is the semiconductor integrated circuit according to claim 46, wherein the first power supply and the second power supply are internal power supplies, and the first internal power supply and the second internal power supply. In this configuration, a decoupling capacitor is connected between the power supply and the power supply.

In addition, in the invention described in Item 48, in the semiconductor integrated circuit according to Item 46, the first power source and the second power source are external power sources, and the first external power source and the second external power source. A number of decoupling capacitors equal to the number of level conversion circuits are connected to an external power supply, and each decoupling capacitor is connected to a node between two corresponding level conversion circuits. is there.

Further, in the invention described in Item 49, in the semiconductor integrated circuit according to Item 9, the plurality of level conversion circuits are different from each other in potential of the first power source and the first power source. Among the plurality of level conversion circuits, a level conversion circuit connected to the first power supply or a level conversion circuit connected to the second power supply, which is arranged in series with a second power supply having a potential. The output of the circuit is the unused configuration.

According to a 50th aspect of the present invention, in the semiconductor integrated circuit according to the 49th aspect, the number of the plurality of level converting circuits is the level converting circuit connected to the first power source or the second power source. With the exception of the level conversion circuit connected to, the number of parallel data is equal to the required number.

[0065]

With the above structure, in the level conversion circuit according to any one of claims 1 to 8 and claim 31 to claim 34, the charge is accumulated in the charge supplying means, and the charge is discharged to the output node to output. Change the potential of the node.

In this case, in the level conversion circuit according to claim 8, when the capacitance value of the charge supply means (capacitor) is 1/10 of the parasitic capacitance value of the output node of the level conversion circuit, the output node The output amplitude value is level-converted to 1/10 of the input amplitude value.

Here, since the operation of the level conversion circuit is performed by discharging the charge supply means, it is not necessary to provide an internal power supply circuit as in the conventional case, and therefore unnecessary current consumption is not increased due to through current. .

Further, claim 9 to claim 28, claim 44.
According to the forty-fifth aspect of the invention, in the two level conversion circuits connected in series, the electric charge emitted from the output node that changes to the low potential side in one level conversion circuit is high in potential in the other level conversion circuit. Since it is reused for increasing the potential of the output node which changes to the side, the power consumption can be reduced accordingly.

Particularly, in the invention described in claim 21, the electric charge emitted from the output node changing to the low potential side is accumulated in the charge accumulating means, and the accumulated charge is increased to the potential of the output node changing to the high potential side. In the invention described in claim 25, the output node itself is used as the charge storage means, and the output node that changes to the low potential side in one level conversion circuit is directly changed to the low potential side in the other level conversion circuit. Since the charge is reused by being connected to the output node, the charge storage means becomes unnecessary.

In the inventions according to claims 29 and 30, a small capacitance is created by increasing the number of level conversion circuits connected in series, and conversely by increasing the number of parallel connection of level conversion circuits. Since a large capacitance is created and the effective capacitance can be electrically controlled, the output amplitude distribution can be controlled easily.

In addition, in the inventions according to claims 35 to 37, the level conversion circuit in which the degree of change of the output node with respect to time is large, for example, the level conversion circuit in charge of the least significant bit when the address is incremented. With regard to the above, since it is arranged at a position close to the power supply line, the substrate bias voltage of the MOSFET that constitutes the level conversion circuit is reduced, and its operation delay time is shortened.
The operational stability of the entire circuit is improved.

In addition, in the inventions of claims 38 to 40, the plurality of level conversion circuits are level conversion circuits having the same degree of change of the output node with respect to time, and the first power supply and the first power supply. Since it is arranged in series between the first power supply and the second power supply, the level conversion circuit is arranged between the first power supply and the second power supply. The operating frequency can be made different from that of the level conversion circuit arranged between, and a large reduction in power consumption is possible.

Further, according to the forty-first aspect of the invention, in the level conversion circuit which receives the electric charge from the power source, the electric charge is supplied from the power source in a cycle which is an integral multiple of the cycle of the operation clock, so that the power consumption can be reduced. .

In addition, in the invention described in claims 42 and 43, a potential detection circuit composed of an N-type MOSFET,
Since the potential detection circuit composed of the P-type MOSFET is used in a range where the amplification delay is small, the output potential (reference level) of the level conversion circuit is detected with high sensitivity.

In addition, according to the 46th to 48th aspects of the invention, noise generated in the power supply line is caused by the decoupling capacitor having a large capacity, which is arranged between the high potential power supply line and the low potential power supply line. Is limited by the impact of
The stability of the operation of the semiconductor integrated circuit is enhanced.

Further, in the inventions of claims 49 and 50, even if noise occurs in the power supply voltage or the ground line voltage, the effect is only on the level conversion circuit to which the power supply voltage or the ground line voltage is applied. Is directly received, and the influence of the noise does not appear in the output of the other level conversion circuit located in the middle. Therefore, parallel data can be output without being affected by noise.

[0077]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic diagram of a circuit according to the first embodiment of the present invention. FIG. 1 shows an inverter type level conversion circuit which operates in synchronization with a clock signal. In the figure, Vin is an input node, Vout is an output node, 2 and 3 are complementary clock signals CLK, XCLK, Vcc are external power supply lines on the high potential side, Vss is a power supply line on the low potential side and are composed of ground lines. To be done. VM is a power supply line having an intermediate potential ((Vcc-Vss) / 2) between the high potential Vcc and the low potential Vss.

Further, 1a is a first capacitor,
It functions as a first charge supply unit that discharges the charged charge. Similarly, reference numeral 1b is a second capacitor as a second charge supply means for discharging the charged charge.

Further, 9 is a discharging means, which is composed of two PMOSs.
It is composed of FETs 4 and 5 and two NMOSFETs 6 and 7. Further, 11 is a precharge circuit, which is one NM
It is composed of OSFET 8 and one PMOSFET 12. Further, 70 is a PMOSFET and 71 is an NMOSFET.
At the time of ON operation, the corresponding power supply lines Vcc and Vss are connected to the corresponding capacitors 1a and 1b to be charged.

The capacitance values CV of the two capacitors 1a and 1b are equal to each other, and the capacitance value CV and the output node V
The ratio to the parasitic capacitance value of out is the output node Vou that you want to realize.
potential of t and precharge potential of the output node Vout
The potential difference from (Vcc / 2) and the capacitors 1a and 1b
The first potential (Vcc (for example, 3.
0V), Vss (0V)) and the potential difference between the potential of the output node Vout desired to be realized, and the ratio is set. For example, when the output parasitic capacitance is 3 pF, the capacitance value CV of the capacitor is 0.3 pF.

Next, the control method of the level conversion circuit of FIG. 1 will be described with reference to FIG.

The input Vin is a signal that changes to two different values as shown in FIG. In addition, PMOSFET 4 and NMOSFE
T 7 is controlled by the input Vin, and the other PMOSFETs 5, 12,
Reference numeral 70 is the clock signal CLK (3) shown in FIG.
6, 8 and 71 are respectively controlled by the inverted clock signal XCLK (2) shown in FIG.

That is, as shown in FIG. 2, in the half cycle (first period) α of the clock signal CLK (3), the two MOSFETs 8 and 12 of the precharge circuit 11 output the power supply line VM of the intermediate potential. Connect to node Vout and output node Vout
Is precharged to an intermediate potential. Furthermore, in this half cycle α, the PMOSFET 5 and NMOSFET 6 of the discharging means 9 are further turned on.
FF and turn PMOSFET 70 and NMOSFET 71 to O
The external power supply line Vcc on the high potential side is set to the first
The external power supply line Vss on the low potential side is connected to the second capacitor 1b of the capacitor 1a, and each is charged to a high potential and a low potential. The capacitors 1a and 1b are charged in the period α (same time as the first period), but in order to output the charged charges to the output nodes Vout and XVout, it may be in a stage before the output, It may be a period (second period) different from the precharge period of the output node.

Thereafter, in the half cycle (third period) β after the half cycle α of the clock signal CLK (3), the precharge by the precharge circuit 11 is stopped and the PMOSFE
Turn off the T 70 and NMOSFET 71 and turn on the condenser 1
The charging of a and 1b is stopped, and at the same time, the PMOS of the discharge circuit 9 is
Turn on FET 5 and NMOSFET 6. In the discharge circuit 9,
Either PMOSFET 5 or NMOSFET 6 is turned on according to the input Vin, and accordingly, either one of the capacitors 1a,
The electric charge charged in 1b is discharged to the output node Vout through the discharging circuit 9.

Therefore, in the present embodiment, the voltage level of the output node Vout is made to have a small amplitude by the charge redistribution without power loss from the capacitors 1a and 1b.
Unlike the conventional case, it is not necessary to build a low power supply voltage inside the chip, and the direct current-like through current consumed by the extra internal power supply circuit increases the current consumption, and the internal power supply circuit It is possible to avoid consuming extra power due to the voltage drop.

The source voltage of the input MOSFETs 4 and 7 is
The high side of the capacitors 1a and 1b holds a high voltage near the power supply voltage Vcc, and the low side holds a low voltage near the ground voltage Vss at the initial stage of operation, so that the input MOSF is effective.
The ETs 4 and 7 are easily turned on, and therefore, the delay time td1 in the case of obtaining an output with a small amplitude unlike the conventional case is not increased, and the delay time td2 of the present embodiment can be reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG.

This embodiment shows an embodiment applied to a level conversion circuit having complementary inputs and outputs. In the figure, Vi
n and XVin are complementary inputs, and Vout and XVout are complementary output nodes. 9'is a discharging means, and two NMOSFETs 13 and 13 arranged on the input side and two PMOSFETs.
14 and 14. Reference numeral 11 'denotes a precharge means, which is composed of a PMOSFET 17 arranged on the output side. Reference numerals 1a and 1b are capacitors as charge supplying means similar to those in the first embodiment. 19 is an NMOSFET
, 20 is a PMOSFET, Vc is a power supply line of a predetermined potential, Vs is a power supply line of another potential lower than the power supply line Vc,
It is composed of a ground wire. The capacitor 1a is charged to the potential of the power source line Vc, and the other capacitors 1b are charged to the potential of the power source line Vs.

The two NMOSFETs 13 of the discharging means 9 ',
13 is a complementary output node V for charging the capacitor 1a.
can be discharged to out and XVout, and the two PMOSFETs
14 and 14 can discharge the electric charge of the capacitor 1b to complementary output nodes Vout and XVout. Also, the PMOSFET 17 of the precharge means 11 'precharges the complementary output nodes Vout and XVout to the same potential by short-circuiting the complementary output nodes Vout and XVout.

The capacitors 1a and 1b have the same capacitance value CV, and this capacitance value CV is equal to each output node V
The parasitic capacitance values of out and XVout are set to the same value, and the ratio of the parasitic capacitance value to each of the parasitic capacitance values is the output nodes Vout and XV desired to be realized.
out Mutual output amplitude values and the capacitors 1a and 1b
Is set to be the ratio of the potential difference between each of the potentials for charging the output nodes and the precharge potentials of the output nodes Vout and XVout.

Next, a method of controlling the level conversion circuit shown in FIG. 3 will be described. Two NMOSFETs 1 on the input side of the discharge circuit 9 '
One of 3 and 13 and one of the two PMOSFETs 14 and 14 are controlled by either of complementary inputs Vin and XVin, and the other NMOSFET 13 and PMOSFET 14 are controlled by the remaining complementary inputs. In addition, the precharge circuit 11
'PMOSFET 17 and PMOSFET 20 are set to clock signal CL
It is controlled by K and the NMOSFET 19 is controlled by the inverted clock signal XCLK. The complementary clock signals CLK, XCLK and the complementary inputs Vin, XVin are shown in FIG.

The operation of the level conversion circuit shown in FIG. 3 will be described with reference to FIG.

In FIG. 5, in the first half cycle α within one cycle of the clock signal, that is, during the period when the complementary inputs Vin and XVin have the same value, the PMOSFET 1 of the precharge circuit 11 'is
7, the complementary output nodes Vout and XVout are short-circuited and precharged to the same potential. Further, in this half cycle α, the four MOSFETs 13 and 14 of the discharge circuit 9 ′ are turned on.
NMOSFET 19 and PMOSFET 20 are turned on at the same time as FF
Then, the capacitor 1a is charged to the low potential of the power line Vs on the low potential side, and the capacitor 1b is charged to the power line Vs on the high potential side.
The high potential of c is charged.

Next, in the latter half half cycle β of one cycle of the clock signal, that is, in the period in which a predetermined potential difference appears in the complementary inputs Vin and XVin, the PMOSFET 1 of the precharge circuit 11 'is turned on.
7, the NMOSFET 19 and the PMOSFET 20 are turned off, the upper NMOSFET 13 and the lower PMOSFET 14 of the discharge circuit 9 ′ are turned on, and the electric charge of the capacitor 1a charged to the low potential is discharged to one output node Vout. At the same time, the electric charge of the capacitor 1a charged to a high potential is discharged to one output node XVout. As a result, the following potential difference (amplitude value) ΔV appears at the complementary output nodes Vout and XVout.

ΔV = 2 × Vcc (1 + CD / CV) CD: Complementary output nodes Vout, XVout parasitic capacitance values) Therefore, also in this embodiment, similarly to the first embodiment, the capacitors 1a, 1b are connected to the capacitors 1a, 1b. Of the output nodes Vout and XVout which are complementary to each other by the charge redistribution without power loss of
Since the voltage level of the power supply is set to a small amplitude, the current consumption increases due to the shoot-through current when a low-voltage power supply voltage is built into the chip as in the past, and extra power is generated due to the voltage drop in the internal power supply circuit. The consumption of can be avoided.

(First Modification of Second Embodiment) FIG. 4 shows a level conversion circuit obtained by modifying a part of the level conversion circuit of FIG. The level conversion circuit of FIG. 4 is different from the level conversion circuit of FIG. 3 in that the capacitor 1a charged to a low potential and the capacitor 1b charged to a high potential are provided in the level conversion circuit of FIG. A period in which one of the plate electrodes of the capacitor 1 is charged to a high potential of the power source line Vc and the other plate electrode is charged to a low potential of the power source line Vs, and a predetermined potential difference appears between the complementary inputs Vin and XVin. In β, each plate electrode of the capacitor 1 is connected to one of the complementary output nodes Vout and XVout.

According to this modification, since the number of capacitors can be reduced from two to one as compared with the second embodiment, the layout area of the capacitors can be reduced by half.

(Second Modification of Second Embodiment) FIG.
(A) And (b) shows the 2nd modification of the level conversion circuit of the said FIG. In FIG. 3, instead of providing the two capacitors 1a and 1b as the charge supplying means, only one capacitor 1 (charge supplying means) is provided, and the other charge supplying means are high in FIG. 3 (a). In the same figure (b), it is composed of a low-potential power source line Vss, and in the same figure, it is composed of a low-potential power source line Vss.
When either one of the OSFETs 13 and 13 is turned on, the charge of the high-potential power source line Vcc and the low-potential power source line V are respectively supplied.
The electric charge of ss is discharged to one of the complementary outputs Vout and XVout through the turned-on NMOSFET 13. Other configurations are the same as those in FIG. 3, and thus description thereof will be omitted.

(Third Embodiment) FIG. 7 shows a semiconductor integrated circuit according to a third embodiment of the present invention, in which the complementary level conversion circuit of FIG. 6A is arranged in the upper stage. The complementary level conversion circuit of b) is arranged in the lower stage. In the upper level conversion circuit, the two input gate MOSFETs 16 and 16 are
Two MOSFs in the lower level conversion circuit consisting of PMOSFETs
The ETs 15 and 15 are composed of NMOSFETs, and the MOSFET 18 constituting the precharge circuit is also composed of NMOSFETs.

The capacitors 1a and 1b are respectively NM
It is connected to the power supply line VM of intermediate potential through the OSFETs 20a and 20b. The middle potential of the power supply line VM is the high potential power supply line V.
It is an intermediate potential (VM = (Vcc-Vss) / 2) between the potential of cc and the potential of the low-potential power supply line Vss. 2 above
NMOSFETs 20a and 20b are both inverted clock signals XC
Controlled by LK. Reference numeral 21 in the drawing is an NMOSFET for making the potentials of the two capacitors 1a and 1b common, and is controlled by the inverted clock signal XCLK.

Since the other structure is the same as the structure shown in FIGS. 6A and 6B, the corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

Next, a method of controlling the semiconductor integrated circuit will be described.

As shown in FIG. 8, the complementary inputs Vin1 and XVin1 of the upper level conversion circuit are the input gate PMOSFET 16 and
It has the potential to turn ON / OFF the PMOSFET 14 completely, and complementary inputs Vin2 and XVin2 of the lower level conversion circuit.
Input gate PMOSFET 13 and PMOSFET 15 completely turned on
And has a potential that can be turned off.

As shown in the figure, in the first half period α within one period of the clock signal, that is, in the period where the complementary inputs are equal to each other, the complementary output nodes Vout1, XVout1 and Vout2 and XVout2 are PMOSFE respectively
It is equalized by turning on T 17 and NMOSFET 18. Also, during this period α, the two NMOSFETs 20a, 2
When 0b is turned on, both capacitors 1a and 1b are precharged to the intermediate potential by the intermediate potential power supply line VM.

After that, a potential difference is generated between the complementary inputs during the latter half period β of one cycle of the clock signal, and the input XVin1 is lowered to the low potential Vss, and the input Vin2 is input.
In the period in which the voltage rises to the high potential Vcc, in the upper level conversion circuit, the high potential power supply line Vcc passes through the PMOSFET 16 on the side controlled by the input XVin1 and outputs one output node X.
This output node XVout1 rises to a high potential by being connected to Vout1, and the other output node Vout1 is connected to the capacitor 1a via the PMOSFET 14 on the side controlled by the input XVin1 and is connected to the other output node Vout1. The current Iu flows toward the capacitor 1a.

On the other hand, in the period β, in the lower level conversion circuit, the low-potential power supply line Vss passes through the NMOSFET 13 on the side controlled by the input Vin2 and outputs one output node Vou.
When connected to t2, this output node Vout2 has a low potential Vss.
At the same time, the other output node XVout2 is connected to the capacitor 1b via the NMOSFET 15 on the side controlled by the input Vin2, and the current IL flows from the capacitor 1b to the other output node XVout2, The output node XVout2 rises above the precharge potential in the period α.

Here, the electric charge charged in the capacitor 1a by the current Iu flowing from the output node Vout1 of the upper level conversion circuit results in the output node XVou from the capacitor 1b of the lower level conversion circuit by the current IL.
It is charged at t2 and the charge is reused.

Therefore, in this embodiment, since the charges can be reused by the two level conversion circuits, the power consumption can be further reduced.

The capacitance value C of each capacitor 1a, 1b
As in the first embodiment, V is the ratio of the parasitic capacitance value CD of the output node to the output amplitude value of the output node desired to be realized, the charging potential VM of each of the capacitors 1a and 1b, and the precharge of the output node. Potential difference from the potential (ie, about Vcc /
It is set to the ratio with 2). For example, when the output amplitude value of the output node to be realized is Vcc / 10, CV:
CD is a ratio of 2:10.

(Modification of Third Embodiment) FIG. 9 shows a modification of the third embodiment. In FIG. 7, two capacitors 1a and 1b are used for storing the high potential side potential and the low potential side potential. Instead of being provided for storage, paying attention to the plate electrode on the side connected to ground, both plate electrodes of one capacitor 1 are respectively connected to the output nodes on the side that changes to the low potential side of the upper level conversion circuit. And the output node on the side that changes to the high potential side of the lower level conversion circuit are connected to store the respective potentials. Therefore, the number of capacitors can be reduced from two to one, and the layout area of the capacitors can be reduced by half.

(Fourth Embodiment) FIG. 10 shows a fourth embodiment of the present invention. In the embodiment of FIG. 7, each capacitor 1
Although the ratio between the capacitance value CV of a and 1b and the parasitic capacitance value CD of the output node is set to 2:10, this ratio is set to 1:10 to reduce the capacitance value CV of each capacitor 1a and 1b. It is configured to reduce the layout area of the capacitors. Specifically, each capacitor 1
The potential difference between a and 1b and each output node before the short circuit is approximately V
The configuration is set from cc / 2 to about Vcc which is twice as high as that.

That is, in FIG. 10, the charge supply means 700 surrounded by a broken line is composed of two capacitors 1a and 1b.
And has four switches SW1 to SW4. As shown in FIGS. 11 and 12, the four switches SW1 to SW4 are controlled by complementary signals WCLK and XWCLK which change every one cycle of complementary clock signals CLK and XCLK.
During the period γ shown in, the two switches SW1 and SW3 are turned on.
And turn off the other two switches W2 and SW4
On the other hand, in the subsequent period δ, the reverse operation is performed.

Therefore, during the half cycle period ε of the clock signal of FIG. 12, for example, the input XVin of the upper level conversion circuit is input.
When the PMOSFET 14 on the side controlled by 1 is turned on, one output node Vout1 (on the side where the potential drops) is connected to the capacitor 1a, and the potential of this capacitor 1a becomes close to the high potential of the power supply line Vcc on the high potential side. And the output node XVout2 on one side (potential rising side) is connected to the capacitor 1b by turning on the NMOSFET 15 on the side controlled by the input Vin2 in the lower level conversion circuit, and the potential of this capacitor 1b increases. Goes down to near the low potential of the power supply line Vss on the low potential side. This state is maintained for the subsequent half cycle period η of the clock signal.

After that, the four switches SW1 to SW4
This time, the output node Vout1 or XV on the side where the capacitor 1b drops the potential in the upper level conversion circuit this time.
Connected to out1, the potential of the capacitor 1b rises to near the high potential of the power line Vcc on the high potential side, while the other capacitor 1a raises the potential in the lower level conversion circuit Vout2 or XVout2. And the potential of the capacitor 1a drops to near the low potential of the power source line Vss on the low potential side.

Therefore, the potential difference between each of the capacitors 1a and 1b and the output node connected to each of them can be set to about Vcc, so that each of the capacitors 1a and 1b can be set.
The ratio between the capacitance value CV of b and the parasitic capacitance value CD of the output node can be set as small as 1:10, and the layout area of each capacitor can be reduced.

(Modification of Fourth Embodiment) FIG. 13 shows a modification of the fourth embodiment, which is the charge supplying means 70 of FIG.
This is an example in which 0 is modified. The charge supply means 701 of FIG.
One capacitor 1 and two switches S connecting it to the upper level conversion circuit and the lower level conversion circuit
It has W1 and SW4. The two switches SW1,
SW4 is a complementary clock signal CL as shown in FIG.
During the half cycle period α of K and XCLJ, the switch SW1 is turned on and the switch SW4 is turned off, and the operation is reversed during the other half cycle period β.

Further, as shown in FIG. 15, the complementary inputs Vin1 and XVin1 of the lower level conversion circuit are changed by a half cycle from the complementary inputs Vin1 and XVin1 of the upper level conversion circuit.

Therefore, as shown in FIG. 15, during the half period period α of the clock signal, the capacitor 1 is switched to the switch S.
When W1 is turned on, it is connected to one of the complementary output nodes Vout1 and XVout1 of the upper level conversion circuit on the side where the potential drops (Vout1 in the figure), and the high potential power supply line Vc
After being charged in the vicinity of the high potential of c, the capacitor 1 is switched to the switch SW during the half-cycle period β of the clock signal thereafter.
When it is turned on, it is connected to one of the complementary output nodes Vout2 and XVout2 of the lower level conversion circuit (XVout2 in the figure) on the side where the potential rises, and its capacitor 1
Is discharged to the output node XVout2, and the capacitor 1 drops to a potential near the low potential of the low potential power supply line Vss.

Therefore, in this modification, one capacitor 1 is alternately connected to the output node near the high potential Vcc and the output node near the low potential Vss every half cycle of the clock signal. The ratio between the capacitance value CV and the parasitic capacitance value CD of the output node can be set as small as 1:10, and the layout area of each capacitor can be reduced.

(Fifth Embodiment) Next, a semiconductor integrated circuit according to a fifth embodiment of the present invention will be described with reference to FIG.

In the semiconductor integrated circuit of FIG. 16, three complementary level conversion circuits of different types are provided with a power supply Vcc and a ground line V.
It is connected in series with ss.

The middle level conversion circuit is the level conversion circuit shown in FIG. 3, the upper level conversion circuit is the level conversion circuit shown in FIG. 6A, and the lower level conversion circuit is the level conversion circuit shown in FIG. It is a level conversion circuit shown. However, all the MOSFETs in the middle level conversion circuit are NMOSFETs 24, 25, 26.
And the MOSFETs in the upper level conversion circuit are all PMOS
It consists of FETs 14, 16 and 17, and the MOSFETs in the lower level conversion circuit are all composed of NMOSFETs 13, 15 and 18.

The capacitor 1c included in the upper level converting circuit and one of the two capacitors 1d and 1e included in the middle level converting circuit are
Power supply line 22 of high potential Vu via three NMOSFETs 21 ...
And the other capacitor 1e of the middle level conversion circuit and the capacitor 1f of the upper level conversion circuit are connected to the power supply line 23 of low potential VL via three NMOSFETs 27 ... .

The high potential Vu of the power supply line 22 is 3 (Vc
c-Vss) / 4, and the low potential VL of the power supply line 23
Is set to (Vcc-Vss) / 4.

PMOSFET 1 of the upper level conversion circuit
7. The NMOSFET 24 of the middle level conversion circuit and the NMOSFET 18 of the lower level conversion circuit respectively short-circuit the corresponding two output nodes and precharge the two output nodes to the same potential. Functions as a charging means. Further, the four capacitors 1a to 1d constitute a charge storage means, and the power supply lines Vu and VL at the intermediate potentials respectively connect the capacitors 1a to 1d to the intermediate potentials VU and VL (potentials different from the output node precharge potential). ) Functions as a charging means. The precharge means, the charge storage means, and the charging means constitute the charge amount change characteristic equalizing means according to claim 9.

Furthermore, the PMOSFET 1 of the upper level conversion circuit
4. The NMOSFET 25 of the level conversion circuit in the middle stage and the NMOSFET 15 of the level conversion circuit in the lower stage each have a capacitor 1
a to 1d are assigned to the corresponding output nodes Vout1, XVout1, V
Connected to out2, XVout2, Vout3, and XVout3, a charge redistribution unit that redistributes the charge accumulated in each of the capacitors 1a to 1d to the output node is configured.

Next, the control method of the semiconductor integrated circuit of this embodiment will be described. As shown in FIG. 18, in the middle level conversion circuit, the level conversion circuit is operated in synchronization with complementary clock signals CLK and XCLK, NMOSFE in the half-cycle period α of the signal
T24 is turned on to short-circuit the complementary outputs VOUT2 and XVOUT2, and both outputs are precharged to approximately the midpoint potential (1/2 Vcc = Vc) between the low potential side power line 23 and the high potential side power line 22. At the same time, each of the capacitors 1b and 1c is charged to the potentials of the high-potential-side and low-potential-side power supply lines 22 and 23, and the nodes of the capacitors CV1b and 1c are charged in a half cycle period β thereafter. Complementary inputs Vin2 and XVIN
It is connected to complementary outputs Vout2 and XVout2 via NMOSFETs 25 and 26 on the side controlled to be ON by 2 respectively.

Similarly, the upper level conversion circuit also outputs complementary outputs Vout1 and XVout1 during the half cycle period α of the clock signal.
Is precharged to an intermediate potential of the respective potentials at the time of complementary output, and the capacitor 1a is charged to the potential Vu of the power source line 22 on the high potential side, and then in the half cycle period β,
The node A of the capacitor 1a and the power supply line V on the high potential side
cc and cc are connected to the complementary outputs Vout1 and XVout1 through the PMOSFETs 16 and 14 on the side controlled to be ON by the complementary inputs Vin1 and XVin1, respectively.

Similarly, the lower level conversion circuit also outputs complementary outputs Vout3 and XVou in the half period period α of the clock signal.
Precharge t3 to the intermediate potential of the respective potentials at the time of complementary output, charge both capacitors 1d to the potential VL of the power source line 23 on the low potential side, and the half cycle period β thereafter.
Then, the node D of the capacitor 1d and the power source line Vss on the low potential side are turned on by the complementary inputs Vin3 and XVin3, respectively.
It is connected to the complementary outputs Vout3 and XVout3 via NMOSFETs 13 and 15 on the side controlled by.

The complementary inputs Vin2, XVin2 and Vin3, XVin3 of the middle and lower level conversion circuits are:
As shown in FIG. 17, stand by at the ground potential Vss level,
Only one of the inputs is high potential Vcc after the input is confirmed.
, And complementary inputs Vin1 and XVin1 of the upper level conversion circuit wait at the high potential Vcc level, and only one of the inputs transitions to the ground potential Vss after the input is fixed. With such a setting, the flow of the through current due to the short circuit between the high potential power source line Vcc, the two medium potential power source lines Vu and VL, and the low potential power source line Vss is prevented. It constitutes a through current prevention means.

When the structure of the through current preventing means is different, for example, between the point A and the point A'in FIG.
And point B ′, between point C and point C ′, and between point D and point D
17 are respectively provided between the complementary clock signals CLK and ′ so that the complementary clock signals CLK and CLK do not turn on until one of the complementary inputs transitions to a potential lower than the threshold voltage of the input NMOSFET. XCLK (Complementary input Vin1, XV
It can be replaced by a configuration in which control is performed by a signal different from in1, Vin2, XVin2, Vin3, and XVin3.

Therefore, in this embodiment, FIG.
As shown in FIG. 3, during the half cycle period β of the clock signal, the charge discarded by the output node Vout1 or XVout1 on the side where the potential drops in the upper level conversion circuit, the output node Vout2 on the side where the potential rises in the middle level conversion circuit. Or XVou
The charges released from the output node Vout2 or XVout2 on the side of which the potential is lowered in the middle level conversion circuit while being used for raising the potential of t2 are the potential of the output node Vout3 or XVout3 on the side of which the potential is increased in the lower level conversion circuit. Used for climbing. Therefore, only one level conversion circuit in the upper stage needs to supply the charge from the outside, and the remaining 2
There is no need for new charge supply in each level conversion circuit,
Low power consumption is possible.

Here, the case where the n level conversion circuits are operated will be described by comparing the degree of reduction in power consumption obtained by the present embodiment with that of the above-mentioned conventional example.

When the internal power supply circuit is used to step down the voltage level as in the first conventional example (Japanese Patent Laid-Open No. 4-211515), the power supply voltage is Vcc, the output current is IH, and the stepped down voltage is VH. The power consumption in the internal power supply circuit is n
(Vcc-VH), and the power consumption of n circuits is n · I
Since H · VH, the total power consumption Ptotal is Ptotal =
n · IH · Vcc.

A second conventional example (Japanese Patent Laid-Open No. 4-302463)
As described above, when n circuits separately provided are operated in series to reduce the voltage, the applied voltage per circuit is Vcc / n, so the total power consumption Ptotal is Ptotal = (Vcc /
n · IH) · n + α = IH · Vcc + α. here,
The power consumption α is the power consumption due to the through current that flows when the voltage (Vcc-Vss) is resistance-divided, and the through current IH
Always flows from the power supply to the ground terminal in vain,
Can be expressed in IH and Vcc. Therefore, the total power consumption Ptotal
Becomes Ptotal = 2 · IH · Vcc.

On the other hand, in the present invention, as shown in the equivalent circuit of FIG. 19, a circuit in which n (three in the figure) level conversion circuits 501 ... Charge and discharge the same charge, that is, a capacitor whose potential fluctuates. Of the same level are connected to each other only when the output of each level conversion circuit 501 ... Is in a high impedance state, and the capacitor of the level conversion circuit located at the uppermost stage is charged. Since the plurality of level conversion circuits of No. 2 operate by reusing the charges from the level conversion circuit one stage above, the total power consumption Ptotal is Ptotal = IH.Vcc.

Therefore, as shown in FIG. 20, the present invention is
As in the case of the second conventional example, the three level conversion circuits operate in series and the power consumption is halved as compared with the case where a through current is generated.
It is possible to reduce the power consumption by 1 / n as compared with the power consumption generated when the voltage is dropped in the internal power supply circuit as in the first conventional example.

In this embodiment, three different types of complementary level conversion circuits are combined, but when four or more stages are arranged in series, the level conversion circuit of the type arranged in the middle stage of FIG. 16 is used. Can be realized by further connecting a plurality of the above. In this case, an intermediate value between the potential of the high-potential external power supply line Vcc and the potential of the low-potential external power supply line Vss ((Vcc + Vs
The level conversion circuit that outputs a potential higher than s) / 2) from the output node is composed of PMOSFETs, and the level conversion circuit that outputs a lower potential from the output node is composed of NMOSFETs. With this configuration, the voltage between the gate and the source of the MOSFET increases, and the operation can be stabilized.

Next, FIG. 21 shows a circuit for generating the above intermediate potentials Vu and VL. The intermediate potential generating circuit shown in the same figure is composed of current mirror type comparators 28, 29 and 30 which use a potential divided by four resistors R1, R2, R3 and R4 as a reference potential, and these comparators 28. .About.30 output MOSFETs 31-33.

Although the intermediate potential generation circuit is basically the same as the power supply circuit shown in FIG. 28 of the conventional example, the charge supply capability is significantly different from that of the conventional example, and the level conversion circuits of the middle and lower stages are different. Since the charges are reused, it is not necessary to supply new charges. That is, the intermediate potential generating circuit shown in FIG. 21 does not need to be provided as a charge supply function, and the only necessary time is necessary when deciding the first operating point when the power is turned on. That is, the output does not need to have a low resistance as in the conventional example, the device size of the intermediate potential generating circuit of FIG. 21 can be reduced, and the through currents IDC2, IDC3, IDC shown in FIG.
The total sum of DC4 and IDC5 can be reduced to less than microampere. In addition, as shown in FIG. 21, for example, the switches SW5, SW6, SW7, and SW8 are closed and operated only when the power is turned on, or only during a half cycle of the row of the clock signal CLK, and the other switches are turned off to further It is possible to reduce the through current.

(Sixth Embodiment) Next, a semiconductor integrated circuit according to a sixth embodiment of the present invention will be described with reference to FIG.

In the present embodiment, the charge supply means as described above is not separately provided, but the parasitic capacitance of the output node of the level conversion circuit is used as the charge supply means, and the charge accumulated at the output node is used by another level conversion circuit. It is to be reused.

That is, as shown in the figure, the upper level complementary level conversion circuit is the level conversion circuit shown in FIG. 6A, and the lower level complementary level conversion circuit is the level conversion circuit shown in FIG. 6B. It has the same configuration as the circuit. All the MOSFETs in the upper level conversion circuit are composed of PMOSFETs 16, 14, and 17, and all the MOSFETs in the lower level conversion circuit are NMOS.
It is composed of FETs 13, 15, and 18.

Two PMOSFEs of the upper level conversion circuit
Between T14 and 14 (point A in the figure) and between the two NMOSFETs 15 and 15 (point B in the figure) of the lower level conversion circuit are connected to the intermediate potential power supply line VM. The intermediate potential VM of the power supply line VM is set to ((Vcc-Vss) / 2).

PMOSFET 14 of the upper level conversion circuit
And the NMOSFET 15 of the lower level conversion circuit has an output node Vout1 or XVout1 (Vout2 or XVout2) that changes to the low potential side in one level conversion circuit and an output node Vout2 that changes to the high potential side in the other level conversion circuit.
Alternatively, by connecting and short-circuiting with XVout2 (Vout1 or XVout1), charge redistribution means for redistributing the charge emitted from the output node changing to the low potential side to the output node changing to the high potential side is configured. . The other configuration is similar to that of FIG. 7, and thus its description is omitted.

Next, a method of controlling the semiconductor integrated circuit of this embodiment will be described. As shown in FIG. 24, the clock signal CLK
During the half cycle period α of, the PMOSFET 17 and the NMOSFET 18 are turned on to turn the complementary output nodes Vout1, XVout1, Vout2, XVout2 of each level conversion circuit to the intermediate potential of the respective potentials at the time of the complementary output. 3/4 Vcc potential and 1 /
Precharge to 4 Vcc potential.

After that, in the remaining half cycle period β of the clock signal CLK, the output node Vout1 and XVout1 of the output node Vout1 and XVout1 of the upper level conversion circuit which is in the high impedance state due to the turning off of the PMOSFET 17 is connected to the output node on the potential drop side. , Output nodes Vout2 and XVou of the lower level conversion circuit
The PMOS on the side of the output node on the side of rising potential of t2 that is turned on by either complementary input Vin1 or XVin1
The FET 14 and either of the complementary inputs Vin2 and XVin2 are short-circuited through the NMOSFET 15 which is turned on to make the potential intermediate to the power supply line Vc, and the remaining output node Vout1 of the level conversion circuit at the upper stage or XVout1 is connected to the high potential power supply line Vcc, and the remaining output node Vout2 or XVout2 of the lower level conversion circuit is connected to the low potential power supply line Vss.

As shown in FIG. 24, the complementary inputs Vin1 and XVin1 of the upper level conversion circuit stand by at the ground potential Vss level, and only one of the inputs has a low potential after the input is fixed. Vss is set to transition, while complementary inputs Vin2 and XVin of the lower level conversion circuit are set.
2 is set to stand by at the low potential Vss level, and only one of the inputs transitions to the high potential Vcc after the input is fixed. With such a setting, the high potential power supply line Vcc and The penetration current is prevented from flowing due to a short circuit with the low-potential power supply line Vss.

In the case of another configuration, for example, between the node A and the node B of FIG. 22, the node E and the power supply line Vcc, and the node F and the ground power supply Vss,
As shown in FIG. 23, it can be replaced by a configuration in which MOSFETs 50, 51 and 52 are provided so as not to turn on until any one of complementary inputs transitions to a potential lower than the threshold voltage of the input MOSFET. .

Therefore, in this embodiment, FIG.
As can be seen from the output node V of the upper level conversion circuit
Of the out1 and XVout1, the electric charge emitted from the output node on the side where the potential drops is taken as the output node Vou of the lower level conversion circuit.
Since it can be reused for the output node on the side of rising potential of t2 and XVout2, low power consumption is possible.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described with reference to FIG.

This embodiment is an expanded version of the sixth embodiment, in which two level conversion circuits in the upper stage of FIG. 22 and two level conversion circuits in the lower stage are provided, and a total of four level conversion circuits are provided. A semiconductor integrated circuit is formed by the circuit.

A first intermediate potential Vu (Vu = 3 (Vc-Vss) /) is provided between the first and second level conversion circuits.
The power line 55 of 4) has the second intermediate potential Vc (Vc = 2 (Vc-Vs) between the level conversion circuits of the second and third stages.
s) / 4) power supply line 56, and between the third and fourth level conversion circuits, the third intermediate potential VL (Vc = (V
A power line 57 of c-Vss) / 4) is arranged.

Since the other structure is the same as that of FIG. 22, the description thereof will be omitted.

In this embodiment, as shown in FIG. 26, four output line pairs having an amplitude of Vcc / 4 operate while reusing charges from each other. Therefore, of the four level conversion circuits, only the uppermost level conversion circuit connected to the most power supply side supplies the electric charge necessary for the potential fluctuation of Vcc / 8 from the external power supply line Vcc, and the remaining three. It can be seen that the level conversion circuit of 1 operates with recycled charges.

In the sixth embodiment and the seventh embodiment, the output node (output wiring) has the same parasitic capacitance, and the potentials for turning on only one of the transistors to which complementary inputs are connected are relatively low. A data transfer system that can be utilized by a circuit that can be easily possessed, for example, a memory circuit that operates with a synchronization signal, that operates with 16, 32, 64, or 128 bits before being input to, for example, a parallel-serial conversion circuit If the circuit is made into a unit of 4 bits or 8 bits and applied to a data system circuit constituting the unit, the power consumption of the memory can be reduced.

(Eighth Embodiment) FIG. 31 shows an eighth embodiment of the present invention. This figure shows, for example, the discharge circuit 9'of FIG.
And a level conversion circuit including the precharge means 11 ′, which is a semiconductor integrated circuit including a plurality of blocks showing the main configuration of the level conversion circuit. As shown in FIG. 32, each block has an input pair part IDi, XIDi and an output pair part Di, XD.
i and level setting units H and L for each output pair. F is a functional circuit, specifically, a switch composed of a transistor. For example, if attention is paid to the output D, the level of one Di of the input pair section is compared with the other XDi in a pair relationship. And if it is "High",
It has a function of connecting the output D to the level setting unit H and connecting it to the level setting unit L if it is "Low". EQ is a signal for equalizing the output line pair. The operation table of each block is shown in FIG.

Input pair IDi, XID of each block
i corresponds to the complementary inputs Vin and XVin of FIG. 25, and the output pair parts Di and XDi are complementary output nodes Vout and X of FIG.
Vout, the level setting sections H and L are the intermediate potentials VU, VC and VL in the same figure, and the functional circuit F is the MOSFET 14 and
15 respectively.

In the seventh embodiment shown in FIG. 25, a plurality of level conversion circuits are connected to the power source Vc as schematically shown in FIG.
The output line pair of the level conversion circuit is connected between c and the ground line Vss, and one of the output line pairs of the adjacent level conversion circuits is short-circuited during the first period of one cycle of the system clock, and the remaining While the configuration is such that short-circuiting the output line pair itself of each level conversion circuit is repeated in the second period, in the present embodiment, as shown in FIG. 35, between the power supply Vcc and the ground line Vss. , A plurality of groups (two in FIGS. 31 and 35) in which each block is connected in parallel are provided, and these groups and a single level conversion circuit are connected between the power supply Vcc and the ground line Vss.

According to the structure of this embodiment, by connecting a plurality of blocks in parallel, as shown in the equivalent circuit of FIG. 35, the total capacitance in which the capacitors Cd0 to Cdn of the output line pairs of each block are connected in parallel. Becomes n × Cdn. On the other hand, the total capacity of the groups not connected in parallel is 1 × Cdn. Therefore, in the configuration of FIG. 31, the potential of the output line pair of each block is determined by the capacitance ratio of the group, and the amplitude 70 of 1: n is obtained as shown in FIG. The selected blocks will operate at a small amplitude, and the individual blocks that are not connected in parallel will operate at a large amplitude.

In the third embodiment shown in FIGS. 7 and 8, it is necessary to separately provide a capacitance smaller than the output line pair in terms of layout or process, but in the present embodiment, As a method of making a small capacity, it is only necessary to increase the number of blocks connected in series, and conversely, as a method of making a large capacity, to increase the number of blocks connected in parallel. That is, it is possible to electrically control the effective capacitance to control the amplitude distribution of the output.

(Modification of Eighth Embodiment) FIGS. 37 and 3
8 shows a modification of the eighth embodiment. In the eighth embodiment, instead of arranging two groups vertically and arranging a single block between them, conversely, arranging two individual blocks vertically and arranging a group between them. It is configured. The operation in this case has the waveform shown in FIG.

(Ninth Embodiment) FIG. 39 shows a ninth embodiment of the present invention. In the figure, a plurality of blocks are connected in series, and the first, second and third down converters 1 are provided in the chip between the external power supply Vcc and the potential Vss of the ground line.
01 to 103 are arranged, and the internal power supply line 104 of the high potential Vup is provided between the first and second down converters 101 and 102.
And the second and third down converters 10
The internal power supply line 105 having the low potential Vlw is taken out between the two and 103, and the decoupling capacitors 106 and 106 having a relatively large capacitance are connected between the two internal power supply lines 104 and 105.
It is a configuration in which they are individually arranged. However, as shown in FIG. 40, while the input of the circuit has a full amplitude (Vcc-Vss), the output amplitude has a plurality of potentials between the internally generated high potential Vup and low potential Vlw. It becomes a value that is equally divided (six in this figure).

In this embodiment, the high potential Vup internally generated by using the three down converters 101 to 103 is used.
Since the stability of the low potential Vlw and the low potential Vlw is enhanced by the large-capacity decoupling capacitors 106 and 106, the bounce caused by the noise of the external power source or the ground line is greater than that when the direct potential is connected between the external power source and the ground line. Can solve the problem.

In this embodiment, the external power supply voltage is stepped down by using the three down converters 101 to 103.
Of course, the same can be applied to the case where the external power supply voltage is boosted and the voltage is used as the internal power supply voltage.

(First Modification of Ninth Embodiment) FIG. 56 shows a first modification of the ninth embodiment of the present invention. The ninth
In the embodiment, two decoupling capacitors 106 and 106 are arranged between the internal power supply line 104 having the high potential Vup and the internal power supply line 105 having the low potential Vlw, but in this modification, they are connected in series. When the external power supply line and the ground line are directly connected to a plurality of blocks, the same number of decoupling capacitors 106 ', 106' ... as the number of blocks connected in series are connected to the external power supply line and the ground line. Are connected in series and the decoupling capacitors 106 '... Are connected to the nodes A, B ... C between the blocks.

Therefore, in this embodiment, as shown in FIG. 57, even if noises of values ΔV1 and ΔV2 occur in the voltage Vcc of the external power source, this noise is divided by the decoupling capacitors 106 '... , Only the noise of a low value of ΔV 1 / n and ΔV 2 / n whose partial pressure is reduced by the number (n) of decoupling capacitors 106 ′ acts on each block, and the bounce caused by the noise of the external power supply or the ground line The problem can be better resolved.

(Second Modification of Ninth Embodiment) FIG. 58 shows a second modification of the ninth embodiment of the present invention. The ninth
In this embodiment, the decoupling capacitor 106 suppresses the influence of noise from the external power supply, but in this modification, a plurality of blocks connected in series are directly connected to the external power supply line and the ground line. The output of the block affected by the noise of the external power supply line and the ground line is not used as a signal.

That is, in the figure, the number of blocks connected in series is the required number of parallel data (for example, 8).
Output of the uppermost block to which the power supply Vcc is applied and the lowermost block connected to the ground line of the voltage Vs (0V) Is a configuration that is not used as the parallel data.

Therefore, in the present modification, as shown in FIG. 59, even if noise occurs in the power supply voltage Vcc or the ground line voltage Vss, the influence is directly received only in the uppermost block and the lowermost block. Since the influence of the noise does not appear on the output of the other blocks located in the middle, it is possible to output the parallel data which is not influenced by the noise.

(Tenth Embodiment) FIG. 41 shows the first embodiment of the present invention.
An example of 0 is shown. In the figure, the power supply Vcc and the ground wire (first
Of the plurality of level conversion circuits connected in series between the power supply of the second power supply and the power supply of the second power supply.
SB)) to the most significant bit (MSB), the most significant bit LSB that changes most frequently is assigned to the uppermost level conversion circuit whose output line is directly connected to the power supply line. It is adopted.

That is, in this embodiment, for example, the substrate bias voltage Vbs (Vbs = Vcc-Vb) of the two MOSFETs 14 and 14 constituting the charge redistribution means in FIG. 25 can be seen from FIGS. 42 and 43. 42, the output potential is located farther from the power supply Vcc, that is, the waveform 3 is larger than the waveform 1 in FIG.
Is larger, and accordingly, the operation delay time of the MOSFET 14 increases as shown in FIG. 43 (B).
The level conversion circuit forming the least significant bit LSB is directly connected to the power supply line, and the delay time of the uppermost level conversion circuit is limited to the minimum of all the level conversion circuits.

Therefore, in this embodiment, for example, when the address is incremented, the least significant bit changes the most, and the frequency of change decreases toward the upper bit, but the level conversion circuit for the least significant bit. Since the high operational stability is ensured, the operational stability of the entire circuit can be improved.

(Eleventh Embodiment) FIG. 44 shows the first embodiment of the present invention.
1 shows an example. This figure is used when connecting a memory and a graphic controller with N bit lines. For example, 512 bits of super-multi-bit are divided into 8 bits, and these are divided into one group, It is divided into 64 groups. In this case, when one data is represented by 8 digits (8 bits), the same digit group of 4 data is in the same group.

FIG. 45 shows a frequency divider used to drive the super-multibit. The frequency divider in the figure is formed by connecting a plurality of (four in the figure) D-latch circuits 107 ... Cascaded, and outputs OT-1 and OT-1 whose frequency is doubled for each stage with respect to the frequency of the input IN. Outputs OT-2, OT-3, OT-4 ... The output OT-1 of the frequency divider is used as an operation signal for a group in which the least significant bit LSB is collected in 8 bits, and the output OT-2 is used in a group in which 8 bits are arranged one bit higher than the least significant bit LSB. Is used as the operation signal for the group in which the output OT-3 ...

Therefore, in the present embodiment, the operating frequency is different for each group, and the set group of the most significant bits, which hardly changes, operates only at the frequency of 1/64 of the system clock, as shown in FIG. In addition, as the number n of groups increases, the power consumption ratio with the related art increases (n: 2), and a large reduction in power consumption is possible.

In this embodiment, the number of bits belonging to the same group is the same in each group, but the number of bits may be different.

(Twelfth Embodiment) FIG. 48 shows the first embodiment of the present invention.
2 shows an example. This figure shows the clock CL of FIG.
K is the first clock CLK1 and P-type MOSF
A P-type MOSFET 121 is separately arranged between the ET 16 and the power supply Vcc, and the MOSFET 121 is controlled by a second clock CLK2 via an inverter 122. Other configurations are
Since it is the same as FIG. 25, the same parts are denoted by the same reference numerals and the description thereof is omitted.

The second clock CLK2 is the first clock.
The frequency divider having the D-latch circuit 107 shown in FIG. 45 is used for the configuration for generating the second clock CLK2 having a frequency twice that of the clock CLK1.

Therefore, in this embodiment, FIG.
As shown in (b), the charge Q1 is not supplied from the power supply Vcc to the level conversion circuit most connected to the power supply Vcc side every cycle, but as shown in FIGS. The charge Q2 is supplied from the power supply once. The charge Q2 supplied from the power supply Vcc is shown by hatching in FIG. 49 and FIG. As a result, FIG. 49 and FIG. 50 (a)
Then, for example, in the period of t = T1, the power source is connected, and next t = T2
During the period of, the connection with the power supply Vcc is stopped, so 2
The total charge amount in a cycle is as shown in the following formula.

(Q1 + Q1)> Q2 + “0” (however, Q2 = 1.5 × Q1) As can be seen from the above equation, the power consumption can be reduced in this embodiment. Of course, as can be seen from the operation waveform, the amplitude value is small when no charge is supplied, but since it is a differential output line pair, a high margin can be secured.

(Thirteenth Embodiment) FIGS. 51 and 52 show the thirteenth embodiment of the present invention. In the semiconductor integrated circuit of FIG. 25, four level conversion circuits are arranged in series between the power supply and the ground line, but instead of this, the semiconductor integrated circuit has eight level conversion circuits arranged in series. Circuit. As described in the seventh embodiment of FIG. 25, the output of each level conversion circuit is different and has eight reference levels between the potential level of the power supply and the ground level. In FIG. 52,
Reference numeral 150 denotes a potential detection circuit (potential detection means) configured by an N-type MOSFET that receives an output line pair of a level conversion circuit that is a driver, and 151 indicates a potential detection circuit (potential detection means) configured by a P-type MOSFET. ). The N-type potential detection circuit 150 includes an input gate unit 150 as shown in FIG.
a is composed of an N-type MOSFET, and a P-type potential detection circuit 15
As shown in FIG. 54, the input gate section 151a of No. 1 is an N-type MOSFET.

In the potential detection circuit 150 composed of the N-type MOSFET, the precharge potential of the output node of the corresponding level conversion circuit is from the intermediate potential between the potential of the power source Vcc and the ground potential to the potential of the power source Vcc. Is responsible for the input level of
The input level from the intermediate potential to the ground potential is P type.
The potential detection circuit 151 composed of MOSFET is in charge. The output of the potential detecting means 150 composed of the N-type MOSFET is the source part 150d of each N-type pair transistor 150c of the CMOS flip-flop circuit 150b.
Potential detection circuit 1 composed of a P-type MOSFET connected to
The output of 51 is a CMOS type flip-flop circuit 15
The source portion 151d of each P-type pair transistor 151c of 1b is connected.

FIG. 55 shows the N-type and P-type with respect to the input potential.
2 shows the amplification delay of each potential detection circuit composed of a MOSFET of the type. In the potential detection circuit 150 composed of the N-type MOSFET, the amplification delay does not change so much from the power supply voltage Vcc to 1/2 Vcc, but when it is less than that, the delay rapidly increases. The reason for this is that the difference from the threshold voltage of the N-type MOSFET in the input section becomes small and it cannot be turned on sufficiently. On the other hand, in the potential detection circuit 151 composed of the P-type MOSFET, contrary to the above, it is sufficiently turned on between 1/2 Vcc and Vss.

Therefore, in this embodiment, the potential detection circuit is used in a range where the amplification delay is small, and the output potential (reference level) of the corresponding level conversion circuit (driver) is used.
A potential detection circuit with good sensitivity can be provided in the vicinity.

As can be seen from FIGS. 51 and 52, N
Type level conversion circuit composed of MOSFETs, Vss ~ 1 /
It is used between 2Vcc, and is used between 1 / 2Vcc and Vcc in the level conversion circuit composed of P-type MOSFET, while it is 1/2 in the potential detection circuit composed of N-type MOSFET.
It is used between Vcc and Vcc, and is used between Vss and 1/2 Vcc in a potential detection circuit configured by a P-type MOSFET, and has a complementary relationship.

[0188]

As described above, according to the level conversion circuit and the control method thereof according to the first to eighth and thirty-first to thirty-fourth aspects of the present invention, the electric charge is supplied to the electric charge supplying means such as the capacitor. Level conversion is performed by accumulating and redistributing this accumulated charge to the output node of the level conversion circuit, so the internal power supply circuit (down converter) as in the past is unnecessary, and the level is maintained without passing through current. The conversion can be performed, and wasteful power consumption can be eliminated to reduce power consumption.

Further, according to the semiconductor integrated circuit and the control method thereof of the inventions of claims 9 to 28, 44 and 45, one of the two level conversion circuits discharges the other charge. Since it is reused for changing the potential rise of the level conversion circuit, even if it is a semiconductor integrated circuit composed of many level conversion circuits, all level conversion circuits can be operated only by the consumption current for operating one level conversion circuit. Therefore, multi-bit small-amplitude data transfer can be performed with only one bit of the current consumption, and power consumption can be effectively reduced, and its practical effect is extremely large.

In particular, the semiconductor integrated circuit according to the seventeenth aspect of the invention has the effect of reducing the capacitance value of the charge storage means by half as compared with the semiconductor integrated circuit according to the fifteenth aspect of the invention.

According to the semiconductor integrated circuit of the twenty-fifth aspect of the invention, the output node changing to the low potential side is directly connected to the output node changing to the high potential side in another level conversion circuit to recharge the charges. Since the charge storage means is used, there is an effect that the charge storage means is unnecessary, and accordingly, the layout area can be reduced and the cost can be reduced.

In addition, according to the twenty-ninth and thirtieth aspects of the present invention, the effective capacitance can be electrically controlled by appropriately setting the number of series connection or parallel connection of the level conversion circuits. It is possible to easily control the distribution.

Further, according to the inventions of claims 35 to 37, since the level conversion circuit having a large degree of change of the output node with respect to time is arranged near the power supply line, the level conversion circuit is configured. By limiting the substrate bias voltage of the MOSFET to a small value, the operation delay time can be shortened, and the operational stability of the entire circuit can be improved.

Further, according to the inventions of claims 38 to 40, a plurality of level conversion circuits are provided in the same level conversion circuit having the same degree of change of output node with respect to time. And the second power source, the level conversion circuit is disposed between the first power source and the second power source, and the first power source and the second power source separately. It is possible to operate by making the operating frequency different between the level conversion circuit disposed between and, and it is possible to achieve low power consumption.

According to the forty-first aspect of the invention, in the level conversion circuit which receives the electric charge from the power source, the electric power is supplied from the power source at a cycle that is an integral multiple of the cycle of the operation clock, so that low power consumption is achieved. Is possible.

Further, according to the inventions of claims 42 and 43, the amplification delay of the potential detection circuit composed of the N-type MOSFET and the potential detection circuit composed of the P-type MOSFET is small. Since it is used within the range, the output potential (reference level) of the level conversion circuit can be detected with high sensitivity.

In addition, in the inventions of claims 46 to 48, a decoupling capacitor having a large capacity, which is arranged between the high-potential power line and the low-potential power line,
Since the influence of noise generated on the power supply line is limited to a small amount, it is possible to improve the operational stability of the semiconductor integrated circuit.

Further, according to the inventions of claims 49 and 50, even if noise occurs in the power supply voltage or the ground line voltage, the output of the level conversion circuit affected by the noise is not used. Therefore, it is possible to satisfactorily output the outputs of the plurality of level conversion circuits that are not affected by the data as parallel data.

[Brief description of drawings]

FIG. 1 is a diagram showing a level conversion circuit of a first embodiment.

FIG. 2 is an explanatory diagram of an operation of the level conversion circuit according to the first embodiment.

FIG. 3 is a diagram showing a level conversion circuit according to a second embodiment.

FIG. 4 is a diagram showing a modification of the level conversion circuit of the second embodiment.

FIG. 5 is an explanatory diagram of an operation of the level conversion circuit according to the second embodiment.

FIG. 6 is a diagram showing another modification of the level conversion circuit of the second embodiment.

FIG. 7 is a diagram showing a semiconductor integrated circuit according to a third embodiment.

FIG. 8 is an explanatory diagram of an operation of the semiconductor integrated circuit of the third embodiment.

FIG. 9 is a diagram showing another modification in which the capacitors of the semiconductor integrated circuit of the third embodiment are shared.

FIG. 10 is a diagram showing a semiconductor integrated circuit according to a fourth embodiment.

FIG. 11 is a diagram showing control of switches of a semiconductor integrated circuit according to a fourth embodiment.

FIG. 12 is an explanatory diagram of the operation of the semiconductor integrated circuit of the fourth embodiment.

FIG. 13 is a diagram showing a modification of the semiconductor integrated circuit of the fourth embodiment.

FIG. 14 is a diagram showing control of switches in a modification of the semiconductor integrated circuit of the fourth embodiment.

FIG. 15 is an explanatory diagram of an operation of a modified example of the semiconductor integrated circuit of the fourth embodiment.

FIG. 16 is a diagram showing a semiconductor integrated circuit according to a fifth embodiment.

FIG. 17 is a diagram showing a circuit added to the semiconductor integrated circuit of the fifth embodiment.

FIG. 18 is an explanatory diagram of the operation of the semiconductor integrated circuit of the fifth embodiment.

FIG. 19 is a diagram showing an equivalent circuit of a semiconductor integrated circuit according to a fifth embodiment.

FIG. 20 is a diagram showing the effect of the fifth embodiment.

FIG. 21 is a configuration diagram of an internal power supply circuit according to a fifth embodiment.

FIG. 22 is a diagram showing a semiconductor integrated circuit according to a sixth embodiment.

FIG. 23 is a diagram showing a circuit added to the semiconductor integrated circuit of the sixth embodiment.

FIG. 24 is an explanatory diagram of the operation of the semiconductor integrated circuit of the sixth embodiment.

FIG. 25 is a diagram showing a semiconductor integrated circuit according to a seventh embodiment.

FIG. 26 is an explanatory diagram of the operation of the semiconductor integrated circuit of the seventh embodiment.

FIG. 27 is a diagram for explaining the configuration and operation of the level conversion circuit of the first conventional example.

FIG. 28 is a configuration diagram of a conventional internal power supply circuit.

FIG. 29 is a diagram for explaining the configuration and operation of the level conversion circuit of the second conventional example.

FIG. 30 is a diagram showing an equivalent circuit of a level conversion circuit of a second conventional example.

FIG. 31 is a circuit diagram showing an eighth embodiment.

FIG. 32 is a block diagram of a main part of a level conversion circuit.

FIG. 33 is an operation diagram of the level conversion circuit of FIG. 32.

FIG. 34 is an explanatory diagram of a case where level conversion circuits are connected in series.

35 is a diagram showing an equivalent circuit of the circuit in FIG. 31. FIG.

FIG. 36 is a diagram showing operation waveforms of the eighth embodiment and its modification.

FIG. 37 is a circuit diagram showing a modification of the eighth embodiment.

FIG. 38 is a circuit diagram showing an equivalent circuit of a circuit of a modified example of the eighth embodiment.

FIG. 39 is a circuit diagram showing a ninth embodiment.

FIG. 40 is a diagram showing operating waveforms of the circuit of the ninth embodiment.

FIG. 41 is an explanatory diagram of a circuit according to the tenth embodiment.

FIG. 42 is an explanatory diagram of the operation of the circuit of the tenth embodiment.

FIG. 43 is a diagram for explaining characteristics of operation delay time of MOSFET.

FIG. 44 is a diagram showing a circuit of the eleventh embodiment.

FIG. 45 is a diagram showing a configuration of a frequency divider.

FIG. 46 is a diagram showing operating frequencies of respective groups in the eleventh embodiment.

FIG. 47 is a diagram showing effects of the eleventh embodiment.

FIG. 48 is a diagram showing a circuit of the twelfth embodiment.

FIG. 49 is an explanatory diagram of the operation of the twelfth embodiment.

FIG. 50 is a comparison diagram between the operation of the twelfth embodiment and the operation of the seventh embodiment.

FIG. 51 is a diagram showing a main part of a circuit of the thirteenth embodiment.

FIG. 52 is a diagram showing an overall structure of a circuit of a thirteenth embodiment.

FIG. 53 is a diagram showing an internal configuration of a potential detection circuit configured by an N-type MOSFET.

FIG. 54 is a diagram showing an internal configuration of a potential detection circuit configured by a P-type MOSFET.

FIG. 55 is a diagram showing operation delay characteristics of an N-type MOSFET and a P-type MOSFET.

FIG. 56 is a diagram showing an overall configuration of a circuit of a first modification of the ninth embodiment.

FIG. 57 is an explanatory diagram of the operation of the first modification of the ninth embodiment.

FIG. 58 is a diagram showing an overall configuration of a circuit of a second modification of the ninth embodiment.

FIG. 59 is an explanatory diagram of the operation of the second modification of the ninth embodiment.

[Explanation of symbols]

1 Capacitor (Charge Supply Means) 2,3 Complementary Clock Signals 4,7,13,16 Input Gate 9 Discharge Means 11 Precharge Circuits 21,27 Complementary Inputs 5,6 Connect Capacitors to Outputs
MOSFETs 70, 71 MOSFETs 17 and 18 for charging and discharging capacitors Equalize transistors 106, 106 'Decoupling capacitors 107 D-latch circuit 150 Potential detection circuit composed of N-type MOSFET 151 Potential detection circuit composed of P-type MOSFET

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/10 7735-4M G11C 11/34 354 A

Claims (50)

[Claims] 1. A signal that changes to two different values is input and it operates in synchronization with a clock signal, and the amplitude value of the input signal is converted into another amplitude value and output from a single output node. An inverter type level conversion circuit, comprising: first charge supply means precharged to a first potential;
A second charge supply unit that is precharged to a second potential different from the first potential and one of the two charge supply units are selected according to the input signal, and the selected charge supply unit is selected. And a discharge means for discharging the electric charge accumulated in the output node to the output node. 2. A signal that changes to two different values is input and it operates in synchronization with a clock signal, and the amplitude value of the input signal is converted into another amplitude value and output from two output nodes. Complementary level conversion circuit, first charge supplying means precharged to a first potential, and second charge supplying means precharged to a second potential different from the first potential. And the first signal according to the input signal
Discharging means for discharging the electric charge accumulated in the electric charge supplying means to one of the two output nodes and discharging the electric charge stored in the second electric charge supplying means to the other output node. A level conversion circuit characterized by that. 3. A precharge circuit for precharging an output node to a third potential between a first potential of the first charge supply means and a second potential of the second charge supply means. The level conversion circuit according to claim 1 or 2, wherein: 4. The level conversion circuit according to claim 3, wherein in the complementary level conversion circuit, the precharge circuit short-circuits two output nodes. 5. A precharge circuit precharges an output node to a third potential during a first period within one cycle of the clock signal and a first period during a second period within the one cycle of the clock signal. The charge supply unit and the second charge supply unit are precharged to the first potential and the second potential, respectively, and the third period after the first period and the second period within one cycle of the clock signal. 5. The method of controlling a level conversion circuit according to claim 3, wherein the electric charge precharged in the electric charge supplying means by the discharging means is discharged to the output node during the period. 6. The level conversion circuit according to claim 2, wherein the first charge supply means or the second charge supply means is constituted by a high-potential power supply line. 7. The level conversion circuit according to claim 2, wherein the first charge supply means or the second charge supply means is constituted by a low-potential power supply line. 8. The charge supplying means is composed of a capacitor, and the capacitor has a ratio of a capacitance value thereof and a parasitic capacitance value of the output node is a potential of the output node desired to be realized and a precharge potential of the output node. 2. The capacitance value is set so as to be a ratio of a potential difference between the potential of the capacitor 2 and a potential of the first potential, which is a precharge potential of the capacitor, and a potential of the output node. The level conversion circuit according to 1, 2, 3, 5, 6 or 7, or a control method thereof. 9. A level conversion circuit which receives a signal that changes to two different values and operates in synchronization with a clock signal, converts the amplitude value of the input signal into another amplitude value, and outputs the amplitude value from an output node. A plurality of level conversion circuits, and two level conversion circuits of the plurality of level conversion circuits have opposite charge transfer directions at output nodes and the same absolute value of the charge with respect to time. And a charge redistribution unit for moving charges between two level change circuits having the same charge amount change characteristic. Integrated circuit. 10. The semiconductor integrated circuit according to claim 9, wherein the plurality of level conversion circuits are complementary level conversion circuits each having two output nodes whose outputs are complementary. 11. The plurality of level conversion circuits comprises:
It comprises one level conversion circuit according to claim 7 and one level conversion circuit according to claim 7, wherein the two level conversion circuits are connected in series between a high-potential power line and a low-potential power line. 11. The semiconductor integrated circuit according to claim 10, wherein the semiconductor integrated circuit is arranged. 12. The plurality of level conversion circuits comprises:
It comprises one or a plurality of level conversion circuits described above, one level conversion circuit according to a sixth aspect, and one level conversion circuit according to a seventh aspect, wherein the plurality of level conversion circuits are high. 11. The semiconductor integrated circuit according to claim 10, wherein the semiconductor integrated circuit is arranged in series between a power line having a potential and a power line having a low potential. 13. A transistor of a level conversion circuit for outputting a higher potential from an output node as compared with a potential of an intermediate value between a potential of a high potential power line and a potential of a low potential power line is a P-type MOSFET. The transistor of the level conversion circuit configured to output a low potential from the output node is an N-type MOSFET.
11. The method according to claim 10, 11 or 1 is characterized in that
2. The semiconductor integrated circuit according to 2. 14. The charge amount change characteristic equalizing means comprises a precharge means for precharging two output nodes having substantially the same parasitic capacitance value to the same potential, a charge accumulating means for accumulating charges, and the charge accumulating means. 14. A semiconductor integrated circuit according to claim 10, 11, 12 or 13, comprising a charging means for charging the means to a potential different from the predetermined potential. 15. The semiconductor integrated circuit according to claim 14, wherein the charging means charges the charge storage means to a potential between the precharge potentials of the two level conversion circuits for redistributing charges. . 16. The charge storage means performs charge redistribution 2
16. The semiconductor integrated circuit according to claim 15, wherein the semiconductor integrated circuit is shared by one level conversion circuit. 17. The charge storage means performs charge redistribution 2
The charging means is shared by the individual level conversion circuits, and the charging means alternately charges the vicinity of the precharge potential of one level conversion circuit that performs charge redistribution and the vicinity of the precharge potential of the other level conversion circuit. 17. The semiconductor integrated circuit according to claim 16, wherein the inputs of the two level conversion circuits are set such that the signal change cycles are shifted from each other by a half cycle. 18. The charge reallocation means redistributes charge 2.
One of the two charge storage means of each level conversion circuit is
One of the level conversion circuits is connected to the output node on the side that changes to the high potential side in one level conversion circuit, and the other charge storage means is connected to the output node on the side that changes to the low potential side in the other level conversion circuit. 16. The semiconductor integrated circuit according to claim 14, wherein the semiconductor integrated circuit is connected. 19. The charge amount variation characteristic equalizing means precharges two output nodes having substantially the same parasitic capacitance value in each level conversion circuit to a predetermined potential, and the precharge potentials of the respective level conversion circuits are mutually precharged. 11. The semiconductor integrated circuit according to claim 10, wherein the potential difference is set to the same value or the ratio of the reciprocal of the parasitic capacitance value of each of the level conversion circuits. 20. The charge redistribution means, in two level conversion circuits in which precharge potentials are adjacent to each other and should perform charge redistribution, an output node in which one of the level conversion circuits changes to a lower potential side according to an input. 20. The semiconductor integrated circuit according to claim 19, wherein the other level conversion circuit short-circuits an output node that changes to a high potential according to an input. 21. In each level conversion circuit, two output nodes are precharged to the same potential in a first period within one cycle of the clock signal, and at the same time, in a second period within one cycle of the clock signal, The charge storage means of the two level conversion circuits for redistributing charges are charged to a predetermined potential between both precharge potentials of the two level conversion circuits for redistributing charges.
After that, in the third period after the first period and the second period within one cycle of the clock signal, one of the two charge accumulating means of the two level conversion circuits for redistributing the charges is One of the two level conversion circuits for redistributing charges is connected to the output node on the side that changes to the high potential side while the other charge storage unit changes to the low potential side on the other level conversion circuit. 16. The method of controlling a semiconductor integrated circuit according to claim 14, wherein the control circuit is connected to the output node on the side. 22. The potential for charging the two charge storage means in the second period within one cycle of the clock signal is a potential between both precharge potentials of the two level conversion circuits for redistributing charges. 22. The method for controlling a semiconductor integrated circuit according to claim 21, wherein. 23. The potential for charging the two charge storage means in the second period within one cycle of the clock signal has one of the two level conversion circuits for redistributing charges in one charge storage means. 22. The semiconductor integrated circuit according to claim 21, wherein the semiconductor integrated circuit has substantially the same potential as the charge potential, and the other charge storage means has substantially the same potential as the other precharge potential of the two level conversion circuits for redistributing charges. Circuit control method. 24. The first period and the second period are the same period, claim 21, 21, 22 or 23.
A method of controlling the level conversion circuit or the semiconductor integrated circuit described. 25. In each level conversion circuit, two output nodes are precharged to the same potential during a predetermined period within one cycle of the clock signal, and thereafter, a period after the predetermined period within one cycle of the clock signal. And an output node on the side that changes to the high potential side in one level conversion circuit of the two level conversion circuits for redistributing charges and an output node on the side that changes to the low potential side in the other level conversion circuit. 21. The method for controlling a semiconductor integrated circuit according to claim 19, wherein connection is made. 26. The power supply terminal is disposed between two power supply terminals, and
11. The semiconductor integrated circuit according to claim 9 or 10, further comprising a through current preventing unit that controls so that a through current does not flow between the individual power supply terminals. 27. The through current preventing means comprises a plurality of transistors, and the plurality of transistors are simultaneously turned on.
27. The semiconductor integrated circuit according to claim 26, wherein the semiconductor integrated circuit is controlled so as not to turn off. 28. The semiconductor integrated circuit according to claim 27, wherein the plurality of transistors are controlled by an independent control signal different from the input of the level conversion circuit. 29. A plurality of level conversion circuits are provided, output nodes respectively provided in some of the plurality of level conversion circuits are connected in parallel with each other, and the plurality of output nodes connected in parallel are the first output nodes. The first charge supplying means or the second charge supplying means is connected to the first charge supplying means or the second charge supplying means.
2. A level conversion circuit according to 2, 3, 4, 5, 6, 7 or 8, or a control method for a level conversion circuit. 30. A plurality of level conversion circuits are provided, output nodes respectively provided in some of the plurality of level conversion circuits are connected in series with each other, and each of the plurality of output nodes connected in series is provided. 9. The level conversion circuit or level conversion circuit according to claim 1, 2, 3, 4, 5, 6, 7 or 8, characterized in that is connected to the first charge supply means or the second charge supply means. Control method. 31. The level conversion circuit according to claim 6, wherein the high-potential power supply line is a high-potential external power supply line. 32. The level conversion circuit according to claim 6, wherein the high-potential power supply line is a high-potential internal power supply line. 33. The level conversion circuit according to claim 7, wherein the low-potential power supply line is a low-potential external power supply line. 34. The level conversion circuit according to claim 7, wherein the low-potential power supply line is a low-potential internal power supply line. 35. The plurality of level conversion circuits are arranged in series between a first power supply and a second power supply having a potential different from the potential of the first power supply, and the plurality of level conversion circuits are provided. The level conversion circuit, of the conversion circuits, whose degree of change of the output node with respect to time is large is arranged at a position closer to the first power supply or the second power supply than the remaining level conversion circuits. A semiconductor integrated circuit or a method for controlling a semiconductor integrated circuit according to 19, 20, or 25. 36. A semiconductor integrated circuit or a method for controlling a semiconductor integrated circuit according to claim 35, wherein the level conversion circuit composed of a P-type MOSFET is arranged on a side closer to a power supply having a higher potential. 37. The semiconductor integrated circuit or the method of controlling a semiconductor integrated circuit according to claim 35, wherein the level conversion circuit composed of the N-type MOSFET is arranged on the side closer to the power source having a lower potential. 38. A plurality of level conversion circuits, of which a plurality of level conversion circuits having the same degree of change of output node with respect to time are the same, the first power supply and the first power supply.
10. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit is arranged in series with a second power source having a potential different from the potential of the power source. 39. The plurality of level converting circuits are grouped by level converting circuits having the same degree of change of output nodes with respect to time, and the level converting circuits belonging to each group for each group have a first power source and a first power source. 39. The semiconductor integrated circuit according to claim 38, wherein the semiconductor integrated circuit is arranged in series with two power sources. 40. The cycle of the operating clock is different between the group of level conversion circuits in which the degree of change of the output node with respect to time is large and the group of level conversion circuits in which the degree of change of the output node with respect to time is small. 40. The level conversion circuit according to claim 39. 41. The charge amount change characteristic equalizing means controls the connection with the power supply at a cycle that is an integral multiple of a cycle of operation clocks of the plurality of level conversion circuits.
A semiconductor integrated circuit or a method for controlling a semiconductor integrated circuit according to 9, 20 or 25. 42. At the output nodes of the plurality of level conversion circuits arranged in series between the first power supply and the second power supply, potential detecting means for detecting the potentials of the corresponding output nodes are provided. Of the multiple potential detection means connected in the previous period,
The potential detecting means corresponding to the output node of the level conversion circuit on the side where the precharge potential of the output node of the level conversion circuit is higher than the intermediate potential between the first power supply and the second power supply is an N-type MOSFET. 42. The semiconductor integrated circuit according to claim 9, wherein the potential detecting means configured to correspond to the output node of the level conversion circuit on the side lower than the intermediate potential is a P-type MOSFET. 43. An output of the potential detecting means composed of an N-type MOSFET is connected to each source part of an N-type pair transistor of a CMOS flip-flop circuit and composed of a P-type MOSFET. The output of the detection circuit is CMOS
5. Each of the P-type pair transistors of the P-type flip-flop circuit is connected to the respective source units.
2. The semiconductor integrated circuit according to 2. 44. The outputs from the output nodes of the plurality of level conversion circuits are transferred to the outside as two or more parallel data, and the two or more parallel data are previously stored in the first power supply and the second power supply. 10. The method of controlling a semiconductor integrated circuit according to claim 9, wherein the voltage is transferred to the outside by using each voltage range obtained by dividing a range of a finite potential difference from the potential of the power supply of 1. 45. The method of controlling a semiconductor integrated circuit according to claim 44, wherein the number of divisions of the finite potential difference is the same as the number of parallel data transfers. 46. The plurality of level conversion circuits are arranged in series between a first power supply and a second power supply having a potential different from the potential of the first power supply, and the first power supply. 10. The semiconductor integrated circuit according to claim 9, wherein a decoupling capacitor having a relatively large capacity is connected between the second power supply and the second power supply. 47. The first power source and the second power source are internal power sources, and a decoupling capacitor is connected between the first internal power source and the second internal power source. 46. The semiconductor integrated circuit according to 46. 48. The first power supply and the second power supply are external power supplies, and a number of decoupling capacitors equal to the number of level conversion circuits is provided between the first external power supply and the second external power supply. 47. The semiconductor integrated circuit according to claim 46, wherein each of the decoupling capacitors is connected to a node between two corresponding level conversion circuits. 49. A plurality of level conversion circuits are arranged in series between a first power supply and a second power supply having a potential different from the potential of the first power supply, and the plurality of level conversion circuits are provided. 10. The semiconductor integrated circuit according to claim 9, wherein, of the conversion circuits, the output of the level conversion circuit connected to the first power supply or the level conversion circuit connected to the second power supply is not used. 50. The number of the plurality of level conversion circuits is the first
50. The semiconductor integrated circuit according to claim 49, wherein the number is the same as the number of parallel data required, except for the level conversion circuit connected to the power supply of or the level conversion circuit connected to the second power supply. .