JPH08297983A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To obtain a semiconductor memory in which the conduction of a memory transistor and the conduction of a comparison transistor are sensed at the time of reading out the memory without waiting the discharge of a digit line and the reading rate is increased correspondingly. CONSTITUTION: Each memory cell transistor MCT can be set with one of four threshold values Vr0 , Vr1 , Vr2 , Vr3 and each word line W0 of a comparison transistor can be set with one of three threshold values H00 , H01 , H02 . A sense circuit 1 comprises P channel transistors 11-18 wherein the transistor 12, 13, 14 has a channel width two times as wide as that of the transistor 11. When a data is stored under that state, a memory transistor MCT00 is selected by X and Y addresses and the word line is driven to an intermediate level V1 between the threshold values Vr0 , Vr1 . More specifically, only a timing signal T0 goes L through a timing signal generation circuit to turn a transistor 15 on and the transistors 12, 11 form a current mirror circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and its reading method, and more particularly to a one-transistor type multi-valued mask ROM.

[0002]

2. Description of the Related Art Generally, in a mask ROM, each memory cell is composed of one MOS type memory transistor, and data "1" and "0" are used to turn on / off a selected memory transistor.
(Or “0”, “1”). However, in such a configuration, one bit of data corresponds to one memory cell.

Therefore, as a method of further increasing the storage capacity, a method has been proposed in which a plurality of threshold values are set in a memory transistor and one memory cell stores a plurality of bits of data. For example, by allowing each memory transistor to set any of four threshold values, one memory cell equivalently stores 2-bit data.

However, what is important here is how to detect, that is, sense, which one of a plurality of thresholds each memory transistor is set to.

One of the methods is disclosed in Japanese Patent Laid-Open No. 58-46798.
No. 6,086,045. Such a method will be described with reference to FIG.

Each of Q _{1 to} Q ₄ is a MOS transistor as a memory cell. The threshold voltage of each memory cell differs depending on the information to be stored. For example, the threshold voltage of the memory cell Q ₁ is V _th1 , and the memory cell Q is
The threshold voltage of ₂ is V _th2 , the threshold of the memory cell Q is V _th3 ,
The threshold voltage of the memory cell Q ₄ is set to V _th4 , and the respective relationships are set such that V _th1 > V _th2 > V _th3 > V _th4 . These thresholds are M
This is achieved by changing the amount of ion implantation into the channel region of the OS transistor, the thickness of the gate oxide film, and the like.

In reading information, that is, in a sensing operation, first, the P terminals of the word line precharge circuit 21 and the bit line precharge circuit 22 are set to a high level to precharge all the word lines and bit lines. Next, in order to select the memory cell Q ₁ , the switch transistor T
The gate of R3 is set to high level, and the electric charge accumulated in the word line W ₁ is discharged to zero potential. Therefore, the gate-source voltage of the memory cells Q ₁ and Q ₂ becomes higher than the threshold voltage and both are turned on. The charges accumulated on the bit lines B _L1 and B _L2 are thus released and the potential starts to drop. However, since the gates of the memory cells are all connected to the bit line, the potential of the bit line B _L1 does not _drop below the threshold V _th1 of the memory cell Q ₁ , and the bit line B _L1
The potential of _L2 does not decrease to below the threshold of the memory cell Q _2.
When the switch transistor TR1 is turned on to select the bit line B _L1 , the charge accumulated in the input wiring circuit of the A / D converter 23 is switched to the switch transistor T1.
R1, the memory cells Q _1, the word line W _1, to discharge through the switching transistor TR3, the input terminal of the A / D converter 23 becomes V _th1. Then, from the output, the threshold value V
A digital value corresponding to _th1 is output, this signal is stored in the output buffer circuit 24, and then output as information of the memory cell Q ₁ .

When this one cycle time ends,
After each switch transistor is turned off, precharge is performed and a read operation similar to the above is performed to take out digital information corresponding to the threshold value stored in each memory cell.

As another sensing method, a method of driving the potential of a selected word line in a stepwise manner is disclosed in Japanese Patent Laid-Open No. 56-153.
It is disclosed in Japanese Patent No. 582.

The sensing method of this memory cell will be described with reference to FIG. Note that FIG. 19A is a basic circuit diagram for one memory transistor, and FIG. 19B is a timing chart diagram of the circuit.

Reference numeral 201 is a P-channel MISFET, and 203 is an N-channel MISFET as a memory transistor. The threshold of the MISFET 203 is set to one of a plurality of thresholds.

In sensing, first, the word line 206
Is set to a ground level at which the memory cell transistor does not conduct, and the gate signal φP is set to a low potential.
T201 is made conductive, and the bit line 208 is connected to the power supply voltage V _DD.
Charge to level and precharge. Next, the gate signal φP is set to a high potential to make the MISFET 201 non-conductive.

Next, the voltage level of the word line 206 is set to V _G1.
Change to. The threshold of the MISFET 203 is this voltage V
When it is lower than _G1, this transistor becomes conductive, the precharge charge of the bit line 208 is discharged to the ground through this MISFET, and the bit line 208 becomes low level (hereinafter referred to as L). In this state, the first clock pulse of the clock signal φ to the 2-bit shift register 210 changes the logical level of the bit line to the shift register 2
Read in 10. Next, the level of word line 206 is changed to V _G2 . In the above example, MISFET 203 remains conductive and bit line 208 is L.

In this state, the second pulse of the clock signal φ shown in FIG. 18B is generated, and the logic level of the bit line is read into the shift registers 210 and 211. As a result, the 2-bit register shift register 210 holds (L, L) data. That is, the memory cell transistor stores 2 bits of (0,0).

[0015]

However, as shown in FIG.
In the sense method of _{No. 2} , the voltage levels of the bit lines B _L1 and B _L2 are converted into digital values by the A / D converter. However, an A / D converter with high accuracy is used to detect a small change in the voltage value. Will be needed. Such an A / D converter has a complicated structure, a large chip size, and a long conversion time.

On the other hand, in the sensing method of FIG. 19, it is necessary to discharge the voltage of the bit line 208 in which the memory cell itself is precharged below the threshold value of the shift register, which causes a problem that the reading speed is slow. is there.

Therefore, a main object of the present invention is to provide a semiconductor memory device which can sense a multi-valued memory cell transistor at high speed.

[0018]

A read-only memory device according to the present invention comprises at least one word line and at least one memory transistor having a gate connected to this word line, and is selected from a plurality of threshold values. A memory transistor having a selected threshold value and a plurality of comparison transistors each having a gate connected to a word line and each having a threshold value different from each other and having a threshold value selected from a plurality of threshold values; Voltage driving means for respectively driving a plurality of voltages between the gate and the source of the comparison transistor, and a current flowing through the memory transistor each time the memory transistor and the comparison transistor are connected and driven by each of the plurality of voltages. Based on the difference between the Wherein the re-transistor and a sense circuit for outputting multi-bit data to be stored.

Further, in another read-only memory device of the present invention, the word line is not driven stepwise, but the virtual ground line made of metal wiring is driven stepwise.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION In order to clarify the above and other objects, features and effects of the present invention, an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a memory according to the first embodiment. This memory has N word lines W ₀ to
It has a cell array 500 having W _N , M bit lines B _{0 to} B _M , and memory transistors MCT _{00 to} MCT _NM arranged at intersections of word and bit lines, respectively. Further, according to the present invention, the comparison transistor array 6
00 are provided, and the array 600 has N rows and J columns of comparison transistors H _{00 to} H _NJ . J is the number of thresholds that each memory transistor can be set to, minus one. For example, if four thresholds can be set for each memory transistor MCT, J will be 3. One of the word lines W is selected by the X decoder / driver 3 according to the X address. The bit line B is selected by the Y decoder 5 and the Y selector 4 according to the Y address.

In the comparison transistor array 600, the comparison transistors arranged in the same row have the gates connected to the corresponding word lines, and the comparison transistors arranged in the same column have the drains of the sense lines SN _{0 to} SN _J. Connected to the corresponding one. Each sense line SN is connected to the sense circuit 1. The bit line selected by the Y selector is also connected to the sense circuit 1. The sense circuit 1 generates multi-bit information stored in the selected memory cell based on the magnitude of the current flowing through the bit line and the sense line, and outputs it to the output circuit 2. The output circuit 2 is formed of a tristate buffer or the like, and drives the output terminal 7 based on the data from the sense circuit 1. Although there are a plurality of output terminals 7, only one is shown in the drawing.

The sense circuit 1 according to this embodiment is shown in FIG.
Is shown in. In the figure, one word line W ₀ , one memory transistor MCT ₀₀ and the selection transistor MB ₀ in the Y selector 4 are also shown. Further, in the present embodiment, one of the four threshold values can be set in each memory cell transistor MCT, so that the comparison transistor of the word line W ₀ is H ₀₀ , H ₀₁ , H ₀₂ as shown in the drawing. Three are provided. The sense circuit 1 includes P-channel transistors 11, 12, 13, 1
4, 15, 16, 17, 18, power supply terminal V _CC , three block circuits R ₁ , R ₂ , R ₃ and two NOR circuits 1
It consists of 9, 20. Each of the block circuits R _{1 to} R ₃ is configured as shown in FIG. The channel widths of the transistors 12, 13 and 14 are set to twice the channel width W of the transistor 11 as shown. The channel length of the transistors 12, 13, 14 may be half that of the transistor 11.

Next, the operation of this memory will be described with reference to the timing chart of FIG. It is assumed that the memory transistor MCT ₀₀ is selected by the X and Y addresses, and the threshold value of this transistor is four threshold values V _T0 and V _T0 .
It is assumed that the second threshold value V _T1 of _{T 1} , V _T2 , and V _T3 is set. In addition, the comparison transistors H ₀₀ , H ₀₁ , H
The thresholds of ₀₂ are V _T0 , V _T1 , and V _T2 , respectively. In the following description, a logical high level is abbreviated as H and a logical low level is abbreviated as L.

The word line W ₀ is first driven to an intermediate level V ₁ between the thresholds V _T0 and V _T1 . At this time, the timing signal generating circuit (not shown) sets only the timing signal T ₀ to L and turns on the transistor 15. As a result, the transistors 12 and 11 form a current mirror circuit having the input side transistor and the output side transistor, respectively. Since the cell transistor MCT ₀₀ has the threshold value V _T1 , it remains off even if the word line W _{0 has} the V ₁ level.
On the other hand, the comparison transistor _H00 becomes conductive. This causes the current I ₀ to flow. As described above, the transistors 12 and 11 form a current mirror circuit. However, since the channel width of the transistor 11 is half the channel width of the transistor 12, a current of half the current I ₀ is applied to the transistor 11. However, the memory cell transistor MC
Since T ₀₀ is in the off state, no current flows through the bit line B ₀ . As a result, the level at the S point is V as shown in FIG.
_It is pulled up to _CC, and the output of the inverter 18 outputs L level. As a result, (inversion S, T ₀ , Q _K-1 , Q _K-2 ) = (L, L, L, L) is input to the latch block R ₀ and Q ₀ = L is output.

The word line W ₀ is then driven to the intermediate level V ₂ between the thresholds V _T1 and V _T2 . Also, the timing signal T
₀ , T ₁ , and T ₂ are (H, L, H), respectively. The memory transistor MCT ₀₀ thus becomes conductive and tries to carry the current I ₁ . On the other hand, in the comparison transistor array, the comparison transistor H ₀₁ becomes conductive and the current I ₁ flows, and the same current also flows in the P-type transistor 13. The P-type transistors 13 and 11 now form a current mirror, but since the gate width of the transistor 11 is half that of the transistor 11, the transistor 11 has the ability to pass only half the current of I ₁ . As a result, the point S becomes L level and the inverted S becomes H level. At this time, the timing signal T ₀
˜T ₂ , the output Q ₀ of the latch block R ₀ remains L, while the latch block R ₁ has (inversion S, T
₁ , Q _K-1 , Q _K-2 ) = (H, L, L, L) is input and the output Q ₁ thereof becomes H. The latch block R ₂ has (inversion S, T ₂ , Q _K-1 , Q _K-2 ) = (H, H, L,
H) is input, its output Q ₂ becomes L.

The word line W ₀ is further driven to an intermediate level V ₃ between the thresholds V _T2 and V _T3, and the timing signals T ₀ ,
T ₁ and T ₂ are (H, H, L), respectively. In this case, in the same way as when the level of the word line W ₀ is V ₂ ,
The output node S is L and the inversion S is H. There is no change in the output of each of the latch blocks R ₀ and R ₁ , and Q _{2 of the} latch block R ₂ remains L.

After this, the voltage level of the word line W ₀ is V ₃
As it is, the timing signals T ₀ , T ₁ , and T ₂ all become H. Therefore, the transistors 12 to 14 are separated from the transistor 11, but the gate of the transistor 11 holds the previous bias potential. Therefore, the output node S remains L and the inversion S remains H level. As a result, the outputs of the latch blocks R _{0 to} R ₂ do not change.

Thus, the NOR gates 19 and 20 output (1, 0) as the 2-bit data stored in the cell transistor MCT ₀₀ .

After that, the word line W ₀ is reset to the ground level, and the data sensing and reading operations are completed.

When the threshold of the memory transistor MCT is V _T0 or V _T2 , H appears at the output node S when the drive level of the word line W is W ₁ or W ₃ , respectively. When the threshold value of the memory transistor MCT is V _T3 , the output node S remains L regardless of the drive level of the word line. These states are the latch block R
_The 2-bit output data corresponding to the set threshold value is fetched by _{0 to} R ₂ . FIG. 4 shows the relationship between the threshold value of the memory transistor and the word line drive voltage, the on / off state of each transistor, and the value of the output data. That is, the thresholds of the memory transistors are V _T0 , V _T1 ,
The output data when V _T2 and V _T3 are (0, 0),
(1,0), (0,1) and (1,1).

As described above, since the current sensing method using the current mirror circuit is adopted in the sensing method, the speed of changing the output node S to H or L is remarkably fast. Moreover, its configuration is simplified.

FIG. 5 shows a circuit diagram of a memory according to the second embodiment of the present invention. The same components as those in FIG. 2 are designated by the same reference numerals. In this embodiment, the transistors 15 to 17 for receiving the timing signals T _{0 to} T ₂ are provided between the comparison transistors H _{00 to} H ₀₂ and the input side transistors 12 to 14 of the current mirror circuit, respectively. Since the operation of this circuit is substantially the same as the operation shown in FIGS. 2 and 3, the description thereof will be omitted.

FIG. 6 is a circuit diagram of a memory according to the third embodiment of the present invention. This memory is used in the first embodiment and the second embodiment.
Similar to the embodiment described above, the method is one in which the level of the word line is raised and read out, but in the present embodiment, the transistor 30 is used.
As shown in the current mirror circuit by 33 to 33, the cell side transistor is the input side and the comparison transistor side is the output side. Further, the sense line is connected to the latch block circuit R as each output node. The channel width of the transistors 31, 32 and 33 is twice the channel width of the transistor 30.

The threshold of the memory transistor MCT ₀₀ is V ₁
The operation will be described assuming that it is set to. The word line W ₀ is driven to the V ₁ level and the timing signals T ₀ , T
_{When 1} and T ₂ respectively become (L, H, H), the comparison transistor H ₀₀ is conductive, and the memory transistor MCT ₀₀ and the comparison transistors H ₀₁ and H ₀₂ are non-conductive. Since the memory transistor MCT ₀₀ is off, the transistors 30, 31, 32 and 33 remain off. Therefore, the level of output node S ₅ becomes L level. The latch block R ₀ has (S, T ₀ , Q _K-1 , Q _K-2 ) =
(L, L, L, L) is input and Q ₀ = L is output.

When the word line W ₀ is driven to the V ₂ level and the signals T ₀ , T ₁ , and T ₂ become (H, L, H), the memory transistor MCT ₀₀ becomes conductive, and the comparison transistor H ₀₀ and H ₀₁ also conduct. The conduction of the memory transistor MCT ₀₀ causes a current I to flow through the transistor 30.
₀ flows. From the above-described setting of the channel width in the transistors 30 to 32, I ₀ is set in the transistors 31 and 32.
Current that is twice as high as that of On the other hand, only the current I ₀ flows through the comparison transistors H ₀₀ and H ₀₁ . Therefore, the levels of the output nodes S ₅ and S ₆ both rise to the H level and are transmitted to the latch block circuits R ₀ and R ₁ . The latch block R ₀ includes (S, T ₀ , Q
Latch block R holds the previous output state (Q ₀ = L) because it receives _K-1 , Q _K-2 ) = (H, H, L, L).
₁ has (S, T ₁ , Q _K-1 , Q _K-2 ) = (H, L, L,
Since L) is input, Q ₁ = H is output. Also,
For R ₂ , (S, T ₁ , Q _K-1 , Q _K-2 ) = (indefinite, H,
Since L, H) are input, Q ₂ = L is output.

The word line W ₀ is further driven to the voltage level V ₃ and the signals T ₀ , T ₁ and T ₂ are (H,
H, L), all of the memory transistor MCT ₀₀ and the comparison transistors H ₀₀ , H ₀₁ , H ₀₂ become conductive. As a result, the levels of the output nodes S ₅ , S ₆ , and S ₇ are all H level. As a result, the latch block R ₀
Is (S, T ₀ , Q _K-1 , Q _K-2 ) = (H, H, L,
L) is input and Q ₀ = L in the period C, so Q ₀
= Hold L On the other hand, R ₁ has (S, T ₁ , Q _K-1 ,
Q _K-2 ) = (H, H, L, L) is input, and Q in period C
₁ = outputs the Q ₁ = H because it is H. Also, R ₂
Is (S, T ₁ , Q _K-1 , Q _K-2 ) = (H, L, L,
H) is input and Q ₂ = H is output.

When the signals T ₀ , T ₁ and T ₂ are (H, H, H) while the word line W ₀ is at V ₃ level,
The transistors are all in the conducting state, thus retaining their previous state.

Thus, also in this embodiment, D ₁ , D are stored as the store data of the memory cell transistor MCT _00.
2 = 1,0 is obtained. Moreover, in the present embodiment, the threshold V _{T0 of} the memory transistor and the comparison transistor,
V _T1 , V _T2 , V _T3 and word line W ₀ levels V ₁ , V ₂ ,
The relationship with V ₃ is V _T0 <V ₁ <V _T1 <V ₂ <V _T2 <V ₃
It is not necessary to limit to the relationship of <V _T3 , and as shown in FIG. 7, the drive levels V ₁ , V ₂ , V ₃ of the word line W ₀ can be set widely. That is, this memory circuit forms a current mirror circuit with a memory transistor and a comparison transistor, and includes a current mirror transistor provided in a sense line of a current mirror transistor and a comparison transistor provided in a bit line of the memory transistor. Since the channel ratios are set differently, the conduction state of the memory transistor is configured to sense the difference between the conduction currents of the comparison transistor and the memory transistor and output a high level or a low level. Therefore,
Even when the potential of the word line becomes high V ₁ than V _T0, V _T1, the current flowing through the memory transistor (e.g., 1
Since the current (μA) is much smaller than the current (eg, 10 μA) flowing in the comparison transistor, the sense circuit can sufficiently output a high level.

More specifically, in the present memory in which the differences between the thresholds are equal, V _T3 −V _T2 = V _T2 −V _T1 = V _T1 −V _T0 holds.

Assuming that the current value flowing through the comparison transistor whose threshold value is V _T0 is I ₀ and the current value flowing through the memory transistor whose threshold value is V _T1 is I ₁ , I ₀ = K (V ₁ −V _T0 ) I ₁ = K (V ₁ −V _T1 ) (when V ₁ > V _T1 ) I ₁ = 0 (when V ₁ ≦ V _T1 ). Note that K is an arbitrary constant. So, let's say V
_{Even if} the value of ₁ is set to (V _T2 + V _T1 ) / 2, from the above equation, I ₁ = I ₀ * (V ₁ −V _T1 ) / (V ₁ −V _T0 ) = I ₀ *
The current I ₁ flowing through the memory transistor for the reason of 1/3 or more
Flows only 1/3 of the current I ₀ of the comparison transistor. Therefore, the potential of V ₁ is (V _T2 + V _T1 ) /
Even if the number becomes 2, the inverter 18 or the block circuit may be set so that the high level is recognized even with the ratio of 1: 3. Therefore, there is an effect that the design and manufacturing of the present memory become easy.

FIG. 8 shows a part of the X decoder / driver that can be used in the above-described embodiments. This circuit is a NOA circuit 8 that outputs a high level depending on the combination of addresses.
00 and two-stage inverters 801 and 802. Two
The operating voltage of the inverter 802 of the stage is timing signals T ₀ , T ₁ , T ₂ and transistors 803 to 805.
Is switched to one of the voltages V ₁ , V ₂ and V ₃ .
Thus, the level of the selected word line W is driven stepwise in synchronization with the timing signal.

Each drive level can be generated by the configuration of FIG. 9 as an example. This circuit is a pMOS transistor 90 having a drain connected to a power supply voltage and a gate grounded.
1, the source is grounded, and the gate and drain are connected to the source of the transistor 901, respectively.
00 nMOS transistors 902 connected in parallel
The output voltage is extracted from the source of the transistor 901. The threshold value of the nMOS transistor is V
_The cell transistor is made of _Ti, and V _{i, which} is substantially equal to V _Ti , is output from the output terminal. By providing a plurality of nMOS transistors, for example, if the current driving capability of the nMOS transistors is 1 μA, the number of 50 nMOS transistors is 50 μA, and a drive current with high driving capability can be obtained. Therefore, it has an effect that the delay becomes very small.

In each of the above embodiments, the word line is driven from the low potential to the high potential, but a method of driving the word line from the high potential to the low potential to read the information of the memory transistor may be used.

FIG. 10 shows a semiconductor memory according to a fifth embodiment of the present invention. FIG. 10A is a block diagram showing a part of the memory, and FIG. 10B is a block diagram of the latch block R of FIG. It is a circuit diagram.

In this embodiment, as a method of detecting the threshold value of the memory transistor, a method of driving a ground line made of metal wiring as a virtual ground line instead of driving the potential of the word line is adopted.

The output W _{0 of the} word line is connected to the gates of the comparison transistors H ₀₀ , H ₀₁ and H ₀₂ for comparison of the memory transistors MCT ₀₀ and MCT ₀₁ and the memory transistor. Memory transistor MCT
_One of the source and the drain of ₀₀ is connected to the bit line B ₀ , and the other is connected to the virtual ground line KG1. on the other hand,
One of the source and drain of the memory transistor MCT ₀₁ is connected to the bit line B ₀ , and the other is connected to the virtual ground line K.
It is connected to G2. One of the sources or drains of the comparison transistors H ₀₀ and H ₀₁ is commonly connected to the virtual ground line KG3, the other is connected to the sense lines SN ₀ and SN ₁ , and _one of the sources or drains of the comparison transistors H ₀₂ is sensed. connected to line SN _1, the other is connected to a virtual ground line KG4. Each source / drain is composed of a common diffusion layer. Each virtual ground line is formed of metal wiring made of aluminum wiring. Virtual ground line KG
1, KG2 are virtual ground lines (eg, KG) that are switched and selected by an address and are connected to a memory to be read.
1) is connected to the node V, and the other virtual ground line (eg, KG2) is connected to V _CC . Virtual ground line K
G3 and KG4 are also controlled to the potential of the node V or V _CC . The bit line B ₀ and the sense lines SN ₀ and SN ₁ each form a current mirror. Sense line SN
₀ is connected to the sense amplifier SA1, and the sense line SN ₁ is connected to the sense amplifier SA2. The block circuit R ₃ is
Input Q ₂ · S ₁ + inverted Q ₂ S ₂ and T ₂ and output D ₁ via Q ₁ and the inverter. Block circuit R
₄ inputs the S ₂ and T ₁ Q _2, via the inverter to output a D _2.

Next, referring to the timing chart of FIG.
Will be described. For the sake of explanation, the thresholds of the memory transistors MCT ₀₀ and MCT ₀₁ are V ′ _T1 and V ′ _T3 , respectively, and the thresholds of the comparison transistors H ₀₀ , H ₀₁ and H ₀₂ are V ′ _T0 , V ′ _T1 and V ′, respectively. Let _T2 be the relationship between the levels of the virtual ground line V _SS , V ₁ ′, V ₂ ′, V ₃ ′ and V _CC V _SS <V ₃ ′ <V ₂ ′ <V ₁ ′ <V _CC (FIG. 12) And Further, here, a method will be described in which the level of the virtual ground line is once set to V ₂ ′ and then the level of the virtual ground line is raised or lowered depending on the state of the memory transistor.

First, as an initial state, both timing signals T ₁ and T ₂ are set to H level. Then, the transistor 62 that inputs the power supply V ₁ ′ to the drain and Q ₂ · inversion B ₂ to the gate is off, and the transistor 6 that inputs the power supply V ₃ ′ to the drain and inversion Q ₂ and inversion B ₂ to the gate.
3 is off, the transistor 64 which inputs the power supply V ₂ ′ to the drain and the inversion B ₁ to the gate is also off, so the potential V of the common source of the transistors 62, 63 and 64 is floating. While the address signal A in the previous state is at the H level, the virtual ground line KG1 is charged to almost V _CC -V _Th . Word line W ₀
Also, the selector signal Y _{0 is} also set to H level to turn on each memory transistor and each comparison transistor. From the above configuration, the virtual ground line KG1 is connected to the node V and is in a floating level, and since the inversion A of the KG2 is L, the transistor 51 is on and the transistor 57 is off, so V _CC -V _Tn (N-type peripheral) It is precharged to near the transistor threshold). Moreover, the bit line B ₀ also rises to near V _CC -V _Tn . Therefore, no current flows in the memory transistor MCT ₀₁ . Further, since the virtual ground line KG4 is at the V _CC -V _Tn level, the comparison transistor H ₀₂ is off. (Period A) After initial setting, the timing signals B ₁ and B ₂ are set to (L, H). Then, the transistor 64 is turned on and the node V is lowered to the V ₂ ′ potential. Since the transistor 60 is also on, the virtual ground line KG3 is at V
₂ 'becomes the potential. The potential of KG1 also becomes V ₂ '. Since the threshold value of the memory transistor MCT ₀₀ is V ′ _T1 , the predetermined current I ₁ flows through the memory transistor MCT ₀₀ . Since the bit line B ₀ is commonly connected to the source and gate of the p-type transistor 53, the current I ₁ also flows through the p-type transistor 53. The p-type transistor 55 whose gate is connected to the bit line B ₀ is the transistor 53.
Of it tends to flow twice the current of the current I ₁ from being a 2W / L, the channel W / L of the comparison transistor H ₀₁ threshold is V _'T1 is current because it is the same as the transistor 53 Only I ₁ flows. Therefore, the level of S ₂₀ rises and the level of S ₂ via the sense amplifier SA2 rises to the V _CC level. In addition, the transistor 54,
Since the sense line SN ₀ and the comparison transistor H ₀₀ whose threshold is V ′ _T0 have the same structure, the output S of the sense amplifier SA1 is output.
₁ also becomes H level. The block circuit R ₃ receives the timing signal B ₂ and Q ₂ · S ₁ + inversion Q ₂ · S ₂ , but the data output D ₁ is also undefined because Q ₂ is undefined. Further, the block circuit R ₄ has a timing signal B ₁
= H level of S ₂ is latched by L level, Q ₂ is H level, data output D ₂ is L level, and “0” is output as data. During this period, the memory transistor M
Threshold CT ₀₀ is detected to be V _'T0 or V' _T1.

(Period B) Next, the memory transistor M
Threshold CT ₀₀ enters the detection operation of whether a 'or V is a _{T0' T1} V. Timing signal B ₂ is at L level,
When B ₁ becomes H level, the transistor 62 is turned on and 63 and 64 are turned off because Q ₂ is at H level during the period A, and the node V rises to the V ₁ ′ potential. Then, the virtual ground lines KG1 and KG3 become V ₁ 'and the memory transistor MCT ₀₀ becomes non-conductive. Therefore,
Since no current flows through the bit line B ₀ , the transistors 53, 54 and 55 are turned off. Virtual ground line KG3
Is at the V ₁ ′ potential, the comparison transistor H ₀₀ is turned on and the sense line SN ₀ drops to near the V ₁ ′ potential.
Therefore, the sense amplifier SA1 outputs the L level.
The block circuit R ₃ has (Q ₂ , S ₁ ) = (H,
L), the L level is latched by the L level of the timing signal B ₂ , the output D ₁ is at the H level, and the data “1” is output.
Is output. The block circuit R ₄ has a timing signal B
_{Since 1} is at H level, Q _{2 of} period A is held and L level, that is, data “0” is output regardless of the level of S ₂ .

(Period C) When the timing signals B ₁ and B ₂ become the H level, the transistors 62, 63 and 64 are turned off, and the node V becomes the floating level. Although both the virtual ground lines KG1 and KG3 are in a floating level and the outputs of S ₁ and S ₂ are not fixed, the block circuits R ₃ and R ₄ receive the H level timing signals B ₁ and B ₂ respectively, so B's Q
The outputs of ₁ and Q ₂ are held and the data outputs D ₁ and D ₂
Respectively yield (1,0).

(Period D) When the inversion A becomes H level,
The transistor 51 is turned off and the transistor 52 is turned on, so that the virtual ground line KG2 is connected to the node V. The node V is not connected to the power supplies V ₁ , V ₂ , and V ₃ because the timing signal B ₂ is at H level, but as described above, the virtual ground line KG was at V _CC -V _Tn level.
Since it is connected to 2, it rises to the V _CC -V _Tn level. Further, the memory transistor MCT ₀₁ threshold V _'T3 is selected for the virtual ground line KG2 and the node V is connected. Since the address signal A is at L level, the transistor 52 is on, and the transistor 56 is off, so that the virtual ground line KG1 is at V _CC -V _Tn level.
D ₁ and D ₂ are retained.

(Period E) When B ₁ becomes L level and B ₂ becomes H level, only the transistor 64 is turned on and the node V becomes the V ₂ ′ potential. Since the node V is at V ₂ ′ potential, the virtual ground line KG2 is also at V ₂ ′ potential. Since the threshold value of the memory transistor MCT ₀₁ is V ′ _T3 , the memory transistor MCT ₀₁ is non-conductive and no current flows through the transistor 53. Therefore, since the transistors 54 and 55 are off, no current flows through each transistor. Therefore, the sense lines SN ₀ and SN ₁ have the same potential V ₂ ′ as the virtual ground line KG3.
become. Therefore, the potentials S ₁₀ and S ₂₀ of each digit line are V
_The 2'level potential is amplified by the sense amplifiers SA1 and SA2 and S
Both ₁ and S ₂ are at the L level. The block circuit R ₃ is
Since the timing signal B ₂ is H level, L level Q
_It outputs ₁ and D ₁ holds "1". Block circuit R
₄ outputs a Q ₂ of L level is latched to L level S ₂ at the H-level timing signal B _2, D ₂ is "1"
Is output.

(Period F) Next, in the period up to the previous time, the threshold value of the memory transistor MCT ₀₁ is V ′ _T2 or V ′.
Is determined to be _T3, it determines threshold or V _'T2 or V' _T3 of the memory transistors during this period. Since the timing signal B ₁ is at H level, B ₂ is at L level, and Q ₂ is at L level in the period E, the transistors 62,
64 is off and 63 is on, and the node V becomes the V ₃ ′ potential. Although the virtual ground line KG2 is at the V ₃ ′ potential, the memory transistor MCT ₀₁ is non-conductive because the threshold value is V ′ _T3 , and thus the transistors 53, 54 and 55 remain off. Since the virtual ground line KG4 is at the V ₃ ′ potential, the comparison transistor H ₀₂ is turned on and a current flows from the sense line 1 to the virtual ground line KG4. S
₂₀ outputs an L level to S ₂ via the sense amplifier SA2 is withdrawn V ₃ 'potential. Since the timing signal B ₁ is input to the block circuit R ₄ , Q ₂ is L
As the level and data D ₂ , “1” is output. The block circuit R ₃ latches the L level at the L level of B ₂ because Q ₂ is at the L level and S ₂ is at the L level. As a result, Q
₁ is L level, and data output "1" is output.

(Period G) Since both the timing signals B ₁ and B ₂ are at H level and the node V is at floating level, KG2 is also at floating level. The other virtual ground lines are both at the V _CC -V _Tn potential. Also,
Timing signals B ₁ and
Since the H level is input to B _2, the level of the period F is maintained.

By the above operation, the memory transistor MC
T _00, the threshold value of the MCT ₀₁ is detected to V _'T1, V' _T2 respectively. If the thresholds of the memory transistors are V ′ _T0 , V ′ _T1 ,
When _V'T2 and _V'T3 , the above-mentioned operation is performed,
(0,0), (1,0), (0,1), (1,
1) is output.

With the above structure, since the virtual ground line (and digit line) is formed of aluminum wiring, the resistance is small, and the word line formed of polysilicon wiring (for example, even if the gate is formed of polysilicon and a tungsten layer). 1
The delay time is shorter than driving 0Ω / □). Therefore, since it is not necessary to increase the number of X decoders in order to shorten the word lines in consideration of the delay of the word lines, the number of X decoders can be reduced, and the cell occupation rate can be increased to increase the capacity.

FIG. 13 shows a circuit diagram of a memory according to the fifth embodiment of the present invention. In this embodiment, the potential of the node V is V ₁ ′ → V ₂ ′ → by the timing signals B ₁ , B ₂ and B ₃ .
A circuit for determining the threshold value of the memory transistor by changing it to V ₃ 'is disclosed. The block circuit of FIG. 13 (a) is shown in FIG. 13 (b). Memory transistors MCT ₀₀ and MCT ₀₁ connected to the word line, comparison transistors H ₀₀ , H ₀₁ and H ₀₂ , bit line B ₀ , sense lines SN ₀ and S.
N ₁ , virtual ground lines KG1, KG2, KG3, KG4
10 is the same as that in FIG. The circuit for controlling the voltage of the virtual ground includes V ₁ ′, V ₂ ′, V ₃ ′ and transistors 91, 92, 93 for switching the potentials.
And the timing signals T ₁ , T ₂ and T ₃ are input to the gates of the transistors ₁ , ₂ and ₃ , respectively. The virtual ground line K for controlling the potential of the virtual ground line
G1 is provided with a p-type transistor 80 whose gate receives the address signal A and whose drain is connected to V _CC, and an n-type transistor 81 whose drain is connected to the node V. Each virtual ground line KG2, KG3, KG
Similarly, a pair of P-type and N-type transistors 4 are similarly provided, and inversion A, inversion B ₁ + inversion B ₂ , and inversion B ₃ are connected to the gates of each pair of transistors. Transistor MK for commonly inputting Y selector output Y ₀ for controlling access to memory transistors to its gate
₁ , B ₀ , MK ₂ are provided on the virtual ground line KG1, the bit line B ₀ , and the virtual ground line KG2, respectively.
The bit line B ₀ and the sense lines SN ₀ and SN ₁ are provided with a transistor 84 having a W / L channel and transistors 85 and 86 having a W / L channel, respectively, and their gates are commonly connected. The outputs of the sense lines SN ₁ and SN ₂ are supplied to the block circuit R via sense amplifiers SA3 and SA4, respectively.
It is input to ₁ , R ₂ and R ₃ .

Next, the operation of this circuit will be described with reference to FIG. First, in the initial state A, the timing signals B ₁ , B ₂ , and B ₃ are all at the H level, the selector signal Y ₀ output from the Y selector, and the word line W ₀ are both at the L level. In the period B, the memory transistor MCT
_In order to perform the read operation of ₀₀ , the word line W ₀ , the selector signal Y ₀ , and the address signal A are set to the H level.
Then, the bit line B ₀ becomes the V _CC -V _Tn potential, and the potential of the virtual ground line KG1 also rises accordingly.

(Period C) When the timing signal T ₁ becomes L level and B ₂ and B ₃ become H level, the node V and the virtual ground line KG1 become V ₁ ′ potential. Further, the transistor 88 to which the inverted B ₁ + inverted B ₂ is input to the gate is turned on, and the virtual ground line KG3 becomes the V ₁ ′ potential. However, the memory transistor M threshold is V _'T1
Since CT ₀₀ does not conduct, transistors 84, 85,
86 is also non-conductive. Since the virtual ground line KG3 is at V ₁ potential, the sense line SN ₀ , that is, S ₁₀ is also close to V ₁ ′ potential, and S ₁ amplified by the sense amplifier SA3 becomes L level. The block circuit R ₁ is (B ₁
= L, S ₁ = L) and Q ₁ = L is output. In the block circuits R ₂ and R ₃ , the timing signals B ₂ and B ₃ are at H level.
The output is not fixed because S ₂ is undefined at the level.

[0061] (period D) timing signal B ₂ is L level, the B _1, B ₃ becomes the H level, the node V, the virtual ground line KG1, KG3 becomes V ₂ 'potential. Therefore, the memory transistor MCT ₀₀ becomes conductive and the transistor 84
A predetermined current I ₁ flows through. Due to the current flowing through the transistor 84, twice as much current as the transistor 84 tends to flow through the transistors 85 and 86. However, since the virtual ground line KG3 has the V ₂ ′ potential, the comparison transistor H ₀₁ has only a current of approximately V ₁ flowing, so that the potential of S ₂₀ approaches the V _CC potential, and the sense amplifier SA.
The output of 4 is H level. S _10, the level of S ₁₀ to determined the magnitude of the current of the comparison transistor H ₀₀ which is conducting is unknown. The block circuit R ₁ holds Q ₁ = L because the timing signal B ₁ = L and Q ₁ = L in the period C. The block circuit R ₂ has S ₂ =
H, Q ₁ = L is latched by the timing signal B ₂ and Q ₂ =
Outputs H level. The block circuit R ₃ inputs S ₂ = H but is reset to Q ₃ = L level because Q ₂ (= H) is input as a reset input.
The NOR circuit 1 inputs (L, L) to input the data “1”.
The NOR circuit 2 inputs (L, H) and outputs data “2”.

(Period E) Timing signals B ₁ , B ₂ =
Since H level and B ₃ = L level, the node V is V
₃ 'becomes the potential. Block circuit R _1, R ₂ is the output of the period D regardless of the level of S _1, S ₂ since the input both H-level timing signal _{B 1, B 2 (Q 1} ,
Hold Q ₂ ) = (L, H). The block circuit R ₃ is
Although the H level of S ₂₀ is input, it is still reset by Q ₂ = H, so Q ₃ is held at the L level.

From the above operation, the memory transistor MCT
The information of ₀₀ is read as (1, 0). Next, address signal A
Is inverted to start the read operation of the memory transistor T2. The read operation of the memory transistor MCT ₀₁ is
As with the memory transistor MCT ₀₀ , it is read by operating the timing signal. Although the threshold value of the memory transistor is _V'T1 in the above description, the threshold values are _V'T0 and V '.
_T2, each of the data (0, 0) when the V _'T3, (0,
1) and (1, 1) are output.

The timing signals T ₀ , T ₁ and T ₂ are as shown in FIG.
It is generated by a pulse generation circuit as shown in FIG. The pulse generation circuit inputs the pulse ATD generated by detecting a change in address to one of the two NOR circuits 100,
The flip-flop 104 formed by 101 and the output of the flip-flop 104 are input to the delay circuit 102 as the timing signal T ₁ , and the output of the delay circuit 102 is passed through the inverter circuit 103 to one of the flip-flops 109 of the next stage. And a circuit for inputting to the other side of the preceding flip-flop 100 are combined in a plurality of stages.

Next, the operation will be described. First, each timing signal B _i is set to “1” as an initial operation. Then, the low level is input to the other terminal of the terminal to which the pulse ATD of the flip-flop 104 is input. Next, the pulse ATD is input to one of the flip-flops 104. Then, the flip-flop 104 outputs the low-level timing signal T ₀ at the high level of the ATD signal. This low-level timing signal outputs a high-level signal A0 via the delay circuit 102 and the inverter circuit 103. Then, this high level signal A
0 is input to the other terminal of the previous flip-flop,
As a result, the timing signal T ₁ becomes high level. From the above operation, the timing signal T ₀ having a pulse shape whose low level period is t _D0 is generated. The output A0 of the inverter circuit 103 is the flip-flop 10 of the next stage.
The signal is input to one of 9 to perform the same operation as the above pulse generating circuit and generate timing signals T ₁ and T ₂ . From the above, T ₀ , T ₁ , T _2, ... Are formed one after another.

FIG. 15 shows a circuit diagram of the sense amplifier circuit SA. The sense amplifier SA is the transistor 53 of FIG.
The output is controlled by the potential difference between the output S ₀ of S ₀ and the output S ₁₀ and S ₂₀ of the transistors 54 and 55. The W / L of the transistors 120 and 121, 122 and 123 are formed to have the same size.

When S ₀ has a lower potential than S ₁₀ (or S ₂₀ ), that is, when the selected memory transistor is conductive, the output is L level, that is, the inverter 124 outputs H level. Conversely, when S ₀ has a higher potential than S ₁₀ (S ₂₀ ), that is, when the selected memory transistor is non-conductive and the comparison transistor is conductive, the H level, that is, the inverter 124 is L level. Output level.

FIG. 16 shows a constant potential generating circuit used in the fourth and fifth embodiments. Threshold all the gates connected to potential 'power supply voltage V _CC and V ₁ a plurality of transistors 125 is _T1 in parallel with the source-drain terminal' V is connected to the power supply potential V _CC. As in this configuration, the threshold value is _V'T2 ,
A plurality of transistors 126 and 127 are provided each of which is V _'T3. A transistor 129 for inputting the power supply voltage V _CC to the gate is provided between the sources of the plurality of transistors 125 and the ground potential GND. In addition, the transistors 129, 130, and 131 are N-type transistors having the same and large channel width.
It is configured such that the current flowing through the transistor 9 can also flow through the transistors 130 and 131. Each of 125, 126 and 127 is connected in parallel in the number of 10 or more and about 100.

Each virtual ground level generated by this circuit is actually V ₁ '= V _CC -α _{0 V'T0} ,
V ₂ ′ = V _CC −α ₁ V ′ _{T 1} , V ₃ ′ = V _CC −α ₂ V ′ _{T 2}
Therefore, even if the thresholds between the thresholds are set equal, the respective virtual ground levels are corrected by the influence of the back bias. The respective correction amounts have a relationship of α ₀ > α ₁ > α ₂ > 1, and for example, when V ′ _T0 = 1V, α ₁
= About 1.5 times.

The present invention is not limited to the above-described embodiments, but can be modified in various ways without departing from the scope of the invention. For example, word line, virtual G
A method in which the ND line is smoothly moved up and down instead of in a stepwise manner is also possible. However, in this method, it is necessary to accurately match the rising and falling speeds with the timings of T ₀ , T ₁ , and T ₂ , and as a result, the rising and falling speeds are slowed down by a factor of 2 or more compared to the method of driving in a stepwise manner. In addition, the timing margin must be increased.

[0071]

As described above, according to the read method of the read-only memory device of the present invention, sensing is performed in the conductive state of the memory transistor and the conductive state of the comparison transistor.
It is not necessary to wait until the digit line is discharged, and the reading speed is increased accordingly.

Since the output is determined by the current difference between the memory transistor and the comparison transistor, the word line level or the virtual ground line level can be read correctly even if the level fluctuates.

The third embodiment has the advantages that the number of transistors is smaller than that of the first embodiment and the timing management is easy.

The fourth embodiment has an effect that a virtual GND line made of aluminum wiring is driven as a method of reading a multi-valued memory transistor, so that aluminum wiring delay can be ignored and designing and manufacturing are facilitated. Further, since the delay can be ignored, the number of X decoders can be reduced, and as a result, the chip size can be reduced. Further, since the method of setting the level of the virtual GND line once to the intermediate level and then moving it up and down is applied, there is an effect that four-value determination can be performed during the period of the timing signals T ₁ and T ₂ .

The fifth embodiment has the effect that it has a simpler configuration than the third embodiment.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory according to a first embodiment of the present invention.

2 (a) is a circuit diagram of a part of the memory according to the first embodiment of the present invention, and FIG. 2 (b) is FIG. 2 (a).
Another circuit diagram shown by.

FIG. 3 is a timing chart of a part of the memory according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the relationship between the threshold value of the memory T _r and the level of the word line W ₀ .

FIG. 5 is a circuit diagram of a part of the memory according to the second embodiment of the present invention.

FIG. 6 is a circuit diagram of a part of the memory according to the third embodiment of the present invention.

FIG. 7 is a diagram showing the relationship between the threshold value and the word line drive level according to the present invention.

FIG. 8 is a word line potential generation circuit according to the first, second and third embodiments.

FIG. 9 is a voltage generation circuit according to first, second, and third embodiments.

10A is a circuit diagram of a part of the memory according to the fourth embodiment of the present invention, and FIG. 10B is a circuit diagram of FIG.
Another circuit diagram shown by 0 (a).

FIG. 11 is a timing chart of a part of the memory according to the fourth embodiment.

FIG. 12 is a relationship diagram between a threshold value and a virtual ground line drive level according to the fourth embodiment.

13 (a) is a circuit diagram of a part of the memory according to the fifth embodiment of the present invention, and FIG. 13 (b) is a circuit diagram of FIG.
Another circuit diagram shown by 3 (a).

FIG. 14 is a timing chart of a part of the memory according to the fifth embodiment of the present invention.

FIG. 15 is a pulse generation circuit as used in the present invention.

FIG. 16 is a sense amplifier used in the fourth and fifth embodiments of the present invention.

FIG. 17 is a constant voltage generating circuit used in the fourth and fifth embodiments of the present invention.

FIG. 18 is a circuit diagram of a first conventional multi-level memory cell.

FIG. 19 is a circuit diagram and timing chart of a second conventional multi-level memory cell.

[Explanation of symbols]

MCT _{00 to} MCT _NM memory transistor H _{00 to} H _NJ comparison transistor W ₀ word line 1,44 conversion circuit D ₁ , D ₂ data output Y ₀ select signal line 12, 13, 14, 31, 32, 33, 54, 55,8
5,86 P-type transistor with channel width of 2 W 11,30,53,84 P-type transistor with channel width of W 18 Inverters R ₀ , R ₁ , R ₂ Block circuit 45 Voltage control circuit SA1, SA2 Sense amplifier KG1 , KG2, KG3, KG4 Virtual ground line A Address signal 104, 109, 114 Flip-flop circuit 102, 107, 112 Delay circuit

Claims (8)

[Claims] 1. At least one word line, at least one memory transistor having a gate connected to the word line, the memory transistor having a threshold value selected from a plurality of threshold values, and the word line. Between the gates of the memory transistor and the comparison transistor, which are connected to each other, each having a plurality of comparison transistors each having a threshold value selected from the plurality of threshold values, which are different from each other. A voltage driving unit that drives a plurality of voltages, and a current that flows in the memory transistor and a transistor circuit that is connected to the memory transistor and the comparison transistor and that is driven by each of the plurality of voltages. The logic level state based on the difference between A semiconductor memory device comprising: a sense circuit which outputs multi-bit data stored in the memory transistor based on the held logic level state. 2. The voltage driving means selects one of a plurality of potentials generated by a potential generation circuit by a timing signal when a predetermined level is formed by a combination of addresses, and selects one of the plurality of potentials. 2. The semiconductor memory device according to claim 1, wherein is output. 3. The sense circuit is configured by a current mirror circuit having the memory transistor side as an input or an output, the comparison transistor side as an output or an input, and having different input / output current ratios. The semiconductor memory device according to claim 1. 4. At least one word line, at least two memory transistors each having a gate connected to the word line, each memory transistor having a threshold value selected from a plurality of threshold values, and the word. Transistor circuits each having a gate connected to a line, each having a plurality of comparison transistors having different thresholds and having thresholds selected from the plurality of thresholds, and drains of the plurality of comparison transistors adjacent to each other. Or a first ground line commonly connected to one of the sources, a plurality of sense lines connected to the other of the drains or sources thereof, and a bit commonly connected to one of the drains or sources of the memory transistors. Line and the other of the drain or source of each of the memory transistors Second ground lines connected to each other, voltage driving means for driving the first and second ground lines to a potential of a plurality of voltages according to a timing signal, and the first and second grounds. A switching means for switching a line to a power supply voltage or a driving voltage, and a current mirror circuit that inputs and outputs each of the bit line and each of the plurality of sense lines, and is driven by each of the plurality of voltages. And a sense means for holding a logic level state based on a difference from a current flowing through the memory transistor and outputting multi-bit data stored in the memory transistor based on the held logic level state. A semiconductor memory device characterized by the above. 5. The memory transistor is a memory transistor set to one threshold value among four-valued threshold values, and the ground line is set between an upper second value and a lower second value of the four-valued threshold value. If the memory transistor is conductive, the ground line is connected to the lower 2
The threshold value of the memory transistor is set to the lowest threshold value among the lower two values if it is conductive, and the threshold value of the memory transistor is set to the upper one of the lower two values if it is not conductive. If the memory transistor is non-conductive, the ground line is set to an intermediate potential level between the upper two values, and if the memory transistor is conductive, the threshold value of the memory transistor is set to the upper two values. 5. The semiconductor memory device according to claim 4, further comprising means for setting the threshold value of the lower one of the two threshold values to be the highest threshold value of the upper two values when it is non-conductive. 6. The timing signal is a latch circuit having one input terminal for inputting a signal generated by a change in an address and the other input terminal, and the one signal is a first logic. Sometimes, the second logic is output, and when the one signal is the second logic and the other signal is the first logic, the second logic is output and the one signal is output. However, when it is the second logic and the other signal is the second logic, the latch circuit that outputs the logic that holds the previous state and the signal of the latch circuit are delayed and inverted. 5. The semiconductor memory device according to claim 2, further comprising means for generating a signal of the other circuit of the latch circuit. 7. The sense circuit is a sense circuit for comparing the potential of the bit line with the potential of the sense line, and when the potential of the bit line is higher than the potential of the sense line, a first circuit is provided. 5. The semiconductor memory device according to claim 4, wherein the second logic is output when the potential of the bit line is lower than the potential of the sense line. 8. At least one memory transistor having a gate connected to a word line, the memory transistor having a threshold value selected from a plurality of threshold values, and each gate connected to the word line. And a transistor circuit having a plurality of comparison transistors each having a threshold value selected from a plurality of threshold values different from each other, and driving a plurality of voltages between the gate and the source of the memory transistor and the comparison transistor, respectively. Then, each time each of the plurality of voltages is driven, a logic level state based on the difference between the current flowing in the memory transistor and the current flowing in the transistor circuit is held, and based on the held logic level state. Outputting multi-bit data stored in the memory transistor Read method of semiconductor device.