JP2774244B2 - Level conversion circuit, semiconductor integrated circuit, and control method therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an image memory, a synchronous dynamic random access memory (SDRAM), and a static random access memory (SDRAM) in which a number of data lines operate in parallel on a semiconductor chip in synchronization with a clock signal. SRAM) and other memory circuits, level conversion circuits used in microprocessors and the like that perform parallel data processing, and semiconductor integrated circuits using the same.
And to improvements in these control methods.

[0002]

2. Description of the Related Art Conventionally, a level conversion circuit for converting the amplitude level of an output signal into a level different from the amplitude level of an input signal is disclosed in, for example, Japanese Patent Application Laid-Open No. H4-211515 (Nakagomi et al.).
Hitachi, Ltd.). Hereinafter, this conventional technique will be described.

[0003] The conventional technique will be described with reference to FIGS. 27 and 28.

FIGS. 27 (a) and 27 (b) show a clock-synchronous level conversion circuit and its operation explanatory diagram. In FIG. 2A, CLK (3) and XCLK (2) are synchronization signals (clock signals),
Vin (11) is an input signal before level conversion, VH (90) is a high-level power supply after level conversion, and VL (91) is a low-level power supply after level conversion. VM (9) is a precharge power supply, and the power supply potential is an intermediate potential between the high-level potential VH and the low-level potential VL.

Next, the operation will be described with reference to FIG.
PMOSFET (5) controlled by clock signals CLK and XCLK
When the NMOSFET (6) is turned on, the inverter operation becomes possible, and the input Vin (11) is inverted and taken in. For example, if Vin (11) is at the power supply potential Vcc level, the output is V
It becomes the low level value of L (91). Next, when the clock signals CLK and XCLK are inverted, the PMOSFET (5) and the NMOS
When T (6) turns off, PMOSFET (12) and NMOSFET (9)
Turns on, the output is connected to the precharge power supply VM (9), and the output is precharged to an intermediate potential. The above operation is made one cycle, and thereafter, the same operation is repeated, and the input Vin (1
If 1) is inverted every cycle, the output is also inverted. In the above operation, the change width of the output level is (VH-VM), (VM-V
L), which is smaller than the change in the input level (Vcc-Vss). That is, the amount of charge for charging and discharging the parasitic capacitance CD (10) of the output node Vout can be reduced. Since this charge amount is determined by the product of the amount of change in the potential of the capacitor and the capacitance value, if the ratio of the amplitude level between the input and the output becomes 1/10 by this level conversion circuit, the output node is charged and discharged. Electric charge is 1/10
In comparison with the case where level conversion is not performed, 1 /
10 lower power consumption is possible.

Next, the level-converted power supply VH (90)
, VL (91) are shown in FIG. This generation circuit is built on the same chip. Generally, as shown in the figure, the power supply circuit is a current mirror type output with the potential divided by resistors R1, R2, and R3 as the reference potential. The method of controlling the output transistor of the above is adopted. The voltage levels of the power supplies VH (90) and VL (91)
Arbitrary selection can be made by adjusting the ratio of R1, R2, and R3.

However, in the internal power supply circuit shown in FIG. 28, it is necessary to supply a power supply current of a driver for driving a wiring having a large capacity with a low resistance, so that the size of the current mirror and the output transistor becomes large. The resistors R1, R2, R3, and R4 that generate the reference potential cannot be selected with high resistance values, and as a result, the through currents IDC1 and IDC2
Is increased to about several mA, resulting in a disadvantage that current consumption increases unnecessarily.

[0008] Looking at the drawbacks of the prior art in terms of power consumption, the power consumption of the level conversion circuit of FIG. 27 is Ptoal = P1 +
It becomes P2. Here, P2 is determined by the product of the current consumption when the wiring capacitance is driven at the amplitude after the level conversion and the amplitude voltage after the level conversion. The power P1 is power that is wasted when the internal power supply circuit performs a voltage drop when generating the internal voltages VH and VL. The current consumption at the time of driving and the amount of voltage (Vcc
-VH + VL), and if the amount of the voltage drop is large, that is, if the output amplitude value is to be reduced, the wasteful power consumption P2 is further increased.

Further, in an image memory or the like, 64 bits, 128 bits,
Since bits or 256 bits operate simultaneously in parallel on the same chip, the above-mentioned power consumption is multiplied by the number of bits, so that there is a disadvantage that a large amount of power is consumed as a whole.

Further, in the level conversion circuit shown in FIG. 27A, the delay time from when the input Vin (11) changes in synchronization with the clock signal until the output is output is td1 shown in FIG.
The delay time td1 is mainly different from the power supply potentials VH (90) and VL (91) which are the source potentials of the PMOSFET (4) and the NMOSFET (7) as the input gates. Although the input is determined by the time required to lower or increase by the threshold voltage of the PMOSFET (4) and the NMOSFET (7), respectively, the power supply potential VH (90) is further reduced so as to further reduce the output amplitude. When the value is lowered and the value of the power supply potential VL (91) is raised, the input is further reduced to the low potential Vss or the high potential Vcc.
Otherwise, the PMOSFET (4) and the NMOSFET (7) do not turn on, so that the delay time td1 increases.

In order to avoid the above-mentioned power loss of the internal power supply circuit, Japanese Patent Application Laid-Open No. 4-302463 (Takashima et al.
(Toshiba) has been proposed. As shown in FIG. 29A, this technique has a circuit 500 having the same power supply current change characteristic with respect to time, that is, having the same on-resistance.
Are connected in series between the power supply Vcc and the ground line Vss, and the terminal voltage effectively applied to each circuit is reduced to a half voltage of the power supply Vcc. In other words, this technique is based on FIG.
As shown in (b), the power supply current is equal at each point of the time change, that is, by connecting in series the circuits having the same internal on-resistance as shown in FIG. During operation, a voltage drop is performed to perform the same operation as the internal power supply circuit of the first conventional example.

[0012]

However, in the prior art shown in FIG. 29, if the power supply current of each circuit is not equal to each time, the voltage determined by the resistance division fluctuates, and the effective current of each circuit is changed. Has the disadvantage that the terminal voltage fluctuates. In addition, since the power supply current of each circuit needs to be supplied by the ground current of the circuit on one stage above itself, FIG.
9 (b), that is, when the power supply current of each circuit 500 and the ground currents (I1 and I1X) and (I2 and I2X) are not equal at each time, the current cannot be reused. DRAM
Considering a sense amplifier operation that performs a parallel operation and restores a bit line potential that consumes a large amount of current, the power supply current is generally reduced to prevent a through current between the power supply and ground of each circuit. The size and wiring resistance of the transistors that perform each function are changed so that there is a time lag between the charging operation that flows and the discharging operation that flows the ground current.
It is impossible to equalize the charging current and the discharging current of each circuit at each time without increasing the through current. Therefore, in order for the upper and lower circuits 500 and 500 to operate in the same manner, it is necessary to supply a current from an additional circuit to the lower circuit 500. Even with this conventional technique, it is still necessary to drive the wiring capacitance. There is a drawback in that unnecessary current consumption other than the necessary current consumption is required.

The present invention has been made in view of the problems of the first and second prior arts, and has as its object the conventional wiring capacitance regardless of the number of simultaneously operating level conversion circuits. The wiring capacity on the output side of the level conversion circuit is driven at high speed with low power consumption, without needless power consumption other than the current consumption required to drive the power supply. The goal is to improve.

[0014]

In order to achieve the above object, according to the present invention, an electric charge is accumulated by using a capacitor or the like, and the accumulated electric charge is reused for a potential change of an output node of a level conversion circuit. By doing so, it is possible to eliminate unnecessary power consumption as in the related art.

That is, a specific configuration of the level conversion circuit according to the first aspect of the present invention receives a signal that changes to two different values and operates in synchronization with a clock signal.
An inverter-type level conversion circuit that converts the amplitude value of the input signal into another amplitude value and outputs the converted signal from a single output node, wherein first charge supply means is precharged to a first potential; A second charge supply unit that is precharged to a second potential different from the first potential, and one of the two charge supply units is selected according to the input signal;
Discharging means for discharging the charge accumulated in the selected charge supply means to the output node.

A specific configuration of the level conversion circuit according to the second aspect of the present invention receives a signal that changes to two different values as input, operates in synchronization with a clock signal, and outputs an amplitude value of the input signal. To a different amplitude value and outputting from two output nodes, a first charge supply means precharged to a first potential,
A second charge supply unit that is precharged to a second potential that is different from the first potential, and charges the charge accumulated in the first charge supply unit in response to the input signal; Discharging means for discharging to one of the nodes and discharging the charge stored in the second charge supply means to the other output node.

According to a third aspect of the present invention, in the level conversion circuit of the first or second aspect, the output node is connected to the first potential of the first charge supply means and the second charge supply means. And a precharge circuit for precharging to a third potential between the second potential and the second potential.

According to a fourth aspect of the present invention, in the level conversion circuit of the third aspect, in the complementary level conversion circuit, the precharge circuit is configured to short-circuit two output nodes. .

In addition, in a specific configuration of the control method of the level conversion circuit according to the present invention, the output node is set to the third potential by the precharge circuit in the first period within one cycle of the clock signal. And precharges the first charge supply means and the second charge supply means to a first potential and a second potential, respectively, in a second period within one cycle of the clock signal, In a third period after the first period and the second period in one cycle of the signal, the charge precharged to the charge supply unit by the discharge unit is discharged to the output node.

Further, according to the invention described in claim 6, according to claim 2,
In the level conversion circuit described above, the first charge supply means or the second charge supply means is configured by a high-potential power supply line.

Further, in the invention according to claim 7, in the level conversion circuit according to claim 2, the first charge supply means or the second charge supply means is constituted by a low potential power supply line. is there.

In addition, a specific configuration of the invention according to claim 8 specifies the charge supply means of the invention according to claim 1, 2, or 5, and the charge supply means is constituted by a capacitor. The ratio between the capacitance value of the capacitor and the parasitic capacitance value of the output node is determined by the potential difference between the potential of the output node to be realized and the second potential which is the precharge potential of the output node, and the second difference which is the precharge potential of the capacitor. 1
And the potential difference between the potential of the output node and the potential of the output node.

In addition, a specific configuration of the semiconductor integrated circuit according to the ninth aspect of the present invention receives a signal that changes to two different values, operates in synchronization with a clock signal, and operates in synchronization with a clock signal. A plurality of level conversion circuits for converting an amplitude value to another amplitude value and outputting the converted value from an output node are provided. Two of the plurality of level conversion circuits transfer charges at the output node between the two level conversion circuits. Charge amount change characteristic equalizing means for setting the charge amount change characteristics in opposite directions and having the same absolute value of the charge with respect to time; and charge transfer between two level change circuits having the same charge amount change characteristics. And a charge redistribution means for performing the movement of the charge.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit of the ninth aspect, each of the plurality of level conversion circuits has a complementary level having two output nodes whose outputs are complementary. The configuration is a conversion circuit.

According to a further aspect of the present invention, in the semiconductor integrated circuit according to the tenth aspect, the plurality of level converting circuits include one level converting circuit according to the sixth aspect,
According to a seventh aspect of the present invention, the two level conversion circuits are arranged in series between a high-potential power supply line and a low-potential power supply line.

According to a twelfth aspect of the present invention, in the semiconductor integrated circuit of the tenth aspect, the plurality of level conversion circuits are one or more level conversion circuits of the second aspect. Item 1, one level conversion circuit;
According to a seventh aspect of the present invention, there is provided one level conversion circuit, wherein the plurality of level conversion circuits are arranged in series between a high-potential power line and a low-potential power line.

According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit according to the tenth, eleventh or twelfth aspect,
The transistor of the level conversion circuit that outputs a higher potential from the output node as compared with the potential of an intermediate value between the potential of the high potential power supply line and the potential of the low potential power supply line is formed of a P-type MOSFET, and has a low potential. Is output from the output node, the transistors of the level conversion circuit are configured by N-type MOSFETs.

According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit according to the tenth, eleventh, twelfth, or thirteenth aspect, the charge amount variation characteristic equalizing means includes two output terminals having substantially the same parasitic capacitance value. The circuit comprises precharge means for precharging the nodes to the same potential, charge accumulation means for accumulating charges, and charging means for charging the charge accumulation means to a potential different from the predetermined potential.

In addition, the invention according to claim 15 is the semiconductor integrated circuit according to claim 14, wherein the charging means comprises:
In this configuration, the charge storage means is charged to a potential between the precharge potentials of the two level conversion circuits for performing the charge redistribution.

[0030] In addition, the invention according to claim 16 is the semiconductor integrated circuit according to claim 15, wherein the charge storage means is shared by two level conversion circuits that perform charge redistribution. It is.

According to a seventeenth aspect of the present invention, in the semiconductor integrated circuit according to the sixteenth aspect, the charge accumulating means is shared by two level conversion circuits which perform charge redistribution, and the charging means is a charge accumulating means. The charge is alternately charged to the vicinity of the precharge potential of one of the level conversion circuits for redistribution and the vicinity of the precharge potential of the other level conversion circuit. In this configuration, the periods are set to be shifted from each other by a half period.

Further, in the invention according to claim 18, in the semiconductor integrated circuit according to claim 14 or 15, the charge redistribution means comprises one of both charge storage means of the two level conversion circuits for redistributing charges. Connected to the output node of one of the two level conversion circuits which changes to the higher potential side, and the other charge storage means is connected to the output node of the other level conversion circuit which changes to the lower potential side. This is a configuration for connecting to an output node.

In addition, in the invention according to claim 19, in the semiconductor integrated circuit according to claim 10, the charge amount change characteristic equalizing means comprises two level conversion circuits having substantially the same parasitic capacitance value in each level conversion circuit. The output node is precharged to a predetermined potential, and the potential difference between the precharge potentials of the respective level conversion circuits is set to the same value or the ratio of the reciprocal of the parasitic capacitance value of each of the level conversion circuits. .

According to a twentieth aspect of the present invention, in the semiconductor integrated circuit according to the nineteenth aspect, the charge redistribution means is provided in two level conversion circuits which are adjacent to each other and have a precharge potential to perform charge redistribution. In this configuration, one of the level conversion circuits short-circuits an output node that changes to a low potential side in response to an input, and the other level conversion circuit short-circuits an output node that changes to a high potential in accordance with the input.

Further, in the method of controlling a semiconductor integrated circuit according to the present invention, two output nodes in each level conversion circuit are precharged to the same potential in a first period within one cycle of a clock signal. In a second period within one cycle of the clock signal, each charge accumulating means of the two level conversion circuits for redistributing charges is connected between the two precharge potentials of the two level conversion circuits for redistribution of charges. The two charge conversion circuits of the two level conversion circuits for redistributing the charges during a third period after the first period and the second period within one cycle of the clock signal after charging to a predetermined potential. One of the means is connected to an output node of one of the two level conversion circuits for redistributing the charges, which is changed to a higher potential side, and the other charge storage means is connected to the other level conversion circuit by the other level conversion circuit. Change to low potential side It is configured to connect to the output node of the side to be.

In addition, in the invention according to claim 22, in the method of controlling a semiconductor integrated circuit according to claim 21, the potential for charging two charge storage means during a second period within one cycle of the clock signal. Is a potential between two precharge potentials of two level conversion circuits for redistributing charges.

According to a twenty-third aspect of the present invention, in the control method of the semiconductor integrated circuit according to the twenty-first aspect, the two charge storage means are charged in a second period within one cycle of the clock signal. The potential is one of the charge storage means
The potential is substantially the same as the precharge potential of one of the two level conversion circuits for redistributing charges, and the other charge storage means is substantially the same potential as the precharge potential of the other of the two level conversion circuits for redistributing charges. The configuration is as follows.

According to a twenty-fourth aspect of the present invention, in the level conversion circuit or the method of controlling a semiconductor integrated circuit according to the fifth, twenty-second, twenty-second, or twenty-third aspects, the first period and the second period are the same period. The configuration is as follows.

According to a twenty-fifth aspect of the present invention, there is provided a control method for controlling a semiconductor integrated circuit according to the nineteenth or twentieth aspect, wherein each of the level conversion circuits performs a predetermined period within one cycle of a clock signal. The two output nodes are precharged to the same potential, and then the charge redistribution is performed in a period after the predetermined period in one cycle of the clock signal.
In this configuration, one of the level conversion circuits is connected to an output node that changes to a higher potential side in one level conversion circuit, and an output node that changes to a lower potential side in the other level conversion circuit.

According to a twenty-sixth aspect of the present invention, in the semiconductor integrated circuit according to the ninth or tenth aspect,
In this configuration, a through-current preventing unit is provided between two power supply terminals and controls so that a through-current does not flow between the two power supply terminals.

According to a twenty-seventh aspect of the present invention, in the semiconductor integrated circuit according to the twenty-sixth aspect, the through current prevention means comprises a plurality of transistors, and controls the plurality of transistors so as not to be simultaneously turned on. It is a configuration that is

According to a twenty-eighth aspect of the present invention, in the semiconductor integrated circuit according to the twenty-seventh aspect, the plurality of transistors are controlled by an independent control signal different from the input of the level conversion circuit.

According to a twenty-ninth aspect of the present invention, there is provided a level conversion circuit or a method for controlling a level conversion circuit according to the first, second, third, fourth, fifth, sixth, seventh or eighth aspect. Are provided, and output nodes respectively provided in some of the plurality of level conversion circuits are connected in parallel with each other, and the plurality of output nodes connected in parallel are connected to the first charge supply means or the second charge supply means. Is connected to the charge supply means.

According to a thirtieth aspect of the present invention, in the level conversion circuit or the control method of the level conversion circuit according to the first, second, third, fourth, fifth, sixth, seventh, or eighth aspect, a plurality of level conversion circuits are provided. Output nodes provided in some of the plurality of level conversion circuits are connected in series with each other, and each of the plurality of output nodes connected in series is connected to the first charge supply unit or the second charge supply unit. Is connected to the charge supply means.

Further, the invention according to claim 31 is the level conversion circuit according to claim 6, wherein the high potential power supply line is a high potential external power supply line.

In addition, the invention according to claim 32 is the level conversion circuit according to claim 6, wherein the high-potential power supply line is a high-potential internal power supply line.

In addition, the invention according to claim 33 is the level conversion circuit according to claim 7, wherein the low potential power supply line is a low potential external power supply line.

According to a thirty-fourth aspect of the present invention, in the level conversion circuit of the seventh aspect, the low potential power supply line is a low potential internal power supply line.

Further, according to the invention of claim 35, in the semiconductor integrated circuit or the method of controlling a semiconductor integrated circuit according to claim 19, 20, or 25, the plurality of level conversion circuits include a first power supply, A level conversion circuit which is arranged in series between a second power supply having a potential different from the potential of the first power supply and has a large change degree of an output node with respect to time among the plurality of level conversion circuits, In this configuration, the circuit is arranged at a position closer to the first power supply or the second power supply than the remaining level conversion circuit.

According to a thirty-sixth aspect of the present invention, in the semiconductor integrated circuit or the method of controlling a semiconductor integrated circuit according to the thirty-fifth aspect, the level conversion circuit comprising a P-type MOSFET is close to a power supply having a high potential. It is a configuration arranged on the side.

In addition, the invention according to claim 37 is the semiconductor integrated circuit or the method for controlling a semiconductor integrated circuit according to claim 35, wherein the level conversion circuit composed of an N-type MOSFET is connected to a power supply having a low potential. It is a configuration arranged on the near side.

According to a thirty-eighth aspect of the present invention, in the semiconductor integrated circuit according to the ninth aspect, a plurality of level conversion circuits are provided, wherein a plurality of level conversion circuits having the same degree of change of the output node with respect to time are provided. The comrades are the first
And a second power supply having a potential different from the potential of the first power supply.

According to a thirty-ninth aspect of the present invention, in the semiconductor integrated circuit according to the thirty-eighth aspect, the plurality of level conversion circuits are grouped by level conversion circuits having the same degree of change of the output node with respect to time. The level conversion circuits belonging to each group are arranged in series between a first power supply and a second power supply.

In addition, in the invention according to claim 40, in the level conversion circuit according to claim 39, a group of the level conversion circuits whose output nodes have a large degree of change with respect to time, and a degree of change of the output nodes with respect to time. Has a configuration in which the cycle of the operation clock is different from the group of the level conversion circuits having a smaller value.

In addition, in the invention according to claim 41, in the semiconductor integrated circuit or the method of controlling a semiconductor integrated circuit according to claim 19, 20 or 25, the charge amount change characteristic equalizing means includes the plurality of level conversion circuits. In this configuration, the connection to the power supply is controlled at a cycle that is an integral multiple of the cycle of the operation clock of the circuit.

The invention according to claim 42 is the semiconductor integrated circuit according to claim 9 to claim 41, wherein
Potential detecting means for detecting the potential of the corresponding output node is connected to output nodes of a plurality of level conversion circuits arranged in series between the power supply and the second power supply. Among the potential detection means, the potential detection means corresponding to the output node of the level conversion circuit on the side where the precharge potential of the output node of the level conversion circuit is higher than the intermediate potential between the first power supply and the second power supply is , N-type MOSFETs, and the potential detection means corresponding to the output node of the level conversion circuit on the side lower than the intermediate potential is constituted by a P-type MOSFET.

According to a thirty-third aspect of the present invention, in the semiconductor integrated circuit according to the thirty-second aspect, an output of the potential detecting means constituted by an N-type MOSFET is an N-type pair of a CMOS flip-flop circuit. The output of the potential detection circuit which is connected to each source of the transistor and is configured by a P-type MOSFET is connected to each source of a pair of P-type transistors of a CMOS flip-flop circuit.

In addition, the invention according to claim 44 is a control method for controlling a semiconductor integrated circuit according to claim 9, wherein
The output from each output node of the plurality of level conversion circuits is
The two or more pieces of parallel data are transferred outside as two or more pieces of parallel data, and each of the two or more pieces of parallel data is divided into a plurality of pieces in advance within a finite potential difference between the potential of the first power supply and the potential of the second power supply. Is transferred to the outside using the above voltage range.

Further, according to a forty-fifth aspect, in the method for controlling a semiconductor integrated circuit according to the forty-fourth aspect, the number of divisions of the finite potential difference is the same as the number of parallel data transfers.

According to a forty-sixth aspect of the present invention, in the semiconductor integrated circuit of the ninth aspect, the plurality of level conversion circuits include a first power supply and a potential different from the potential of the first power supply. And a second power supply having
A relatively large-capacity decoupling capacitor is connected between the first power supply and the second power supply. I do.

According to a forty-seventh aspect of the present invention, in the semiconductor integrated circuit according to the forty-sixth aspect, the first power supply and the second power supply are internal power supplies, and the first internal power supply and the second internal power supply are provided. In this configuration, a decoupling capacitor is connected between the power supply and the power supply.

In addition, in the invention according to claim 48, in the semiconductor integrated circuit according to claim 46, the first power supply and the second power supply are external power supplies, and the first external power supply and the second power supply are connected to each other. A number of decoupling capacitors equal to the number of level conversion circuits are connected to an external power supply, and each of the decoupling capacitors is connected to a node between the corresponding two level conversion circuits. is there.

Further, in the invention according to claim 49, in the semiconductor integrated circuit according to claim 9, the plurality of level conversion circuits are different from a first power supply and a potential of the first power supply. A level conversion circuit connected to the first power supply or a level conversion connected to the second power supply, among the plurality of level conversion circuits, disposed in series between the power supply and a second power supply having a potential; The output of the circuit is in an unused configuration.

The invention according to claim 50 is the semiconductor integrated circuit according to claim 49, wherein the number of the plurality of level conversion circuits is one of a level conversion circuit connected to the first power supply and a second power supply. , Except for the level conversion circuit connected to, the number is the same as the required number of parallel data.

[0065]

According to the above construction, in the level conversion circuit according to any one of claims 1 to 8, and 31 to 34, the charge is stored in the charge supply means, and the charge is discharged to the output node, and the output is output. Change the potential of the node.

In this case, if the capacitance value of the charge supply means (capacitor) is 1/10 of the parasitic capacitance value of the output node of the level conversion circuit, the output node of the level conversion circuit may be connected to the output node. The output amplitude value is level-converted to 1/10 of the input amplitude value.

Here, since the operation of the level conversion circuit is performed by discharging the charge supply means, there is no need to provide an internal power supply circuit as in the prior art, and therefore, unnecessary current consumption due to through current does not increase. .

Further, claims 9 to 28 and claim 44
In the invention according to claim 45, in the two level conversion circuits connected in series, the charge released from the output node that changes to the low potential side in one of the level conversion circuits becomes high potential in the other level conversion circuit. Since it is reused to increase the potential of the output node that changes to the negative side, power consumption can be reduced accordingly.

In particular, according to the present invention, the electric charge released from the output node changing to the low potential side is accumulated in the charge accumulating means, and the accumulated electric charge is raised to the potential rise of the output node changing to the high potential side. In the invention according to the twenty-fifth aspect, the output node itself changes to a low potential side in one level conversion circuit by using the output node itself as a charge storage means, and changes directly to the low potential side in the other level conversion circuit. Since the charge is reused by connecting to the output node, the charge storage means is not required.

Further, according to the present invention, a small capacity is created by increasing the number of serially connected level conversion circuits, and conversely, by increasing the number of parallelly connected level conversion circuits. Since a large capacitance is created and the effective capacitance can be electrically controlled, the amplitude distribution of the output is easily controlled.

In addition, according to the present invention, the level conversion circuit in which the degree of change of the output node with respect to time is large, for example, the level conversion circuit in charge of the least significant bit when the address is incremented. Is located close to the power supply line, the substrate bias voltage of the MOSFETs that make up the level conversion circuit is reduced, and the operation delay time is shortened.
The operation stability of the entire circuit is improved.

In addition, in the invention according to the thirty-eighth to forty-third aspects, the plurality of level conversion circuits are level conversion circuits having the same degree of change of the output node with respect to time, and are connected to the first power supply and the first power supply. And the second power supply, the level conversion circuit disposed between the first power supply and the second power supply, and the first power supply and the second power supply separately from the first power supply and the second power supply. The operating frequency can be made different from that of the level conversion circuit disposed between the two, and a large reduction in power consumption can be achieved.

Further, in the invention according to claim 41, in the level conversion circuit receiving the charge from the power supply, the charge is supplied from the power supply at a cycle that is an integral multiple of the cycle of the operation clock, so that the power consumption can be reduced. .

In addition, in the invention according to claim 42 and claim 43, a potential detection circuit constituted by an N-type MOSFET;
Since each of the potential detection circuits composed of P-type MOSFETs is used in a range where the amplification delay is small, the output potential (reference level) of the level conversion circuit can be detected with high sensitivity.

In addition, according to the inventions of claims 46 to 48, noise generated in the power supply line is provided by the large-capacity decoupling capacitor disposed between the high-potential power supply line and the low-potential power supply line. The impact of is less limited,
The operation stability of the semiconductor integrated circuit is enhanced.

Further, according to the inventions of claims 49 and 50, even if noise occurs in the power supply voltage or the ground line voltage, the effect is limited only to the level conversion circuit to which the power supply voltage or the ground line voltage is applied. Directly, and the effect of the noise does not appear on the output of the other intermediate level conversion circuit. Therefore, it is possible to output parallel data that is not affected by noise.

[0077]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic diagram of a circuit according to a first embodiment of the present invention. FIG. 1 shows an inverter type level conversion circuit which operates in synchronization with a clock signal. In the figure, Vin is an input, Vout is an output node, 2 and 3 are complementary clock signals CLK, XCLK, and Vcc are high-potential-side external power supply lines, and Vss is a low-potential-side power supply line and is constituted by a ground line. Is done. VM is a power supply line of an intermediate potential ((Vcc-Vss) / 2) between the high potential Vcc and the low potential Vss.

1a is a first capacitor,
It functions as first charge supply means for discharging the charged charge. Reference numeral 1b denotes a second capacitor as second charge supply means for discharging the similarly charged charge.

Reference numeral 9 denotes discharge means, which includes two PMOSs.
It comprises FETs 4 and 5 and two NMOSFETs 6 and 7. Reference numeral 11 denotes a precharge circuit, and one NM
An OSFET 8 and one PMOSFET 12 are provided. Further, 70 is a PMOSFET and 71 is an NMOSFET,
At the time of the ON operation, the corresponding power supply lines Vcc and Vss are connected to the corresponding capacitors 1a and 1b for charging.

The capacitance values CV of the two capacitors 1a and 1b are equal to each other.
out of the output node Vou
t and the precharge potential of the output node Vout
(Vcc / 2) and the capacitors 1a, 1b
A first potential (Vcc (for example, 3.
0V), Vss (0V)) and the potential difference between the potential of the output node Vout to be realized. For example, when the parasitic capacitance of the output is 3 pF, the capacitance value CV of the capacitor is 0.3 pF.

Next, a control method of the level conversion circuit of FIG. 1 will be described with reference to FIG.

The input Vin is a signal that changes to two different values as shown in FIG. In addition, PMOSFET 4 and NMOSFE
T7 is controlled by the input Vin and the other PMOSFETs 5, 12,
70 is a clock signal CLK (3) shown in FIG.
6, 8, and 71 are controlled by the inverted clock signal XCLK (2) shown in FIG.

That is, as shown in FIG. 2, in the half cycle (first period) α of the clock signal CLK (3), the power supply line VM of the intermediate potential is output by the two MOSFETs 8 and 12 of the precharge circuit 11. Connected to node Vout and output node Vout
Is precharged to an intermediate potential. Further, in this half cycle α, the PMOSFET 5 and the NMOSFET 6 of the discharging means 9 are further turned off.
FF and PMOSFET 70 and NMOSFET 71
N, the external power supply line Vcc on the high potential side becomes the first
The low-potential-side external power supply line Vss is connected to the second capacitor 1b, and the capacitors 1a and 1b are charged to a high potential and a low potential, respectively. Note that the capacitors 1a and 1b are charged during the period α (the same period as the first period). However, the charge may be output to the output nodes Vout and XVout, so that the charge may be performed before the output. It may be a period (second period) different from the precharge period of the output node.

Thereafter, in a half cycle (third period) β after the half cycle α of the clock signal CLK (3), the precharge by the precharge circuit 11 is stopped and the PMOSFE
Turn off T70 and NMOSFET 71 and set capacitor 1
a, 1b are stopped, and at the same time, the PMOS of the discharging circuit 9 is turned off.
The FET 5 and the NMOSFET 6 are turned on. In the discharge circuit 9,
Either the PMOSFET 5 or the NMOSFET 6 is turned on in response to the input Vin, and therefore, any one of the capacitors 1a,
The charge charged to 1b is discharged to the output node Vout via the discharge circuit 9.

Therefore, in this embodiment, the voltage level of the output node Vout is made small by the charge redistribution without power loss from the capacitors 1a and 1b.
Unlike in the past, it is not necessary to incorporate a low-voltage power supply voltage inside the chip, and a direct current like a DC current consumed by an extra internal power supply circuit increases current consumption, Excessive power consumption due to voltage drop can be avoided.

The source voltages of the input MOSFETs 4 and 7 are
Since the capacitors 1a and 1b hold a high voltage near the power supply voltage Vcc on the high side and a low voltage near the ground voltage Vss on the low side at the beginning of the operation, the input MOSF is effectively set.
The ETs 4 and 7 are easily turned on, so that the delay time td1 in the case of obtaining an output with a small amplitude does not increase as in the related art, and there is an effect that the delay time td2 of the present embodiment can be reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG.

This embodiment shows an embodiment applied to a level conversion circuit whose inputs and outputs are complementary. In FIG.
n and XVin are complementary inputs, and Vout and XVout are complementary output nodes. 9 'is a discharge means, which is composed of two NMOSFETs 13, 13 and two PMOSFETs arranged on the input side.
14 and 14. 11 'is a precharge means, which is constituted by a PMOSFET 17 disposed on the output side. Reference numerals 1a and 1b denote capacitors as charge supply means similar to the first embodiment. 19 is NMOSFET
, 20 are PMOSFETs, Vc is a power supply line of a predetermined potential, Vs is a power supply line of another potential lower than the power supply line Vc,
It is composed of a ground wire. The capacitor 1a is charged to the potential of the power supply line Vc, and the other capacitor 1b is charged to the potential of the power supply line Vs.

The two NMOSFETs 13 of the discharging means 9 ′
13 is a complementary output node V
out, XVout, and the two PMOSFETs
14 and 14 are capable of discharging the charge of the capacitor 1b to complementary output nodes Vout and XVout. The PMOSFET 17 of the precharge means 11 'short-circuits the complementary output nodes Vout and XVout to precharge the complementary output nodes Vout and XVout to the same potential.

The capacitors 1a and 1b have the same capacitance value CV.
out and XVout are the same, and the ratio of each of the parasitic capacitances to the output nodes Vout and XV
out Mutual output amplitude values and the capacitors 1a and 1b
Is set to be a ratio of the potential difference between each potential for charging the output node and the precharge potential of the output nodes Vout and XVout.

Next, a control method of the level conversion circuit of FIG. 3 will be described. Two NMOSFETs 1 on the input side of the discharge circuit 9 '
One of the PMOSFETs 3 and 13 and one of the two PMOSFETs 14 and 14 are controlled by one of the complementary inputs Vin and XVin, and the other NMOSFET 13 and the PMOSFET 14 are controlled by the remaining complementary inputs. The precharge circuit 11
The PMOSFET 17 and the PMOSFET 20 are connected to the clock signal CL.
K, and the NMOSFET 19 is controlled by the inverted clock signal XCLK. The complementary clock signals CLK and XCLK and the complementary inputs Vin and XVin are shown in FIG.

Next, the operation of the level conversion circuit shown in FIG. 3 will be described with reference to FIG.

In FIG. 5, during the first half period α of one cycle of the clock signal, that is, during the period when the complementary inputs Vin and XVin have the same value, the PMOSFET 1 of the precharge circuit 11 'is not changed.
7 turns ON, the complementary output nodes Vout and XVout are short-circuited and precharged to the same potential. In this half cycle α, the four MOSFETs 13 and 14 of the discharge circuit 9 ′
FF and NMOSFET 19 and PMOSFET 20 are ON
Then, the capacitor 1a is charged to the low potential of the low potential side power supply line Vs, and the capacitor 1b is charged to the high potential side power supply line Vs.
The high potential of c is charged.

Next, during the latter half cycle β of one cycle of the clock signal, that is, during the period when a predetermined potential difference appears between the complementary inputs Vin and XVin, the PMOSFET 1 of the precharge circuit 11 'is turned on.
7, the NMOSFET 19 and the PMOSFET 20 are turned off, the upper NMOSFET 13 and the lower PMOSFET 14 of the discharge circuit 9 'are turned on, and the charge of the capacitor 1a charged to a low potential is discharged to one output node Vout. At the same time, the charge of the capacitor 1a charged to a high potential is discharged to one output node XVout. As a result, outputs having the following potential difference (amplitude value) ΔV appear at the complementary output nodes Vout and XVout.

ΔV = 2 × Vcc (1 + CD / CV) CD: Complementary output nodes Vout, parasitic capacitance of XVout) Therefore, in this embodiment, as in the first embodiment, the capacitors 1a, 1b Output nodes Vout, XVout
Voltage level is small, the current consumption increases due to through current when a low-voltage power supply voltage is built in the chip as in the past, and extra power is generated due to the voltage drop in the internal power supply circuit. Consumption can be avoided.

(First Modification of Second Embodiment) FIG. 4 shows a level conversion circuit obtained by partially modifying the level conversion circuit of FIG. The level conversion circuit of FIG. 4 differs from the level conversion circuit of FIG. 3 in that a capacitor 1a charged to a low potential and a capacitor 1b charged to a high potential are provided, and only one capacitor 1 is used. A period in which one of the plate electrodes of the capacitor 1 is charged to the high potential of the power supply line Vc, the other plate electrode is charged to the low potential of the power supply line Vs, and a predetermined potential difference appears between the complementary inputs Vin and XVin. At β, each plate electrode of the capacitor 1 is connected to one of the complementary output nodes Vout and XVout.

According to this modification, the number of capacitors can be reduced from two to one as compared with the second embodiment, so that the layout area of the capacitors can be reduced by half.

(Second Modification of Second Embodiment) FIG. 6
(A) and (b) show a second modification of the level conversion circuit of FIG. In FIG. 3, instead of providing two capacitors 1a and 1b as charge supply means, only one capacitor 1 (charge supply means) is provided, and other charge supply means are high in FIG. In FIG. 4B, the power supply line Vcc is constituted by a low-potential power supply line Vss, and the two NMs of the discharging means 9 'are formed in accordance with the inputs Vin and XVin.
When one of the OSFETs 13 and 13 is turned on, the charge of the high potential power supply line Vcc and the low potential power supply
The ss charge is discharged to one of the complementary outputs Vout and XVout via the NMOSFET 13 which has been turned on. Other configurations are the same as those in FIG. 3, and thus description thereof will be omitted.

(Third Embodiment) FIG. 7 shows a semiconductor integrated circuit according to a third embodiment of the present invention, in which the complementary level conversion circuit shown in FIG. The complementary level conversion circuit of b) is arranged in the lower stage. The upper level conversion circuit includes two input gate MOSFETs 16
It consists of PMOSFET, and two MOSFs of the lower level conversion circuit
The ETs 15 and 15 are composed of NMOSFETs, and the MOSFET 18 constituting the precharge circuit is also composed of NMOSFETs.

Each of the capacitors 1a and 1b has a NM
The power supply line VM is connected to an intermediate potential power supply line VM via the OSFETs 20a and 20b. The intermediate potential of the power supply line VM is a high potential power supply line V
It is a potential (VM = (Vcc-Vss) / 2) of an intermediate value between the potential of cc and the potential of the low potential power supply line Vss. 2 above
NMOSFETs 20a and 20b are both inverted clock signals XC
Controlled by LK. In the figure, reference numeral 21 denotes an NMOSFET for making the potentials of the two capacitors 1a and 1b common, and is controlled by an inverted clock signal XCLK.

The other structures are the same as those shown in FIGS. 6A and 6B, and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

Next, a method of controlling the semiconductor integrated circuit will be described.

As shown in FIG. 8, the complementary inputs Vin1 and XVin1 of the upper level conversion circuit are input gate PMOSFETs 16,
It has a potential capable of completely turning on and off the PMOSFET 14, and has complementary inputs Vin2 and XVin2 of the lower level conversion circuit.
Also completely turns on the input gate PMOSFET 13 and PMOSFET 15
And a potential that can be turned off.

As shown in the figure, during the first half period α of one cycle of the clock signal, that is, during the period when the values of the complementary inputs are equal to each other, the complementary output nodes Vout1, XVout1, and Vout2 and XVout2 are PMOSFE
Equalized by turning on T 17 and NMOSFET 18. In this period α, the two NMOSFETs 20a, 20a, 2
By turning on 0b, both capacitors 1a and 1b are precharged to the intermediate potential by the power supply line VM of the intermediate potential.

Thereafter, a potential difference occurs between the complementary inputs during the second half period β of one cycle of the clock signal, that is, for example, the input XVin1 drops to the low potential Vss and the input Vin2
During the period when the potential of the output node X rises to the high potential Vcc, in the upper level conversion circuit, the high potential power supply line Vcc passes through the PMOSFET 16 controlled by the input XVin1 to one output node Xcc.
Vout1, the output node XVout1 rises to a high potential, and the other output node Vout1 is connected to the capacitor 1a via the PMOSFET 14 controlled by the input XVin1. The current Iu flows toward the capacitor 1a.

On the other hand, in the period β, in the lower level conversion circuit, the low potential power supply line Vss passes through the NMOSFET 13 on the side controlled by the input Vin2 to output one output node Vou.
t2, the output node Vout2 is connected to the low potential Vss.
At the same time, the other output node XVout2 is connected to the capacitor 1b via the NMOSFET 15 controlled by the input Vin2, and the current IL flows from the capacitor 1b toward the other output node XVout2. The output node XVout2 rises above the precharge potential in the period α.

Here, the electric charge charged to the capacitor 1a by the current Iu flowing from the output node Vout1 of the upper level conversion circuit is consequently changed to the output node XVou by the current IL from the capacitor 1b of the lower level conversion circuit.
Charged at t2, the charge is reused.

Therefore, in this embodiment, the charge can be reused by the two level conversion circuits, so that the power consumption can be further reduced.

The capacitance value C of each of the capacitors 1a and 1b
As in the first embodiment, V is the ratio of the parasitic capacitance value CD of the output node to the output amplitude value of the output node to be realized, the charging potential VM of each of the capacitors 1a and 1b, and the precharge of the output node. Potential difference from the potential (that is, about Vcc /
2) is set. For example, when the output amplitude value of the output node to be realized is Vcc / 10, CV:
CD is a ratio of 2:10.

(Modification of Third Embodiment) FIG. 9 shows a modification of the third embodiment. In FIG. 7, two capacitors 1a and 1b are used for storing a high potential side potential and a low potential side potential. Focusing on the plate electrode on the side connected to the ground instead of being provided for storage, each of the two plate electrodes of one capacitor 1 has an output node on the side that changes to the lower potential side of the upper level conversion circuit. And an output node of the lower level conversion circuit which changes to a higher potential side, and the respective potentials are stored. Therefore, since the number of capacitors can be reduced from two to one, the layout area of the capacitors can be reduced by half.

(Fourth Embodiment) FIG. 10 shows a fourth embodiment of the present invention. In the embodiment of FIG.
Although the ratio between the capacitance value CV of the capacitors a and 1b and the parasitic capacitance value CD of the output node is set to 2:10, the ratio is set to 1:10 to reduce the capacitance value CV of each of the capacitors 1a and 1b. The configuration is designed to reduce the layout area of the capacitors. Specifically, each capacitor 1
a, 1b and each output node before the short-circuit
cc / 2 is set to about Vcc which is twice as much as cc / 2.

That is, in FIG. 10, the charge supply means 700 surrounded by a broken line is composed of two capacitors 1a and 1b.
And four switches SW1 to SW4. As shown in FIGS. 11 and 12, the four switches SW1 to SW4 are controlled by complementary signals WCLK and XWCLK that change every period of the complementary clock signals CLK and XCLK.
In the period γ shown in FIG.
And turn off the other two switches W2 and SW4
On the other hand, in the subsequent period δ, the reverse operation is performed.

Therefore, in the period ε of a half cycle of the clock signal shown in FIG.
When the PMOSFET 14 controlled by 1 is turned on, one output node Vout1 (potential drop side) is connected to the capacitor 1a, and the potential of the capacitor 1a is brought close to the high potential of the power supply line Vcc on the high potential side. As one of the output nodes XVout2 (on the potential increasing side) is connected to the capacitor 1b by turning on the NMOSFET 15 on the side controlled by the input Vin2 of the lower level conversion circuit, the potential of the capacitor 1b is increased. Falls to near the low potential of the power supply line Vss on the low potential side. This state is maintained for the subsequent half period η of the clock signal.

Thereafter, the four switches SW1 to SW4
The output node Vout1 or XV on the side where the potential of the capacitor 1b drops in the upper level conversion circuit
connected to the output node Vout2 or XVout2 on the side where the potential of the capacitor 1b rises near the high potential of the power supply line Vcc on the high potential side and the other capacitor 1a rises in the lower level conversion circuit. And the potential of the capacitor 1a drops to near the low potential of the power supply line Vss on the low potential side.

Therefore, the potential difference between each of the capacitors 1a and 1b and the output node connected thereto before the short circuit can be set to about Vcc, so that each of the capacitors 1a and 1b can be set.
The ratio between the capacitance value CV of b and the parasitic capacitance value CD of the output node can be set as small as 1:10, and the layout area of each capacitor can be reduced.

(Modification of Fourth Embodiment) FIG. 13 shows a modification of the fourth embodiment.
This is an example in which 0 is modified. The charge supply means 701 in FIG.
One capacitor 1 and two switches S connecting the capacitor 1 to the upper level conversion circuit and the lower level conversion circuit
W1 and SW4. The two switches SW1,
SW4 is, as shown in FIG. 14, a complementary clock signal CL.
In the period α of the half cycle of K and XCLJ, the switch SW1 is turned on and the switch SW4 is turned off, and the operation is reversed in the other half period β.

Further, as shown in FIG. 15, the complementary inputs Vin2 and XVin1 of the lower level conversion circuit are changed into waveforms shifted by a half cycle with respect to the complementary inputs Vin1 and XVin1 of the upper level conversion circuit.

Therefore, as shown in FIG. 15, during the period α of the half cycle of the clock signal, the capacitor 1
When W1 is turned on, it is connected to the output node (Vout1 in the figure) of the complementary output nodes Vout1 and XVout1 of the upper level conversion circuit which drops in potential, and the high potential power supply line Vc
After the capacitor 1 has been charged to near the high potential, during a period β of a half cycle of the clock signal, the capacitor 1
4 is connected to the output node (XVout2 in the figure) of the complementary output nodes Vout2 and XVout2 of the lower level conversion circuit which rises in potential when turned on, and its capacitor 1
Is discharged to the output node XVout2, and the capacitor 1 drops to a potential near the low potential of the low potential power supply line Vss.

Therefore, in this modification, one capacitor 1 is alternately connected to an output node near the high potential Vcc and an output node near the low potential Vss every half cycle of the clock signal. The ratio between the capacitance value CV and the parasitic capacitance value CD of the output node can be set as small as 1:10, and the layout area of each capacitor can be reduced.

(Fifth Embodiment) Next, a semiconductor integrated circuit according to a fifth embodiment of the present invention will be described with reference to FIG.

In the semiconductor integrated circuit of FIG. 16, three complementary level conversion circuits of different types use a power supply Vcc and a ground line Vcc.
and ss are connected in series.

The middle level conversion circuit is the level conversion circuit shown in FIG. 3, the upper level conversion circuit is the level conversion circuit shown in FIG. 6A, and the lower level conversion circuit is the level conversion circuit shown in FIG. FIG. However, the MOSFETs of the level conversion circuit in the middle stage are all NMOSFETs 24, 25, 26
All the MOSFETs in the upper level conversion circuit are PMOS
The MOSFETs of the lower level conversion circuit are all composed of NMOSFETs 13, 15, and 18.

The capacitor 1c of the upper level conversion circuit and one of the two capacitors 1d and 1e of the middle level conversion circuit 1d are:
Power supply line 22 of high potential Vu via three NMOSFETs 21.
, And the other capacitor 1e of the middle level conversion circuit and the capacitor 1f of the upper level conversion circuit are connected to the low potential VL power supply line 23 via three NMOSFETs 27. .

The high potential Vu of the power supply line 22 is 3 (Vc
c−Vss) / 4 and the low potential VL of the power supply line 23
Is set to (Vcc-Vss) / 4.

PMOSFET 1 of the upper level conversion circuit
7. The NMOSFET 24 of the middle level conversion circuit and the NMOSFET 18 of the lower level conversion circuit respectively short-circuit two corresponding output nodes and precharge the two output nodes to the same potential. Functions as charging means. The four capacitors 1a to 1d constitute charge storage means, and the power supply lines Vu and VL of the intermediate potential respectively connect the capacitors 1a to 1d to the intermediate potentials VU and VL (potentials different from the output node precharge potential). ) Functions as a charging means. The precharge means, the charge storage means and the charge means constitute the charge amount change characteristic equalizing means according to the ninth aspect.

Further, the PMOSFET 1 of the upper level conversion circuit
4. The NMOSFET 25 of the middle level conversion circuit and the NMOSFET 15 of the lower level conversion circuit are each composed of a capacitor 1
a to 1d are output to corresponding output nodes Vout1, XVout1, V
out2, XVout2, Vout3, and XVout3 to form a charge redistribution means for redistributing the charge accumulated in each of the capacitors 1a to 1d to the output node.

Next, a method of controlling the semiconductor integrated circuit of this embodiment will be described. As shown in FIG. 18, the level converter in the middle stage operates in synchronization with complementary clock signals CLK and XCLK, NMOSFE in the period α of the half cycle of the signal
The complementary outputs VOUT2 and XVOUT2 are short-circuited by turning on T24, and these outputs are precharged to a substantially intermediate potential (1 / 2Vcc = Vc) between the low-potential power line 23 and the high-potential power line 22. At the same time, each of the capacitors 1b and 1c is charged to the potential of the power supply lines 22 and 23 on the high potential side and the low potential side, and the node of each of the capacitors CV1b and 1c is Complementary inputs Vin2, XVIN
2 are connected to complementary outputs Vout2 and XVout2, respectively, via NMOSFETs 25 and 26 which are controlled to be ON by 2.

Similarly, the upper level conversion circuit also has complementary outputs Vout1 and XVout1 during a period α of a half cycle of the clock signal.
Is precharged to an intermediate potential between the respective potentials at the time of its complementary output, and the capacitor 1a is charged to the potential Vu of the power supply line 22 on the high potential side.
The node A of the capacitor 1a and the power line V on the high potential side
cc are connected to the complementary outputs Vout1 and XVout1 via the PMOSFETs 16 and 14 on the side controlled to be ON by the complementary inputs Vin1 and XVin1, respectively.

Similarly, the lower level conversion circuit also outputs the complementary outputs Vout3 and XVou during the period α of the half cycle of the clock signal.
t3 is precharged to an intermediate potential between the respective potentials at the time of its complementary output, and both capacitors 1d are charged to the potential VL of the power supply line 23 on the low potential side, and thereafter the half cycle period β
Then, the node D of the capacitor 1d and the low potential side power supply line Vss are turned on by the complementary input Vin3 and XVin3, respectively.
Are connected to the complementary outputs Vout3 and XVout3 via the NMOSFETs 13 and 15 on the side controlled by.

The complementary inputs Vin2, XVin2 and Vin3, XVin3 of the middle and lower level conversion circuits are:
As shown in FIG. 17, after waiting at the level of the ground potential Vss,
After the input is confirmed, only one of the inputs is at high potential Vcc
On the other hand, the complementary inputs Vin1 and XVin1 of the upper level conversion circuit wait at the high potential Vcc level, and after the input is determined, only one of the inputs transitions to the ground potential Vss. With such a setting, it is possible to prevent a through current from flowing due to a short circuit between the high-potential power line Vcc, the two middle-potential power lines Vu and VL, and the low-potential power line Vss. It constitutes a through current prevention means.

The structure of the through current prevention means may be, for example, between point A and point A 'in FIG.
And point B ', between point C and point C', and between point D and point D
17, MOSFETs 21 are provided as shown in FIG. 17 so that complementary clock signals CLK and CLK are not turned on until one of the complementary inputs transitions to a potential lower than the threshold voltage of the input NMOSFET. XCLK (complementary inputs Vin1, XV
in1, Vin2, XVin2, Vin3, XVin3).

Therefore, in this embodiment, FIG.
As shown in the figure, in the period β of a half cycle of the clock signal, the electric charge discarded by the output node Vout1 or XVout1 on the lower side in the upper level conversion circuit becomes the output node Vout2 on the higher side in the middle level conversion circuit. Or XVou
The charge released from the output node Vout2 or XVout2 on the side where the potential is lowered in the middle level conversion circuit is used for the potential rise of t2, and the potential of the output node Vout3 or XVout3 on the side where the potential is raised in the lower level conversion circuit. Used for climbing. Therefore, only the upper level conversion circuit needs to supply the electric charge from the outside, and the remaining 2
There is no need for a new charge supply in the level conversion circuits,
Low power consumption is possible.

Here, a case in which n level conversion circuits are operated will be described by comparing the degree of reduction in power consumption obtained by the present embodiment with the above-described conventional example.

When the voltage level is stepped down using an internal power supply circuit as in the first prior art (Japanese Patent Laid-Open No. 4-115515), the power supply voltage is set to Vcc, the output current is set to IH, and the stepped down voltage is set to VH. The power consumption in the internal power supply circuit is n · IH ·
(Vcc−VH), and the power consumption of the n circuits is n · I
H · VH, the total power consumption Ptotal is Ptotal =
n · IH · Vcc.

A second conventional example (Japanese Patent Laid-Open No. 4-302463)
In the case where the voltage is reduced by operating n separately provided circuits in series as in Equation (3), the applied voltage per circuit is VCC / n, so that the total power consumption Ptotal is Ptotal = (VCC /
n · IH) · n + α = IH · Vcc + α. here,
The power consumption α is the power consumption due to the through current flowing when the voltage (Vcc−Vss) is divided by the resistance, and the through current IH
Always flows from the power supply to the ground terminal
It can be expressed by IH.Vcc. Therefore, the total power consumption Ptotal
Is Ptotal = 2 · IH · Vcc.

On the other hand, in the present invention, as shown in the equivalent circuit of FIG. 19, n (three in the figure) level conversion circuits 501 are circuits for charging and discharging the same charge, that is, a capacitor having a fluctuating potential. Are connected to each other only when the output of each of the level conversion circuits 501 is in a high impedance state, and only charges the capacitor of the level conversion circuit located at the uppermost stage. Of the plurality of level conversion circuits operate by reusing the charge from the level conversion circuit one stage above, so that the total power consumption Ptotal becomes Ptotal = IH.Vcc.

Therefore, as shown in FIG.
As in the second conventional example, the power consumption is １ ／ of that in the case where three level conversion circuits operate in series and involve a through current,
As compared with the first conventional example, the power consumption can be reduced by 1 / n compared to the power consumption caused when the voltage is dropped by the internal power supply circuit.

In this embodiment, three different types of complementary level conversion circuits are combined. However, when four or more stages are arranged in series, the level conversion circuit of the type arranged in the middle stage of FIG. Are further connected in series. In this case, an intermediate value ((Vcc + Vss) between the potential of the high potential external power supply line Vcc and the potential of the low potential external power supply line Vss.
The level conversion circuit that outputs a potential higher than s) / 2) from the output node is configured by a PMOSFET, and the level conversion circuit that outputs a low potential from the output node is configured by an NMOSFET. With this configuration, the voltage between the gate and the source of the MOSFET increases, and the operation can be stabilized.

FIG. 21 shows a circuit for generating the intermediate potentials Vu and VL. The intermediate potential generating circuit shown in FIG. 3 includes current mirror type comparators 28, 29, and 30 using the potentials divided by four resistors R1, R2, R3, and R4 as reference potentials, and these comparators 28. 30 comprises output MOSFETs 31 to 33 controlled by the outputs of.

Although the intermediate potential generating circuit is basically the same as the power supply circuit shown in FIG. 28 of the conventional example, the charge supply capability is significantly different from that of the conventional example, and the intermediate and lower level conversion circuits are used. Since the charge is reused, there is no need to supply a new charge. That is, the intermediate potential generating circuit shown in FIG. 21 does not need to be provided as a charge supply function, and is only required when the first operating point is determined, for example, when power is turned on. That is, unlike the conventional example, the output does not need to have a low resistance, and the device size of the intermediate potential generating circuit shown in FIG. 21 can be reduced. The through currents IDC2, IDC3, IDC3 shown in FIG.
The sum of DC4 and IDC5 can also be reduced to microamps or less. Further, as shown in FIG. 21, for example, the switches SW5, SW6, SW7, and SW8 are operated only when the power is turned on, or closed and operated only during a half cycle of the low period of the clock signal CLK, and are turned off at other times. Can be reduced.

(Sixth Embodiment) Next, a semiconductor integrated circuit according to a sixth embodiment of the present invention will be described with reference to FIG.

In this embodiment, the above-described charge supply means is not separately provided, and the charge accumulated at the output node is used by another level conversion circuit by using the parasitic capacitance of the output node of the level conversion circuit as the charge supply means. It is to be reused.

That is, as shown in the figure, the upper-stage complementary level conversion circuit is the level conversion circuit shown in FIG. 6A, and the lower-stage complementary level conversion circuit is the level conversion circuit shown in FIG. It has the same configuration as the circuit. The MOSFETs of the upper level conversion circuit are all composed of PMOSFETs 16, 14, and 17, and the MOSFETs of the lower level conversion circuit are all NMOS.
The FETs 13, 15, and 18 are provided.

The two PMOSFEs of the upper level conversion circuit
The power supply line VM at an intermediate potential is connected between T14 and T14 (point A in the figure) and between two NMOSFETs 15 and 15 of the lower level conversion circuit (point B in the figure). The intermediate potential VM of the power supply line VM is set to ((Vcc-Vss) / 2).

The PMOSFET 14 of the upper level conversion circuit
The NMOSFET 15 of the lower level conversion circuit includes an output node Vout1 or XVout1 (Vout2 or XVout2) that changes to a low potential side in one level conversion circuit and an output node Vout2 that changes to a high potential side in the other level conversion circuit.
Alternatively, by connecting and short-circuiting XVout2 (Vout1 or XVout1), charge redistribution means is configured to redistribute the charge released from the output node changing to the low potential side to the output node changing to the high potential side. . Other configurations are the same as those in FIG. 7, and the description thereof is omitted.

Next, a control method of the semiconductor integrated circuit of this embodiment will be described. As shown in FIG. 24, the clock signal CLK
When the PMOSFET 17 and the NMOSFET 18 are turned on during the half period α, the complementary output nodes Vout1, XVout1, Vout2, and XVout2 of each level conversion circuit are connected to the intermediate potential of the respective potentials at the time of the complementary output, that is, 3/4 Vcc potential and 1 /
Precharge to 4 Vcc potential.

Thereafter, during the period β of the remaining half cycle of the clock signal CLK, the output node Vout1 and XVout1 of the upper level conversion circuit, which are in the high impedance state due to the turning off of the PMOSFET 17, are connected to the output node on the side where the potential drops, , Output nodes Vout2 and XVou of the lower level conversion circuit
The output node on the side where the potential rises in t2 is connected to the PMOS on the side turned on by one of the complementary inputs Vin1 and XVin1, respectively.
Short-circuit through the NMOSFET 15 on the side turned on by the FET 14 and one of the complementary inputs Vin2 and XVin2 to the intermediate potential of the power supply line Vc, and the output node Vout1 or the remaining output node of the upper level conversion circuit. XVout1 is connected to the high-potential power supply line Vcc, and the remaining output node Vout2 or XVout2 of the lower level conversion circuit is connected to the low-potential power supply line Vss.

As shown in FIG. 24, the complementary inputs Vin1 and XVin1 of the upper level conversion circuit wait at the level of the ground potential Vss, and only one of the inputs has a low potential after the input is determined. Vss, while the complementary inputs Vin2 and XVin of the lower level conversion circuit are set.
2 is set to wait at the low potential Vss level, and only one of the inputs is changed to the high potential Vcc after the input is determined. With such setting, the high potential power supply line Vcc and This prevents a through current from flowing due to a short circuit with the low potential power supply line Vss.

In the case of another configuration, for example, between the nodes A and B, between the node E and the power supply line Vcc, and between the node F and the ground power supply Vss in FIG.
As shown in FIG. 23, each of the MOSFETs 50, 51 and 52 can be replaced by a configuration in which one of the complementary inputs is controlled so as not to turn on until one of the complementary inputs transitions to a potential lower than the threshold voltage of the input MOSFET. .

Therefore, in this embodiment, FIG.
As can be seen, the output node V of the upper level conversion circuit
out1 and XVout1, the electric charge released from the output node on the side where the potential drops is transferred to the output node Vou of the lower level conversion circuit
Since it can be reused for the output node on the side where the potential increases among t2 and XVout2, low power consumption can be achieved.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described with reference to FIG.

This embodiment is an extension of the sixth embodiment. Two upper level converters and two lower level converters in FIG. 22 provide a total of four level converters. A semiconductor integrated circuit is formed by a circuit.

A first intermediate potential Vu (Vu = 3 (Vc-Vss) / Vs) is provided between the first and second level conversion circuits.
4), a second intermediate potential Vc (Vc = 2 (Vc−Vs) is applied between the second and third level conversion circuits.
s) / 4) and a third intermediate potential VL (Vc = (Vc) between the third and fourth level conversion circuits.
A power supply line 57 of (c-Vss) / 4) is arranged.

The other configuration is the same as that of FIG. 22, and the description is omitted.

In this embodiment, as shown in FIG. 26, four output line pairs having an amplitude of Vcc / 4 operate while reusing electric charges with each other. Accordingly, out of the four level conversion circuits, only the uppermost level conversion circuit connected to the power supply side supplies the electric charge necessary for the potential fluctuation of Vcc / 8 from the external power supply line Vcc, and the remaining three It can be understood that the level conversion circuit operates with the reused charge.

In the sixth and seventh embodiments, the output node (output wiring) has the same parasitic capacitance and the potential for turning on only one of the transistors to which the complementary inputs are connected is relatively low. For example, a data transfer system that operates on a 16, 32, 64, or 128 bit before being input to a parallel-to-serial conversion circuit, for example, a memory circuit that operates on a synchronization signal can be used in a circuit that can be easily held. If the circuit is formed in units of 4 bits or 8 bits and the circuit is applied to a data system circuit constituting the unit, the power consumption of the memory can be reduced.

(Eighth Embodiment) FIG. 31 shows an eighth embodiment of the present invention. This figure shows, for example, the discharge circuit 9 'of FIG.
And a semiconductor integrated circuit provided with a plurality of blocks showing the main configuration of a level conversion circuit including precharge means 11 '. As shown in FIG. 32, each block has an input pair IDi, XIDi and an output pair Di, XD
i, and level setting units H and L for each output pair. F denotes a functional (function) circuit, which is a switch composed of transistors. Specifically, for example, when attention is paid to the output D, the level of one Di of the input pair is compared with the other XDi in a pair relationship. And if it is "High",
It has a function of connecting the output D to the level setting unit H and connecting the output D to the level setting unit L if it is “Low”. EQ is a signal for equalizing the output line pair. FIG. 33 shows an operation table of each block.

Input pair IDi, XID of each block
i corresponds to the complementary inputs Vin and XVin in FIG. 25, and the output pair parts Di and XDi correspond to the complementary output nodes Vout and X in FIG.
Vout, the level setting units H and L are the intermediate potentials VU, VC and VL of the same figure, and the functional circuit F is the MOSFET 14 and the same of the same figure.
15 respectively.

In the seventh embodiment shown in FIG. 25, a plurality of level conversion circuits are connected to the power supply Vc as schematically shown in FIG.
c and the ground line Vss, and in operation, one of the output line pairs of the adjacent level conversion circuit is short-circuited during one of the first periods of one cycle of the system clock, and the remaining While the output line pair of each level conversion circuit is repeatedly short-circuited in the second period, in the present embodiment, as shown in FIG. 35, between the power supply Vcc and the ground line Vss. A plurality of groups (two in FIG. 31 and FIG. 35) in which respective blocks are connected in parallel are provided, and these groups and a single level conversion circuit are connected between a power supply Vcc and a ground line Vss.

According to the structure of this embodiment, by connecting a plurality of blocks in parallel, as shown in the equivalent circuit of FIG. 35, the total capacitance of the output line pairs of the respective blocks connected in parallel is Cd0 to Cdn. Is n × Cdn. On the other hand, the total capacity of the group not connected in parallel is 1 × Cdn. Therefore, in the configuration of FIG. 31, the potential of the output line pair of each block is determined by the capacitance ratio of the group, and an amplitude of 1: n 70 is obtained as shown in FIG. The resulting blocks will operate at low amplitude, and individual blocks not connected in parallel will operate at high amplitude.

In the third embodiment shown in FIGS. 7 and 8, it is necessary to separately provide a capacitance smaller than the output line pair in a layout or a process, but in the present embodiment, It is only necessary to increase the number of blocks connected in series as a method of producing a small capacity, and to increase the number of parallel connections of the blocks as a method of producing a large capacity. That is, it is possible to control the amplitude distribution of the output by electrically controlling the effective capacitance.

(Modification of Eighth Embodiment) FIGS. 37 and 3
8 shows a modification of the eighth embodiment. In the eighth embodiment, instead of arranging two groups vertically and arranging a single block between them, conversely, arranging two single blocks vertically and arranging a group therebetween. It is configured. The operation in this case has the waveform shown in FIG.

(Ninth Embodiment) FIG. 39 shows a ninth embodiment of the present invention. In the figure, a plurality of blocks are connected in series, and a first, a second and a third down converter 1 are connected in a chip between an external power supply Vcc and a ground line potential Vss.
01 to 103, and an internal power supply line 104 of high potential Vup is provided between the first and second down converters 101 and 102.
And the second and third downconverters 10
2 and 103, an internal power supply line 105 of low potential Vlw is taken out, and decoupling capacitors 106 and 106 having a relatively large capacity are connected between the internal power supply lines 104 and 105.
This is a configuration in which the components are arranged. However, as shown in FIG. 40, while the input of the circuit has a full amplitude (Vcc-Vss), the output amplitude has a plurality of potentials between the internally generated high potential Vup and the low potential Vlw. The value is equally divided (six equally in the figure).

In this embodiment, the internally generated high potential Vup using three down converters 101 to 103 is used.
Since the stability of the low potential Vlw is enhanced by the large-capacity decoupling capacitors 106, 106, the bounce due to the noise of the external power supply and the ground line is compared with the case where the low potential Vlw is directly connected between the external power supply and the ground line. Problem can be solved.

In this embodiment, the external power supply voltage is reduced by using three down converters 101 to 103.
Of course, the same can be applied to a case where the external power supply voltage is boosted and the voltage is used as the internal power supply voltage.

(First Modification of Ninth Embodiment) FIG. 56 shows a first modification of the ninth embodiment of the present invention. The ninth
In this embodiment, two decoupling capacitors 106 and 106 are arranged between the internal power supply line 104 of the high potential Vup and the internal power supply line 105 of the low potential Vlw. When an external power supply line and a ground line are directly connected to a plurality of blocks, the same number of decoupling capacitors 106 ', 106'... Are connected in series, and the respective decoupling capacitors 106 'are connected to nodes A, B,... C between the blocks.

Therefore, in this embodiment, as shown in FIG. 57, even if noises of values .DELTA.V1 and .DELTA.V2 occur in the voltage Vcc of the external power supply, these noises are divided by the decoupling capacitors 106 '. .., And only low-valued noise of ΔV1 / n and ΔV2 / n reduced by the number (n) of decoupling capacitors 106 ′... The problem can be solved even better.

(Second Modification of Ninth Embodiment) FIG. 58 shows a second modification of the ninth embodiment of the present invention. The ninth
In the embodiment, instead of suppressing the influence of noise of the external power supply by the decoupling capacitor 106, in the present modification, a plurality of blocks connected in series are directly connected to the external power supply line and the ground line. The output of the block affected by the noise of the external power supply line and the ground line is not used as a signal.

That is, in the figure, the number of a plurality of blocks connected in series is the required number of parallel data (for example, 8
Bit), the output of the uppermost block to which the power supply Vcc is applied and the output of the lowermost block connected to the ground line of the voltage Vs (0V). Is a configuration not used as the parallel data.

Therefore, in this modification, as shown in FIG. 59, even if noise occurs in the power supply voltage Vcc or the ground line voltage Vss, only the uppermost block and the lowermost block are directly affected by noise, and Since the influence of the noise does not appear on the output of the other intermediate block, parallel data can be output without being affected by the noise.

(Tenth Embodiment) FIG. 41 shows a tenth embodiment of the present invention.
0 shows an example. In the figure, the power supply Vcc and the ground line (first
Bit 0 (the least significant bit (L)) is supplied to the plurality of level conversion circuits connected in series between the power supply and the second power supply.
SB)), the most significant bit (MSB) is allocated to the highest level conversion circuit whose output line is directly connected to the power supply line. Has adopted.

That is, in this embodiment, for example, the substrate bias voltage Vbs (Vbs = Vcc-Vb) of the two MOSFETs 14 constituting the charge redistribution means in FIG. 25 can be seen from FIGS. 42 and 43. 42, the more the output potential is located far from the power supply Vcc, that is, the waveform 3 is larger than the waveform 1 in FIG.
43B, and the operation delay time of the MOSFET 14 increases as shown in FIG.
As a configuration in which the level conversion circuit constituting the least significant bit LSB is directly connected to the power supply line, the delay time of the uppermost level conversion circuit is limited to the minimum among all the level conversion circuits.

Therefore, in this embodiment, for example, when the address is incremented, the least significant bit changes most frequently, and the frequency of the change decreases as the address shifts to the upper bit. , The operation stability of the entire circuit can be improved, and the operation stability of the entire circuit can be improved.

(Eleventh Embodiment) FIG. 44 shows a first embodiment of the present invention.
1 shows an embodiment. The figure is used when a memory and a graphic controller are connected by N bit lines. For example, a super-multiple bit of 512 bits is divided into 8 bits, and the whole is divided into one group to form a group. It is divided into 64 groups. In this case, when one data is expressed by eight digits (8 bits), the same digit of the four data is in the same group.

FIG. 45 shows a frequency divider used to drive the super-multiple bits. The frequency divider shown in the figure is formed by cascade-connecting a plurality of (four in the figure) D-latch circuits 107... OT-1 and OT-2 each having a frequency doubled for each stage with respect to the frequency of the input IN. OT-2, OT-3, OT-4 ... are output. The output OT-1 of the frequency divider is used as an operation signal for a group in which 8 bits of the least significant bit LSB are collected, and the output OT-2 is for a group in which 8 bits one bit higher than the least significant bit LSB are collected. , And the output OT-3 is sequentially used as an operation signal for a group in which 8 higher-order bits are collected.

Therefore, in this embodiment, the operating frequency differs for each group, and the set group of the most significant bits that hardly changes operates only at the frequency of 1/64 of the system clock. In addition, as the number n of groups increases, the power consumption ratio with the conventional one increases (n: 2), and a great reduction in power consumption is possible.

In the present embodiment, the number of bits belonging to the same group is the same for each group, but may be different.

(Twelfth Embodiment) FIG. 48 shows the first embodiment of the present invention.
2 shows an embodiment. This figure shows the clock CL of FIG.
K is the first clock CLK1, and a P-type MOSF
A P-type MOSFET 121 is separately arranged between the ET 16 and the power supply Vcc, and the MOSFET 121 is controlled by the second clock CLK2 via the inverter 122. Other configurations are
Since the configuration is the same as that of FIG. 25, the same portions are denoted by the same reference numerals and description thereof will be omitted.

The second clock CLK2 is the first clock CLK2.
The frequency divider having the D-latch circuit 107 shown in FIG. 45 has a frequency twice as high as that of the clock CLK1 and generates the second clock CLK2.

Therefore, in this embodiment, FIG.
As shown in (b), the charge Q1 is not supplied from the power supply Vcc to the level conversion circuit most connected to the power supply Vcc side every cycle, but is supplied in two cycles as shown in FIGS. Once, the electric charge Q2 is supplied from the power supply. The electric charge Q2 supplied from the power supply Vcc is indicated by hatching in FIGS. As a result, FIG. 49 and FIG.
Then, for example, the power supply is connected during a period of t = T1, and the next t = T2
During the period of, the connection to the power supply Vcc is stopped.
The total charge in the cycle is as follows.

(Q1 + Q1)> Q2 + “0” (where, Q2 = 1.5 × Q1) As can be seen from the above equation, low power consumption can be achieved in this embodiment. Of course, as can be seen from the operation waveform, when no charge is supplied, the amplitude value is small. However, since the differential output line pair is used, a high margin can be secured.

(Thirteenth Embodiment) FIGS. 51 and 52 show a thirteenth embodiment of the present invention. In the semiconductor integrated circuit of FIG. 25, four level conversion circuits are arranged in series between a power supply and a ground line, and FIG. 25 shows a semiconductor integrated circuit in which the number of level conversion circuits arranged in series is eight. Circuit. As described in the seventh embodiment of FIG. 25, the output of each level conversion circuit is different and has eight reference levels between the potential level of the power supply and the ground level. In FIG. 52,
Reference numeral 150 denotes a potential detection circuit (potential detection means) constituted by an N-type MOSFET which receives an output line pair of a level conversion circuit as a driver, and 151 denotes a potential detection circuit (potential detection means) constituted by a P-type MOSFET. ). As shown in FIG. 53, the N-type potential detection circuit 150
a is composed of an N-type MOSFET and a P-type potential detection circuit 15
1, as shown in FIG. 54, the input gate section 151a is formed of an N-type MOSFET.

The potential detection circuit 150 composed of the N-type MOSFET has a precharge potential at the output node of the corresponding level conversion circuit ranging from an intermediate potential between the potential of the power supply Vcc and the ground potential to the potential of the power supply Vcc. Responsible for the input level of
The input level from the intermediate potential to the ground potential is a P-type
The potential detection circuit 151 composed of a MOSFET is in charge. The output of the potential detecting means 150 composed of the N-type MOSFET is supplied to each source 150d of the N-type pair transistor 150c of the CMOS flip-flop circuit 150b.
And a potential detection circuit 1 composed of a P-type MOSFET
The output of 51 is a CMOS flip-flop circuit 15
1b is connected to the source 151d of the P-type paired transistor 151c.

FIG. 55 shows the N-type and P-type with respect to the input potential.
FIG. 4 shows the amplification delay of each potential detection circuit composed of a MOSFET of the MOSFET type. In the potential detection circuit 150 composed of an N-type MOSFET, the amplification delay does not change so much from the power supply voltage Vcc to 1/2 Vcc, but when it becomes lower than that, the delay rapidly increases. The reason for this is that the difference between the threshold voltage of the N-type MOSFET at the input portion and the threshold voltage of the N-type MOSFET becomes small, and the MOSFET does not turn on sufficiently. On the other hand, in the potential detection circuit 151 composed of a P-type MOSFET, on the contrary, the voltage is sufficiently turned on between 1/2 Vcc and Vss.

Therefore, in this embodiment, the output potential (reference level) of the corresponding level conversion circuit (driver) is used by using the potential detection circuit within a range where the amplification delay is small.
A highly sensitive potential detection circuit can be provided in the vicinity.

As can be seen from FIGS. 51 and 52, N
Vss ~ 1/1 /
In the level conversion circuit composed of a P-type MOSFET, it is used between 1/2 Vcc and Vcc, while in the potential detection circuit composed of an N-type MOSFET, it is used in a voltage of 1/2 Vcc.
It is used between Vcc and Vcc, and is used between Vss and 1/2 Vcc in a potential detection circuit composed of a P-type MOSFET to have a complementary relationship.

[0188]

As described above, according to the level conversion circuit and the control method thereof according to the present invention, the electric charge is supplied to the electric charge supply means such as the capacitor. By accumulating and redistributing the accumulated charge to the output node of the level conversion circuit, the level conversion is performed, so that the internal power supply circuit (down converter) as in the related art is unnecessary, and the level is reduced without passing through current. Conversion can be performed, and power consumption can be reduced by eliminating unnecessary power consumption.

According to the semiconductor integrated circuit and the control method thereof according to the ninth to twenty-eighth, twenty-fourth, and forty-fifth aspects, the two level conversion circuits mutually transfer one of the charges emitted by the other. Is used for the potential rise change of the level conversion circuit, so that even a semiconductor integrated circuit composed of a number of level conversion circuits can operate all the level conversion circuits with only the current consumption for operating one level conversion circuit As a result, multi-bit small-amplitude data transfer can be performed with only one bit of current consumption, and power consumption can be effectively reduced, and its practical effect is extremely large.

In particular, according to the semiconductor integrated circuit of the seventeenth aspect, there is an effect that the capacitance value of the charge storage means can be halved compared to the semiconductor integrated circuit of the fifteenth aspect.

Furthermore, according to the semiconductor integrated circuit of the twenty-fifth aspect, the output node that changes to the low potential side is directly connected to the output node that changes to the high potential side by another level conversion circuit to recharge the electric charge. Since the charge storage device is used, the charge storage means becomes unnecessary, and the layout area can be reduced and the price can be reduced accordingly.

In addition, according to the twenty-ninth and thirty-third aspects of the present invention, the effective capacitance can be electrically controlled by appropriately setting the number of series-connected or parallel-connected level conversion circuits. The distribution can be easily controlled.

Further, according to the inventions of claims 35 to 37, the level conversion circuit having a large degree of change of the output node with respect to time is arranged at a position close to the power supply line, so that the level conversion circuit is constituted. The operation delay time can be reduced by limiting the substrate bias voltage of the MOSFET to a small value, and the operation stability of the entire circuit can be improved.

In addition, according to the thirty-eighth to forty-seventh aspects of the present invention, a plurality of level conversion circuits are connected to each other by the same level conversion circuit having the same degree of change of the output node with respect to time. And a second power supply, a level conversion circuit disposed between the first power supply and the second power supply, and a first power supply and a second power supply separately from the first power supply and the second power supply. The operation can be performed with different operation frequencies between the level conversion circuit and the level conversion circuit disposed between the two, and power consumption can be reduced.

According to the forty-first aspect, in the level conversion circuit receiving the charge from the power supply, the charge is supplied from the power supply at a cycle that is an integral multiple of the cycle of the operation clock. Is possible.

Further, according to the inventions of claims 42 and 43, a potential detection circuit composed of an N-type MOSFET and a potential detection circuit composed of a P-type MOSFET have a small amplification delay. Since it is used in the range, the output potential (reference level) of the level conversion circuit can be detected with high sensitivity.

In addition, according to the present invention, the large-capacity decoupling capacitor disposed between the high-potential power supply line and the low-potential power supply line provides
Since the influence of noise generated on the power supply line is limited to a small extent, the operation stability of the semiconductor integrated circuit can be improved.

Furthermore, according to the inventions of claims 49 and 50, even if noise occurs in the power supply voltage or the ground line voltage, the output of the level conversion circuit affected by the noise is not used. Therefore, it is possible to satisfactorily output the outputs of a plurality of level conversion circuits that are not affected by the output as parallel data.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a level conversion circuit according to a first embodiment.

FIG. 2 is an explanatory diagram of an operation of the level conversion circuit according to the first embodiment.

FIG. 3 is a diagram illustrating a level conversion circuit according to a second embodiment.

FIG. 4 is a diagram illustrating a modification of the level conversion circuit according to the second embodiment.

FIG. 5 is an explanatory diagram of an operation of the level conversion circuit according to the second embodiment.

FIG. 6 is a diagram illustrating another modification of the level conversion circuit according to the second embodiment.

FIG. 7 is a diagram illustrating a semiconductor integrated circuit according to a third embodiment;

FIG. 8 is an explanatory diagram of an operation of the semiconductor integrated circuit according to the third embodiment.

FIG. 9 is a diagram showing another modification in which a capacitor of the semiconductor integrated circuit according to the third embodiment is shared.

FIG. 10 is a diagram illustrating a semiconductor integrated circuit according to a fourth embodiment.

FIG. 11 is a diagram illustrating control of a switch of the semiconductor integrated circuit according to the fourth embodiment.

FIG. 12 is an explanatory diagram of an operation of the semiconductor integrated circuit according to the fourth embodiment.

FIG. 13 is a diagram illustrating a modification of the semiconductor integrated circuit according to the fourth embodiment;

FIG. 14 is a diagram illustrating switch control in a modification of the semiconductor integrated circuit of the fourth embodiment.

FIG. 15 is an explanatory diagram of an operation of a modification of the semiconductor integrated circuit of the fourth embodiment.

FIG. 16 is a diagram illustrating a semiconductor integrated circuit according to a fifth embodiment.

FIG. 17 is a diagram showing a circuit added to the semiconductor integrated circuit of the fifth embodiment.

FIG. 18 is an explanatory diagram of the operation of the semiconductor integrated circuit according to the fifth embodiment.

FIG. 19 is a diagram illustrating an equivalent circuit of a semiconductor integrated circuit according to a fifth embodiment.

FIG. 20 is a diagram showing the effect of the fifth embodiment.

FIG. 21 is a configuration diagram of an internal power supply circuit according to a fifth embodiment.

FIG. 22 is a diagram illustrating a semiconductor integrated circuit according to a sixth embodiment.

FIG. 23 is a diagram showing a circuit added to the semiconductor integrated circuit of the sixth embodiment.

FIG. 24 is an explanatory diagram of an operation of the semiconductor integrated circuit according to the sixth embodiment.

FIG. 25 is a diagram illustrating a semiconductor integrated circuit according to a seventh embodiment.

FIG. 26 is an explanatory diagram of the operation of the semiconductor integrated circuit according to the seventh embodiment.

FIG. 27 is a diagram illustrating the configuration and operation of a level conversion circuit according to a first conventional example.

FIG. 28 is a configuration diagram of a conventional internal power supply circuit.

FIG. 29 is a diagram illustrating the configuration and operation of a level conversion circuit according to a second conventional example.

FIG. 30 is a diagram showing an equivalent circuit of the level conversion circuit of the second conventional example.

FIG. 31 is a circuit diagram showing an eighth embodiment.

FIG. 32 is a block diagram of a main part of the level conversion circuit.

FIG. 33 is an operation diagram of the level conversion circuit of FIG. 32;

FIG. 34 is an explanatory diagram in the case where level conversion circuits are connected in series.

FIG. 35 is a diagram showing an equivalent circuit of the circuit of FIG. 31;

FIG. 36 is a diagram showing operation waveforms of the eighth embodiment and its modification.

FIG. 37 is a circuit diagram showing a modification of the eighth embodiment.

FIG. 38 is a circuit diagram showing an equivalent circuit of a circuit according to a modification of the eighth embodiment.

FIG. 39 is a circuit diagram showing a ninth embodiment.

FIG. 40 is a diagram showing operation waveforms of the circuit of the ninth embodiment.

FIG. 41 is an explanatory diagram of a circuit according to a tenth embodiment.

FIG. 42 is an explanatory diagram of the operation of the circuit according to the tenth embodiment.

FIG. 43 is a diagram illustrating characteristics of an operation delay time of a MOSFET.

FIG. 44 is a diagram showing a circuit according to an eleventh embodiment.

FIG. 45 is a diagram illustrating a configuration of a frequency divider.

FIG. 46 is a diagram showing operating frequencies of each group in the eleventh embodiment.

FIG. 47 is a diagram showing effects of the eleventh embodiment.

FIG. 48 is a diagram showing a circuit according to a twelfth embodiment.

FIG. 49 is an explanatory diagram of the operation of the twelfth embodiment.

FIG. 50 is a comparison diagram of the operation of the twelfth embodiment and the operation of the seventh embodiment.

FIG. 51 is a diagram showing a main part of a circuit according to a thirteenth embodiment.

FIG. 52 is a diagram illustrating an overall configuration of a circuit according to a thirteenth embodiment.

FIG. 53 is a diagram showing an internal configuration of a potential detection circuit composed of an N-type MOSFET.

FIG. 54 is a diagram showing an internal configuration of a potential detection circuit composed of a P-type MOSFET.

FIG. 55 is a diagram showing operation delay characteristics of an N-type MOSFET and a P-type MOSFET.

FIG. 56 is a diagram showing an overall configuration of a circuit according to a first modification of the ninth embodiment;

FIG. 57 is an explanatory diagram of an operation of a first modification of the ninth embodiment.

FIG. 58 is a diagram illustrating an overall configuration of a circuit according to a second modification of the ninth embodiment;

FIG. 59 is an explanatory diagram of an operation of a second modification of the ninth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Capacitor (charge supply means) 2, 3 Complementary clock signal 4, 7, 13, 16 Input gate 9 Discharge means 11 Precharge circuit 21, 27 Complementary input 5, 6 Connect capacitor to output
MOSFET 70, 71 MOSFET for charging / discharging a capacitor 17, 18 Equalizing transistor 106, 106 'Decoupling capacitor 107 D-latch circuit 150 Potential detection circuit composed of N-type MOSFET 151 Potential detection circuit composed of P-type MOSFET

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-124120 (JP, A) JP-A-2-244817 (JP, A) JP-A-2-216910 (JP, A) JP-A-2- 1615 (JP, A) JP-A-1-256213 (JP, A) JP-A-62-53517 (JP, A) JP-A-56-34233 (JP, A) JP-A-63-116517 (JP, A) JP-A-2-216910 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 19/00 G11C 7/00

Claims (50)

(57) [Claims] 1. A signal which changes to two different values as an input, operates in synchronization with a clock signal, converts an amplitude value of the input signal into another amplitude value, and outputs it from a single output node. An inverter type level conversion circuit, wherein first charge supply means is precharged to a first potential;
A second charge supply unit that is precharged to a second potential different from the first potential, and either one of the two charge supply units is selected according to the input signal, and the selected charge supply unit is selected. Discharging means for discharging the charge accumulated in the output node to the output node. 2. A signal which changes to two different values as an input, operates in synchronization with a clock signal, converts an amplitude value of the input signal into another amplitude value, and outputs the converted value from two output nodes. Complementary level conversion circuits, wherein first charge supply means is precharged to a first potential, and second charge supply means is precharged to a second potential different from the first potential. And the first signal according to the input signal.
Discharging means for discharging the charge stored in the charge supply means to one of the two output nodes and discharging the charge stored in the second charge supply means to the other output node. A level conversion circuit characterized in that: 3. A precharge circuit for precharging an output node to a third potential between a first potential of the first charge supply means and a second potential of the second charge supply means. 3. The level conversion circuit according to claim 1, wherein: 4. The level conversion circuit according to claim 3, wherein in the complementary level conversion circuit, the precharge circuit short-circuits two output nodes. 5. An output node is precharged to a third potential by a precharge circuit during a first period within one cycle of the clock signal, and a first potential is supplied to the output node during a second period within one cycle of the clock signal. The charge supply means and the second charge supply means are precharged to a first potential and a second potential, respectively, and a third potential after the first period and the second period within one cycle of the clock signal. 5. The control method according to claim 3, wherein the charge precharged to the charge supply means by the discharge means is discharged to the output node during the period. 6. The level conversion circuit according to claim 2, wherein the first charge supply means or the second charge supply means is constituted by a high-potential power supply line. 7. The level conversion circuit according to claim 2, wherein the first charge supply means or the second charge supply means is constituted by a low potential power supply line. 8. The charge supply means is constituted by a capacitor, and a ratio of a capacitance value of the capacitor to a parasitic capacitance value of an output node is a potential of an output node to be realized and a precharge potential of the output node. The capacitance value is set so as to be a ratio of a potential difference between the first potential and the potential of the output node to a potential difference between the first potential, which is a precharge potential of the capacitor, and a potential of the output node. 8. The level conversion circuit according to 1, 2, 3, 5, 6, or 7, or a control method thereof. 9. A level conversion circuit that receives a signal that changes to two different values as an input, operates in synchronization with a clock signal, converts an amplitude value of the input signal to another amplitude value, and outputs the converted value from an output node. A charge change characteristic in which two of the plurality of level conversion circuits move in opposite directions in the charge at the output node and have the same absolute value of the charge with respect to time. And a charge redistribution means for transferring charges between two level change circuits having the same charge amount change characteristics. Integrated circuit. 10. The semiconductor integrated circuit according to claim 9, wherein each of the plurality of level conversion circuits is a complementary level conversion circuit having two output nodes whose outputs are complementary. 11. The level conversion circuit according to claim 6, wherein:
8. A level conversion circuit according to claim 7, wherein said two level conversion circuits are connected in series between a high-potential power line and a low-potential power line. The semiconductor integrated circuit according to claim 10, wherein the semiconductor integrated circuit is arranged. 12. The plurality of level conversion circuits according to claim 2,
7. A level conversion circuit according to claim 6, wherein the level conversion circuit comprises one or more level conversion circuits, one level conversion circuit according to claim 6, and one level conversion circuit according to claim 7. 11. The semiconductor integrated circuit according to claim 10, wherein the semiconductor integrated circuit is arranged in series between a power supply line having a potential and a power supply line having a low potential. 13. A transistor of a level conversion circuit which outputs a higher potential from an output node as compared with a potential of an intermediate value between a potential of a high potential power supply line and a potential of a low potential power supply line is a P-type MOSFET. The transistor of the level conversion circuit that outputs a low potential from the output node is an N-type MOSFET.
12. The method according to claim 10, wherein
3. The semiconductor integrated circuit according to item 2. 14. The charge amount changing characteristic equalizing means includes: a precharge means for precharging two output nodes having substantially the same parasitic capacitance value to the same potential; a charge accumulating means for accumulating electric charge; 14. The semiconductor integrated circuit according to claim 10, further comprising charging means for charging said means to a potential different from said predetermined potential. 15. The semiconductor integrated circuit according to claim 14, wherein said charging means charges said charge accumulating means to a potential between respective precharge potentials of said two level conversion circuits performing charge redistribution. . 16. The charge accumulating means performs charge redistribution.
17. The semiconductor integrated circuit according to claim 15, wherein the semiconductor integrated circuit is shared by a plurality of level conversion circuits. 17. The charge accumulating means performs charge redistribution.
The charging means, which is shared by the two level conversion circuits, alternately charges the vicinity of the precharge potential of one of the level conversion circuits performing charge redistribution and the vicinity of the precharge potential of the other level conversion circuit. 17. The semiconductor integrated circuit according to claim 16, wherein the inputs of the two level conversion circuits are set such that the change periods of the signals are shifted from each other by a half period. 18. The charge redistribution means according to claim 2, further comprising:
One of the two charge storage means of the two level conversion circuits
One of the level conversion circuits is connected to the output node on the side that changes to the high potential side, and the other charge storage means is connected to the output node on the side that changes to the low potential side in the other level conversion circuit. 16. The semiconductor integrated circuit according to claim 14, wherein the semiconductor integrated circuit is connected. 19. The charge amount change characteristic equalizing means precharges two output nodes having substantially the same parasitic capacitance value to a predetermined potential in each level conversion circuit, and sets a mutual precharge potential of each level conversion circuit. 11. The semiconductor integrated circuit according to claim 10, wherein the potential difference is set to the same value or a ratio of a reciprocal of a parasitic capacitance value of each of the level conversion circuits. 20. The charge redistribution means comprising: an output node in which two pre-charge potentials are adjacent to perform a charge redistribution and one of the level conversion circuits changes to a low potential side in response to an input. 20. The semiconductor integrated circuit according to claim 19, wherein a short circuit is made between the other level conversion circuit and an output node which changes to a high potential in accordance with an input. 21. In each level conversion circuit, two output nodes are precharged to the same potential in a first period in one cycle of the clock signal, and in a second period in one cycle of the clock signal, Charging each charge storage means of the two level conversion circuits for redistributing charges to a predetermined potential between both precharge potentials of the two level conversion circuits for redistributing the charges;
Thereafter, in a third period after the first period and the second period in one cycle of the clock signal, one of the two charge accumulating means of the two level conversion circuits for redistributing the charges is connected to One of the two level conversion circuits for redistributing charges is connected to the output node on the side that changes to the higher potential side, and the other charge storage means changes to the lower potential side by the other level conversion circuit. 16. The control method for a semiconductor integrated circuit according to claim 14, wherein the control circuit is connected to a side output node. 22. A potential for charging two charge storage means in a second period within one cycle of a clock signal is a potential between both precharge potentials of two level conversion circuits for redistributing charges. 22. The control method for a semiconductor integrated circuit according to claim 21, wherein: 23. A potential for charging two charge storage means in a second period within one cycle of a clock signal is applied to one of two level conversion circuits for redistributing charges in one of the charge storage means. 22. The semiconductor integrated circuit according to claim 21, wherein the potential is substantially the same as the charge potential, and the other charge storage means is substantially the same as the other precharge potential of the two level conversion circuits for redistributing the charges. Circuit control method. 24. The system according to claim 5, wherein the first period and the second period are the same period.
A method for controlling the level conversion circuit or the semiconductor integrated circuit according to the above. 25. In each level conversion circuit, two output nodes are precharged to the same potential in a predetermined period within one cycle of the clock signal, and thereafter, a period after the predetermined period in one cycle of the clock signal And an output node on one side of the two level conversion circuits for redistributing the electric charges, which changes to a high potential side, and an output node on the other side, which changes to a low potential side in the other level conversion circuit. 21. The control method for a semiconductor integrated circuit according to claim 19, wherein the connection is established. 26. A power supply terminal, comprising:
11. The semiconductor integrated circuit according to claim 9, further comprising a through-current preventing means for controlling a through-current not to flow between the power supply terminals. 27. The through current prevention means comprises a plurality of transistors, wherein the plurality of transistors are simultaneously turned on.
27. The semiconductor integrated circuit according to claim 26, wherein the control is performed so as not to be N. 28. The semiconductor integrated circuit according to claim 27, wherein the plurality of transistors are controlled by an independent control signal different from an input of the level conversion circuit. 29. A plurality of level conversion circuits, an output node provided in a part of the plurality of level conversion circuits is connected in parallel with each other, and the plurality of output nodes connected in parallel are connected to each other. 2. The device according to claim 1, wherein the first charge supply unit is connected to the first charge supply unit or the second charge supply unit.
9. The level conversion circuit or the method for controlling a level conversion circuit according to 2, 3, 4, 5, 6, 7, or 8. 30. A plurality of level conversion circuits, wherein output nodes respectively provided in some of the plurality of level conversion circuits are connected in series with one another, and each of the plurality of output nodes connected in series is connected to each other. Is connected to the first charge supply means or the second charge supply means. 9. The level conversion circuit or the level conversion circuit according to claim 1, wherein Control method. 31. The level conversion circuit according to claim 6, wherein the high-potential power supply line is a high-potential external power supply line. 32. The level conversion circuit according to claim 6, wherein the high-potential power supply line is a high-potential internal power supply line. 33. The level conversion circuit according to claim 7, wherein the low potential power supply line is a low potential external power supply line. 34. The level conversion circuit according to claim 7, wherein the low potential power supply line is a low potential internal power supply line. 35. A plurality of level conversion circuits, which are arranged in series between a first power supply and a second power supply having a potential different from a potential of the first power supply, and wherein the plurality of level conversion circuits are provided. The level conversion circuit having a large change degree of the output node with respect to time among the conversion circuits is arranged at a position closer to the first power supply or the second power supply than the remaining level conversion circuits. 26. The semiconductor integrated circuit according to claim 19, 20 or 25, or the control method of a semiconductor integrated circuit. 36. The semiconductor integrated circuit or the method for controlling a semiconductor integrated circuit according to claim 35, wherein the level conversion circuit composed of a P-type MOSFET is arranged on a side near a power supply having a high potential. 37. A semiconductor integrated circuit or a method for controlling a semiconductor integrated circuit according to claim 35, wherein the level conversion circuit composed of an N-type MOSFET is arranged on a side closer to a power supply having a low potential. 38. A plurality of level conversion circuits, among which a plurality of level conversion circuits having the same degree of change of the output node with respect to time, includes a first power supply and the first power supply.
10. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit is arranged in series with a second power supply having a potential different from the potential of the power supply. 39. The plurality of level conversion circuits are grouped by level conversion circuits having the same degree of change of an output node with respect to time, and the level conversion circuits belonging to each group in each group are a first power supply and a second power supply. 39. The semiconductor integrated circuit according to claim 38, wherein the semiconductor integrated circuit is arranged in series between the two power supplies. 40. A cycle of an operation clock is different between a group of level conversion circuits having a large degree of change of an output node with respect to time and a group of level conversion circuits having a small degree of change of an output node with respect to time. 40. The level conversion circuit according to claim 39, wherein: 41. The charge amount changing characteristic equalizing means controls connection to a power supply at a cycle that is an integral multiple of a cycle of an operation clock of the plurality of level conversion circuits.
9. The semiconductor integrated circuit according to 9, 20, or 25, or a method for controlling a semiconductor integrated circuit. 42. Each of output nodes of a plurality of level conversion circuits arranged in series between a first power supply and a second power supply has a potential detecting means for detecting a potential of a corresponding output node. Connected, and among the plurality of potential detecting means,
The potential detection means corresponding to the output node of the level conversion circuit whose precharge potential at the output node of the level conversion circuit is higher than the intermediate potential between the first power supply and the second power supply is an N-type MOSFET. 42. The semiconductor integrated circuit according to claim 9, wherein the potential detecting means configured and corresponding to an output node of the level conversion circuit lower than the intermediate potential is configured by a P-type MOSFET. 43. An output of a potential detecting means composed of an N-type MOSFET is connected to each source of an N-type pair transistor of a CMOS flip-flop circuit, and a potential composed of a P-type MOSFET is connected. The output of the detection circuit is CMOS
5. The flip-flop circuit according to claim 4, wherein the source is connected to each source of a P-type pair transistor of the flip-flop circuit.
3. The semiconductor integrated circuit according to item 2. 44. Outputs from each output node of the plurality of level conversion circuits are transferred to the outside as two or more parallel data, and the two or more parallel data are stored in advance in advance of the potential of the first power supply and the second power. 10. The control method for a semiconductor integrated circuit according to claim 9, wherein the data is transferred to the outside by using a plurality of voltage ranges obtained by dividing a range of a finite potential difference with the power supply potential. 45. The method according to claim 44, wherein the number of divisions of the finite potential difference is equal to the number of parallel data transfers. 46. A plurality of level conversion circuits, which are arranged in series between a first power supply and a second power supply having a potential different from the potential of the first power supply, wherein the first power supply 10. The semiconductor integrated circuit according to claim 9, wherein a relatively large decoupling capacitor is connected between the first power supply and the second power supply. 47. The first power supply and the second power supply are internal power supplies, and a decoupling capacitor is connected between the first internal power supply and the second internal power supply. 46. The semiconductor integrated circuit according to 46. 48. The first power supply and the second power supply are external power supplies, and a number of decoupling capacitors equal to the number of level conversion circuits are provided between the first external power supply and the second external power supply. 47. The semiconductor integrated circuit according to claim 46, wherein each of the connected decoupling capacitors is connected to a node between two corresponding level conversion circuits. 49. A plurality of level conversion circuits, which are arranged in series between a first power supply and a second power supply having a potential different from the potential of the first power supply, and wherein the plurality of level conversion circuits are provided. 10. The semiconductor integrated circuit according to claim 9, wherein, of the conversion circuits, an output of a level conversion circuit connected to the first power supply or an output of a level conversion circuit connected to the second power supply is not used. 50. The number of the plurality of level conversion circuits is:
50. The semiconductor integrated circuit according to claim 49, wherein the number is equal to the required number of parallel data except for the level conversion circuit connected to the power supply or the level conversion circuit connected to the second power supply. .