JP2008140531A - Semiconductor device and memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a memory that can respond quickly and reduce power consumption. <P>SOLUTION: The semiconductor device has a first voltage step-down circuit 12 that generates a first step-down voltage VINT1 which is lower than a power supply voltage VDD0 supplied from the outside, and a second voltage step-down circuit 13 that generates a second step-down voltage VINT2 which is lower than the first step-down voltage VINT1. The first voltage step-down circuit 11 has a withstand voltage equivalent to the power supply voltage, and the second voltage step-down circuit has a withstand voltage equivalent to the first step-down voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a memory equipped with a step-down circuit that generates a voltage lower than a power supply voltage.

  A DRAM usually has a thick film transistor for driving a word or the like and a thin film transistor for driving a logic portion. Thin-film transistors can handle voltages up to, for example, about 2.5V, and thick-film transistors can handle voltages up to, for example, about 3.3V. However, the memory cell is operated at, for example, about 1.8 V from the viewpoint of reducing power consumption. Therefore, a step-down circuit that steps down the external voltage VDD0 to 1.8 V, for example, is required (see, for example, Patent Document 1).

  FIG. 18 is a diagram showing a conventional memory and a step-down circuit provided in the periphery thereof. As shown in FIG. 18, the step-down circuit unit 110 includes a power supply terminal 111 that supplies an external system power supply VDD0 such as 3.3 V, and step-down circuits 112 and 113. The external power supply VDD0 is supplied as it is to the I / O interface 31 and the like. The peripheral logic circuit 20 is supplied with a step-down voltage V1 obtained by stepping down the external power supply DVV0 to 2.5V, for example. For this reason, the step-down circuit unit 110 includes a step-down circuit 112. The step-down circuit 112 generates a step-down voltage V1 from the external voltage VDD0. Further, the memory cell 21 is supplied with a lower step-down voltage V2 such as 1.8V. For this reason, the step-down circuit unit 110 includes a step-down circuit 113. The step-down circuit 113 generates a step-down voltage V2 from the external voltage VDD0.

By the way, as described in Patent Document 2, in the overdrive method, as shown in FIG. 19, after the word line is activated and raised to the word line boosted voltage VPP, the bit line is activated and the High side is activated. The bit line (T) is opened and amplified to the array internal step-down voltage VDL, and the bit line (B) on the low side is opened to the ground voltage VSS. At this time, after generating the overdrive start pulse FASAP1T and opening the High-side bit line (T) to the overdrive voltage VDDA, the VDL sense amplifier start signal FASAP2T is generated to generate the array internal step-down voltage VDL. Stabilize with.
JP 2000-149565 A

  However, although it is possible to reduce the power supply voltage of the memory cell array by providing a step-down circuit, in order to generate a low voltage from such a high power supply voltage VDD0, a step-down circuit using a thick film transistor is required. There is a problem that the response is poor and the current mirror current is large and the current consumption is large.

  Further, when it is intended to realize overdrive by providing a stage voltage step-down circuit, it is necessary to set the overdrive voltage as the power supply potential and the normal voltage as the step-down voltage. Therefore, the step-down circuit needs to be composed of a thick film transistor matched to VDD after all, and as described above, the response is poor and the increase in speed is hindered.

  A semiconductor device according to the present invention includes a first step-down circuit that generates a first step-down voltage lower than a power supply voltage supplied from the outside, and a second step that generates a second step-down voltage that is lower than the first step-down voltage. The first step-down circuit has a withstand voltage higher than the power supply voltage, and the second step-down circuit has a withstand voltage higher than the first step-down voltage.

  The memory according to the present invention is provided in common to a plurality of banks and generates a first step-down voltage lower than the power supply voltage from the power supply voltage, and the first step-down voltage provided individually in each bank. A first step-down circuit including a second step-down circuit that generates a second step-down voltage lower than the first step-down voltage from a voltage; and a plurality of memory banks driven by the second step-down voltage. Has a breakdown voltage higher than the power supply voltage, and the second step-down circuit has a breakdown voltage higher than the first step-down voltage.

  In the present invention, the second step-down circuit generates the second step-down voltage from the first step-down voltage lower than the power supply voltage supplied from the outside. Therefore, since it has a withstand voltage equal to or higher than the first step-down voltage, it can be configured with a transistor having a withstand voltage lower than that of a circuit that generates the second step-down voltage from a power supply voltage supplied from the outside.

  According to the present invention, it is possible to provide a semiconductor device and a memory that can respond quickly and reduce power consumption.

Embodiment 1 FIG.
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1A is a block diagram showing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1A, the semiconductor device 1 includes a step-down circuit unit 10, a reference voltage generation circuit 26, sense amplifiers S1 to S4 (21), cell arrays SA1 to SA4 (22), a row decoder 23, and a command control unit. 24, a column decoder 25, a booster circuit 27, an I / O interface 31, and the like. The step-down circuit unit 10 includes a first step-down circuit 12 and a second step-down circuit 13.

  The reference voltage generation circuit 26 generates a reference voltage VREF1 such as 2.5V, for example, a reference voltage VREF2 such as 1.8V, based on the external voltage VDD0 from the external system, and the first step-down circuit 12 and the second step-down circuit, respectively. 13 is supplied. The first step-down circuit is supplied with an external voltage VDD0 from an external system, and generates a first step-down voltage (first internal voltage) VINT1 (= VREF1) based on VREF1.

  The second step-down circuit 13 is supplied with VINT1 from the first step-down circuit 12, and generates a second step-down circuit (second internal voltage) VINT2 (VREF2) based on the reference voltage VREF2.

  The row decoder 23 supplies a voltage obtained by boosting the power supply voltage VDD0 by the booster circuit 27 to the selected word line. In addition, a row address is generated and input to the sense amplifiers S1 to S4. The column decoder 25 generates a column address and inputs it to the sense amplifiers S1 to S4. The command control unit 24 distributes signals for the row decoder 23 and the column decoder 25 to generate a row address and a column address from a serial signal. The row decoder 23, the column decoder 25, and the command control unit 24 are operated by the first step-down voltage VINT1 generated by the first step-down circuit 12.

  The I / O interface 31 controls data exchange between the memory cell array 22 and the external terminal 32. The I / O interface 31 operates based on an external voltage.

  Here, in this embodiment, there are two types of step-down circuits. That is, first, as shown in FIG. 1B, the first step-down circuit 12 that generates the first step-down voltage VINT1 such as 2.5V from the external voltage VDD0 such as 3.3V is provided. Further, as shown in FIG. 1C, a second step-down voltage circuit 13 for generating a second step-down voltage VINT2 such as 1.8 V, which is lower than the first step-down voltage VINT1, is provided.

  For this reason, the first step-down circuit 12 has a withstand voltage equivalent to or higher than the power supply voltage, and the second step-down circuit 13 is configured to have a withstand voltage equivalent to or higher than the first step-down voltage. That is, the thickness of the oxide film of the transistor constituting the first step-down circuit is thicker than the thickness of the oxide film of the transistor constituting the second step-down circuit.

FIG. 2 is a block diagram showing the step-down circuit portion shown in FIG. 1 in more detail. In the step-down circuit unit shown in FIG. 2, the same components as those of the semiconductor device shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. As illustrated in FIG. 2, the step-down circuit unit 10 includes a first step-down circuit 12 that performs voltage conversion, second step-down circuits 13 _{1 to} 13 ₄ , power supply protection circuits 16 and 17, and a switching circuit 15.

As described above, the first step-down circuit 12 is a circuit that converts the external power supply VDD0 from the external system into the first step-down voltage VINT1, and the generated first step-down voltage VINT1 is converted to the peripheral logic circuit 20 and the second step-down voltage. It supplies the circuit _131-134.

Switching circuit 15 includes a power supply terminal 11 for supplying an external source is provided between the second step-down circuit _131-134, by ON the switching circuit 15, first from the first step-down circuit 12 Instead of the one step-down voltage VINT1, the external power supply is configured to be directly supplied to the second step-down circuits 13 _{1 to} 13 ₄ . The switching circuit 15 may be mask-like switching such as an aluminum master slice, or may be electrical signal switching based on a test mode, fuse information, or the like. Here, when the voltage of the external power supply is the same as the first step-down voltage, that is, when the external power supply is low, the first step-down circuit is unnecessary. In the present embodiment, since it has the switching circuit 15, without using the first step-down circuit 12, the external voltage from the power supply terminal 11 directly and the second step-down circuit _131-134, the peripheral logic circuit 20 Can be supplied.

  A power protection circuit 16 is connected to an external power supply line from the power terminal 11 via a switch SW1. Further, the power protection circuit 17 is connected to the first step-down voltage supply line via the switch SW2. Similarly to the above, the switches SW1 and SW2 may be masked switching such as an aluminum master slice, or may be electrical signal switching based on a test mode, fuse information, or the like. When external power is supplied to the first step-down circuit 12, the switch SW1 is turned on to operate the power protection circuit 16. When the external power supply is directly supplied to the second step-down circuit 13 without going through the first step-down circuit 12, the switch SW2 is turned on to operate the power protection circuit 17.

As described above, the second step-down circuits 13 _{1 to} 13 ₄ convert the first step-down voltage VINT1 to generate the second step-down voltage VINT2. The second step-down circuit 13 can use a transistor having a lower withstand voltage than the first step-down circuit 12 because the first step-down voltage VINT1 is lower than the external voltage. That is, since a transistor with a thin oxide film thickness can be used, the switching speed is improved and low power consumption is realized.

  In the present embodiment, an external power source is provided by providing a first step-down circuit 12 that steps down an external power source and a second step-down circuit 13 that further steps down the first step-down circuit VINT1 stepped down by the first step-down circuit 12. As compared with the case where the second step-down voltage is generated, a step-down circuit composed of a transistor having a thin oxide film thickness can be used as the second step-down circuit 13. Therefore, since the oxide film thickness is thin, the current mirror current can be reduced and the responsiveness can be improved.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in order to improve the amplification efficiency of the sense amplifier in the DRAM, there is an “overdrive method” in which a voltage higher than the restore voltage is used for driving the sense amplifier at the initial stage of cell data amplification. If this method is applied to the step-down circuit of the present application, a more effective and stable step-down voltage can be supplied to the DRAM core. Furthermore, the overdrive may be applied to all step-down circuits, or may be applied to some step-down circuits, and more effectively by optimizing the overdrive execution timing. Needless to say, voltage can be supplied.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. 3 and 4 are circuit diagrams showing specific configurations of the first step-down circuit 12 and the second step-down circuit 13, respectively. In the following embodiment, the same components as those in the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 3, the first step-down circuit 12 includes a power supply detection circuit 121 and a driver 122.

  The power supply detection circuit 121 includes N-channel MOS transistors MN11 to MN15 and P-channel MOS transistors MP11 and MP12. The driver 122 includes an N channel MOS transistor MNpower1. The gate film thickness of each transistor is thick. Here, among transistors constituting the amplifier, MN12 to which the reference voltage VREF1 is input is provided as a first transistor, and MN11 constituting a differential pair with MN12 is provided as a second transistor. Further, MN13 to which a BANK common overcharge signal (to be described later) is input is a voltage adjustment transistor that is provided in parallel to MN12 and adjusts the voltage of VINT1, and MN14 is a current adjustment transistor that adjusts the current flowing through MN13.

  MP11 and MP12 have a gate connected and a source connected to the power supply potential VDD0 to form a current mirror. In MP12, the gate and drain are short-circuited, the drain of MN14 is connected to the drain, and MN13 is connected in series to MN14. Further, MN12 is connected in parallel with MN14 and MN13 connected in series. Further, the drain of MN11 is connected to the drain of MP11, and its gate is connected to the source of MNpower1. The sources of MN11 and MN13 are connected to the drain of MN15, the source of MN15 is grounded, and VDC is supplied to the gate. Whether or not the power supply detection circuit 121 operates is set according to the value of VDC. The output of the OR circuit 101 is connected to the gate of the MN 13, and a BANK common overcharge signal described later is input from the OR circuit 101. Further, VREF1 is supplied to the gate of MN12, and Vrcont is supplied to the gate of MN14. VREF1 is a voltage for setting the value of VINT1 when the BANK shared overcharge signal is Low. Vrcont is a voltage for setting the value of the ON resistance of MN14. If Vrcont is large, the ON resistance of MN14 is small.

  The drain of MNpower1 is connected to the power supply potential VDD0, the gate is connected to the drain of MP11 (the drain of MN11), and VDDACTD1 is supplied. The source is connected to the output terminal and outputs VINT1. VINT1 is the output voltage of the first step-down voltage circuit as described above.

  Next, the operation of the first step-down circuit 12 will be described. The power supply detection circuit 121 compares the potential difference between VINT1 and VREF1, and controls the gate voltage (VDDACTD1) of the driver 122. That is, when the voltage of VINT1 drops due to current consumption, VINT1 <VREF1 is detected, and the operation is performed so that VDDACTD1 rises.

  Here, since the MN13 that inputs the BANK common overcharge signal to the gate and the MN12 that inputs VREF1 to the gate are connected in parallel, when the VREF1 and BANK common overcharge signals are High, the two-stage transistors Current flows, and VREF1 is increased in the current detection circuit 121 in a pseudo manner, causing an offset. In this first step-down circuit 12, VDDACTD1 is set to a high level in advance at the time of sensing when a second step-down circuit 13 described later is expected to consume a large amount of current, and prepares for current consumption of the second step-down circuit 13. is there.

  This will be specifically described. When the BANK shared overcharge signal is Low, when VINT1 decreases, the current flowing through MN11 decreases. Thereby, the electric current which flows into MP11 becomes large. In response to this, VDDACTD1 rises and VINT1 rises.

  Further, when the BANK common overcharge is High, since MN12 is ON, a current flows in parallel to MN12 and MN14. That is, it becomes a state where VREF1 is increased in a pseudo manner. Therefore, VINT1 decreases. As a result, the current flowing through MN11 decreases and the current flowing through MP11 increases. In response to this, VDDACTD1 rises.

  Next, the second step-down circuit will be described. As shown in FIG. 4, the second step-down circuit 13 includes a power supply detection circuit 131 and a driver 132. The second step-down circuit 13 according to the present embodiment basically has the same configuration as the first step-down circuit 12. However, the gate thickness of the transistor to be configured is a thin film.

  As shown in FIG. 4, the power supply detection circuit 131 includes N-channel MOS transistors MN21 to MN25 and P-channel MOS transistors MP21 and MP22. The driver 132 is composed of an N-channel MOS transistor MNpower2. Here, among transistors constituting the amplifier, MN22 to which the reference voltage VREF2 is input is provided as a first transistor, and MN21 constituting a differential pair with MN22 is provided as a second transistor. Further, MN23 to which a BANK common overcharge signal (to be described later) is input is provided in parallel with MN22 and is a voltage adjustment transistor that adjusts the voltage of VINT2, and MN24 is a current adjustment transistor that adjusts the current flowing through MN23.

  MP21 and MP22 have a gate connected and a source connected to the power supply potential VDD0 to form a current mirror. In MP22, the gate and the drain are short-circuited, the drain of MN24 is connected to the drain, and MN23 is connected in series to MN24. The MN22 is connected in parallel with the MN24 and MN23 connected in series. Further, the drain of MP21 is connected to the drain of MN21, and the gate thereof is connected to the source of MNpower2. The sources of MN21 and MN23 are connected to the drain of MN25, the source of MN25 is grounded, and VDC is supplied to the gate. Whether or not the power supply detection circuit 131 operates is set according to the value of VDC. A BANK0 overcharge signal described later is input to the gate of MN23. Note that this second step-down circuit is used in BANK0. Further, VREF2 is supplied to the gate of MN22, and Vrcont is supplied to the gate of MN24. VREF2 is a voltage for setting the value of VINT2 when the BANK overcharge signal is Low. Vrcont is a voltage for setting the value of the ON resistance of MN24. If Vrcont is large, the ON resistance of MN4 is small.

  The drain of MNpower2 is connected to the power supply potential VINT1, the gate is connected to the drain of MP21 (the drain of MN21), and VDDACTD2 is supplied. The source potential becomes VINT2. VINT2 is the output voltage of the second step-down voltage circuit as described above.

  Next, the operation of the second step-down circuit 13 will be described. When the BANK shared overcharge signal is Low, when VINT2 decreases, the current flowing through MN21 decreases. Thereby, the electric current which flows into MP21 becomes large. Accordingly, VDDACTD2 rises and VINT2 rises.

  Further, when the BANK common overcharge is High, since MN22 is ON, a current flows in parallel to MN22 and MN24. That is, VREF2 is raised in a pseudo manner. Therefore, VINT2 decreases. As a result, the current flowing through MN21 decreases and the current flowing through MP21 increases. In response to this, VDDACTD1 rises.

  Next, a case where the first step-down circuit 12 and the second step-down circuit 13 are applied to the memory as shown in FIG. 2 will be described. FIG. 5 is a diagram illustrating a sense amplifier, a memory cell, and a multistage voltage down converter. Here, memory cells from BANK0 to BANK2 among n banks BANKn are shown.

  As shown in FIG. 5, the second step-down circuit 13 is connected to the first step-down circuit 12, and VINT1 is supplied. The second step-down circuit 13 is provided for each bank, and supplies the second step-down voltage VINT2 to the sense amplifier. Here, in the present embodiment, the BANK0 to BANK3 overcharge signals are input to the first step-down voltage circuit 12 in order to perform overcharge. As described above, these signals are ORed by the OR circuit 101 and used as a BANK common overcharge signal. In addition, the BANKn overcharge signal corresponding to each bank is input to the second step-down circuit 13.

  FIG. 6 is a diagram illustrating signal waveforms input to the first step-down circuit and the second step-down circuit, respectively. When the BANK0 overcharge signal becomes High, the BANK common overcharge signal also becomes High, and the voltage of VDDACTD1 rises. As a result, the voltage of VINT1 also rises. At this time, VDDACTD2 of BANK0 also rises, and the voltage of VINT2 rises accordingly and overcharge is realized. In the overcharge, the potential difference between the bit lines BL and BLB connected to the sense amplifier 21 gradually increases and the sense period starts.

  Thus, based on the BANKn overcharge signal, a current is supplied to the MN 13 to offset the power supply detection circuit 121 and increase the output voltage of the first step-down circuit 12 (forced activation). As in the present embodiment, in the case of a two-stage step-down circuit, the current of the first step-down circuit 12 is adjusted according to the current consumption in the second step-down circuit 13 connected to the first step-down circuit 12 in the first stage. The output voltage needs to be increased. Normally, a DRAM sense amplifier consumes a large amount of current, and various methods such as overdrive and overcharge are used. In this embodiment, the OR of a BANKn overcharge signal (sense signal) input for each BANK is used. Therefore, the BANK common overcharge signal is used. The amount of charge supplied to the second step-down circuit 13 is compensated by performing overdrive and overcharge of the first step-down circuit in accordance with the overdrive and overcharge timing of the second step-down circuit 13. Thereby, the responsiveness of the first step-down circuit 12 can be improved, the power supply drop of the first step-down circuit 12 can be suppressed, and the high-speed operation of the second step-down circuit 13 can be compensated.

  In the present embodiment, the BANK 0-3 overcharge signal is input to the OR circuit 101 to generate the BANK common overcharge signal. However, as shown in FIG. It is also possible to obtain the logical sum of the BANK0 to 3 overcharge signals. That is, MN16 to MN18 may be connected in parallel with MN13, and BANK0 to 3 overcharge signals may be input to MN13 and MN16 to MN18, respectively.

  Next, a modification according to this embodiment will be described. 8 and 9 are circuit diagrams showing a first step-down circuit according to a modification of the present embodiment. The first step-down circuit shown in FIG. 3 increases current capability by providing an offset between VINT1 and VREF1, and performs overdrive and overcharge. In this modification, the BANK common overcharge signal is used. To control the response of the amplifier.

  In the example shown in FIG. 8, in the power supply detection circuit 121 shown in FIG. 3, MN19 as a second current source transistor is connected between MN11 and MN12 constituting a differential pair and MN15 as a first current source. Connect in series. Then, MN13 as a switching transistor for switching whether MN19 is valid or invalid is connected in parallel to MN19. In the power supply detection circuit 121b, VDC is input to the gate of MN19 in the same manner as MN15. In the example shown in FIG. 9, as in FIG. 7, in the power supply detection circuit 121c, instead of inputting the BANK common overcharge signal to MN13, MN16 to MN18 are provided in parallel to MN13, and MN13, MN16 to MN18 are provided. Are supplied with BANK0-3 overcharge signals.

  Thus, the first step-down voltage circuit 12 according to the present modification increases the current flowing through the amplifier in accordance with the current consumption of the second step-down voltage circuit 13 and increases its capability. Here, the response and capability are controlled in accordance with the BANKn overcharge signal. It is also possible to input the BANKn VDL activation signal, which will be described later, in place of the BANKn overcharge signal, thereby increasing its capability.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. The present embodiment is applied to an overdrive method for improving the ability to forcibly supply charges by greatly displacing the gate voltage of the output driver instead of the overcharge.

  FIG. 10 is a diagram illustrating the first step-down circuit 12 according to the present embodiment. The first step-down circuit 12 includes a power supply detection circuit 123 and a driver 124. The power supply detection circuit 123 includes N-channel MOS transistors MN31 to MN36, P-channel MOS transistors MP31 to MP37, a constant current source 102, and an inverter 103. The driver 124 includes a P-channel MOS transistor MPpower1 and an N-channel MOS transistor MNR connected in series.

  MP35, MP36, and MP37 are connected in parallel with their sources connected to the power supply potential VDD0. The drain of MP37 is connected to the gate of MPpower1. The ENABL signal is input to the gate of MP35. The ENABL signal is a signal that determines whether or not to operate the power supply detection circuit 123. The ENABL signal is a signal for commonly activating the first step-down circuit when a command for activating the second step-down circuit is input regardless of BANK. It becomes Low when all BANKs become inactive.

  The drain of MP35 is commonly connected to the gates of MP32 and MP31. The gates of MP31 and MP32 are connected to each other, the source is connected to the power supply potential VDD0, and forms a current mirror. In MP32, the gate and the drain are short-circuited. The source of MN34 is connected to the drain of MP32. In MP34, the gate and the source are short-circuited.

  The drains of MN32 and MN33 are connected to the drain of MP31. MN32 and MN33 are connected in parallel, and the drain of MN36 is connected to the source. VREF1 is supplied to the gate of MN32, and a BANK common overcharge signal is input to the gate of MN33. The source of the MN 36 is connected to the constant current source 102 connected to the ground, and the ENABL signal is supplied to the gate.

  The gates of MP33 and MP34 are connected to each other and to the drain of MP36, and the power supply potential VDD0 is supplied to the source to form a current mirror. The gate and drain of MP33 are short-circuited. The drain of MP33 is also connected to the drain of MN31, and its source is connected to the drain of MP36. The gate is connected to the drain of MPpower1, and VINT1 is output from the drain.

  The drain of MP34 is connected to the drain of MN35, its gate is connected to the gate of MN34 and the drain of MN34, and the source is grounded. The source of the MN 34 is grounded, and the ENABLE signal via the inverter 103 is supplied to the gate.

  In the driver 124, MPpower1 is connected in series to the MNR connected to the power supply voltage VDD0. VPP is supplied to the gate of the MNR. The gate of MPpower1 is connected to the drains of MP37 and MP34, and VDDACTD1 is supplied.

  The first step-down circuit 12 configured as described above is obtained by replacing the first step-down circuit according to the second embodiment with a general push-pull type. Similarly to the second embodiment, the first step-down circuit 12 includes an MN 33 that inputs a BANK common overcharge signal to the gate and causes an offset to the power supply detection circuit. Here, also in the present embodiment, an MN 14 to which Vrcont is input may be provided, and N channel MOS transistors may be stacked vertically as in the second embodiment.

  In the first step-down circuit 12 as well, the amount of electric charge supplied to the second step-down circuit can be compensated by activating the second step-down circuit with a BANK common overcharge signal as a large current flows through overdrive. it can.

  Next, the second step-down circuit 13 according to the present embodiment will be described. FIG. 11 is a diagram illustrating the second step-down circuit according to the present embodiment. The second step-down circuit 13 includes a power supply detection circuit 133 and a driver 134.

  The power supply detection circuit 133 includes N-channel MOS transistors MN41 to MN44, P-channel MOS transistors MP41 to 44, a constant current source 104, and an inverter 105. The driver 134 has a P-channel MOS transistor MPpower2.

  The source of MP43 is connected to VINT1, and the BANKn overdrive signal is supplied to the gate via the inverter 105. The drain is commonly connected to the gates of MP42 and MP41. The MP43 functions as a third transistor that turns the amplifier on and off. The MP43 is supplied with an inverted signal of the BANKn overdrive signal, and stops the operation of the amplifier when turned ON. The sources of MP41 and MP42 are connected to VINT1, and the gates are connected to each other to form a current mirror. The gate and drain of MP42 are short-circuited. The drain of MN43 is connected to the drain of MP42. MN43 is supplied with VREF2 at its gate. A MN42 is connected in parallel to the MN43, and a MANK common overcharge signal is supplied to the gate. The source of MN43 is connected to a constant current source 104 connected to ground. Further, the drain of MN41 is connected to the drain of MP41, and its gate is connected to the drain of MPpower2. The drain voltage of MN41 becomes VDDACTD2 and is supplied to the gate of MPpower2 constituting the driver 134. The source of MPpower2 is connected to VINT1, and VITN2 is output from the drain. Further, the drain of MP44 whose source is connected to VINT1 is connected to the gate of MPpower2. A VDL activation signal is supplied to the gate of MP44. The drain of MN44 whose source is grounded is connected to the drain of MP44. A BANKn overdrive signal is supplied to the gate of MN44.

  Next, operations of the first step-down circuit 12 and the second step-down circuit 13 will be described. FIG. 12 is a diagram showing signal waveforms at each node. When the ENABLE signal is Low, MP35, MP36, and NP37 in FIG. 10 are turned off, so that MPpower1 is also turned off.

  Next, when the ENABLE signal is High and the BANK common overcharge signal is High, MP35, MP36, and MP37 in FIG. 10 are OFF, and MN36 is ON. Also, MN33 is turned on, and a current flows in parallel to MN32 and MN33. As a result, VREF1 is raised in a pseudo manner. Therefore, VINT1 decreases and the current flowing through MN35 increases. At the same time, the current flowing through MN 34 decreases. In response, VDDACTD1 falls and VINT1 rises.

  Next, when the ENABLE signal is High and the BANK common overcharge signal is Low, MP35, MP36, and MP37 in FIG. 10 are OFF and MN36 is ON. Since MN33 is OFF, VREF1 = VINT1. Here, when VINT1 decreases, the current flowing through MN35 increases and the current flowing through MP34 decreases. In response to this, VDDACTD1 falls and VINT1 rises so that VREF1 = VINT1.

  Further, in the second step-down circuit 13, the MPpower2 of the driver 134 is turned on and the VINT2 is raised by the VDL activation signal and the overdrive signal in the initial sense period. If the overdrive period is long, VINT2 rises to VINT1. During the overcharge period in which overdrive is completed, VREF2 is increased in a pseudo manner.

  When the VDL activation signal is High, the BANK common overcharge signal is High, and the BANKn overdrive signal is High, MP44 is turned OFF and MN44 is turned ON, so that VDDACTD2 becomes Low and MNpower2 is turned ON. Thereby, the voltage of VINT2 rises. Since MP43 is OFF, MP21 and MP22 are OFF and the operation of the amplifier is stopped.

  Next, when the VDL activation signal is High, the BANK common overcharge signal is High, and the BANKn overdrive signal is Low, the MN 44 is turned OFF. On the other hand, MP43 is turned OFF. Accordingly, the amplifier operates, and a current flows through MN42 and MN43. Accordingly, VDDACTD2 falls and VINT2 rises accordingly.

  Further, when the VDL activation signal is High, the BANK common overcharge signal is Low, and the BANKn overdrive signal is Low, MN42 is turned OFF, so VINT2 = VFER2.

  Also in the present embodiment, as in the second embodiment, the BANKn overcharge signal input for each BANK is ORed to form a BANK common overcharge signal, and the second step-down circuit 13 is synchronized with the overdrive timing. By carrying out overdrive of the first step-down circuit, the amount of charge supplied to the second step-down circuit 13 is compensated. Thus, the responsiveness of the first step-down circuit 12 can be improved, the power supply drop of the first step-down circuit 12 can be suppressed, and the high-speed operation of the second step-down circuit 13 can be compensated.

Embodiment 4 FIG.
Next, a fourth embodiment will be described. FIG. 13 is a circuit diagram showing the first step-down circuit according to the present embodiment. In the present embodiment, the transistor of the second step-down circuit according to the third embodiment is thickened and applied to the first step-down circuit. In order to apply to the first step-down circuit 12, the BANKn overdrive signal input to N44 in FIG. 11 is the BANK common overcharge signal input to N54. In this embodiment, the BANK common overcharge signal is used. However, a logical sum signal of the BANKn VDL activation signal may be input. Also, the ENABLE signal is used instead of the VDL activation signal. Further, the power supply potential VDD0 is supplied instead of the first step-down voltage VINT1. The difference is that VREF1 is supplied instead of VREF2, and the BANKn overcharge signal is supplied instead of the BANK common overcharge signal. The other points are the same as in the third embodiment. The first step-down voltage circuit 12 also operates in the same manner as in the third embodiment, and the timing chart shown in FIG. 12 is obtained.

  Here, in the second embodiment shown in FIG. 3, the output driver is an N-channel MOS transistor, whereas in this embodiment, it is a P-channel MOS transistor. The second step-down voltage circuit 12 is provided with pull-out MOS transistors (MP54, MN54) for overdrive of a general array power source shown in FIG. The transistors MP54 and MN54 function as a forcible drive circuit that forcibly sets the gate voltage of the driver. When the ENABLE signal becomes Low, the NP 54 is turned on and the driver 126 is turned off.

  An example in which this extraction MOS transistor is applied to the first step-down circuit shown in FIG. 10 is shown in FIG. FIG. 14 is a circuit diagram showing a first step-down voltage circuit according to a modification of the present embodiment. As shown in FIG. 14, MP67 and MN67 for extraction are added. That is, MP67 and MN67 are connected in series between the gate of MPpower2 and the ground. An ENABLE signal is supplied to the gate of MP67. A BANK common overcharge signal is supplied to the gate of MN67. This BANK common overcharge signal may be input with a logical sum signal of the BANKn BLD activation signal as described above. This circuit also has the same timing chart as FIG.

Embodiment 5. FIG.
Next, another example of the step-down circuit unit shown in FIG. 2 will be described. FIG. 15 is a diagram illustrating the step-down circuit unit according to the present embodiment. The step-down circuit unit 10 includes a first step-down circuit 31 that supplies the first step-down voltage VINT1 to the peripheral logic 20 and the like, and a first step-down circuit 32 that supplies VINT1 to the memory cell. By separating the circuit portion that performs the array operation from the peripheral circuit portion, it is possible to prevent noise from being mixed.

16 and 17 show an example in which a compensation capacitor is inserted between the first step-down circuit 32 and the second step-down circuits 13 _{1 to} 13 ₃ while separating the memory cell portion and the peripheral circuit portion. As shown in FIG. 16, compensation capacitors 111 _{1 to} 111 ₃ are provided between the gates of the transistors constituting the driver of the first step-down circuit 31 and the outputs of the second step-down circuits 13 ₁ 13 ₃ . The compensation capacitor ₁₁₁ 1 to 111 ₃ that the provision can be made to respond the first step-down circuit 32 by the drop of the second step-down circuit _{131-134 3.} That is, in the second step-down circuit _{131-134 3} against sudden power drop of each BANK in the sense time, it is possible to enhance the response sensitivity of the first step-down circuit 32. Since the power recovery for each bank is slow with respect to the power drop, the first step-down circuit 32 may be provided in common for multiple banks as in this example.

In addition, as shown in FIG. 17, first step-down circuits 32 _{1 to} 32 ₃ may be provided for each bank. In this case, to connect the compensation capacitance ₁₁₂ 1-112 ₃ and the gate of the first step-down circuit ₃₂₁ to 323 of the driver, between the output of the second step-down circuit _{131-134 3.} Furthermore, the first step-down circuit ₃₂₁ to 323 second step-down circuit _{131-134 3} predetermined period disconnecting switch ₁₁₃ 1 to 113 ₃ may be a provided. In this case, the sensing operation of the overcharge, the switch ₁₁₃ 1 to 113 ₃ by disconnecting the first step-down circuit _{321 to} 323 from being over-charge period until the sense start the second step-down circuit _{131-134 3.} Here, when VINT2 of BANKn, which is the output voltage of the second step-down circuits 13 _{1 to} 13 ₃ , increases due to overcharge, the gate of the Pch driver of the first step-down circuit via the compensation capacitors 112 _{1 to} 112 ₃ The input rises in the direction that the driver turns off. To prevent an increase in the gate input of the Pch driver of the first step-down circuit, a switch ₁₁₃ 1 to 113 ₃ provided, separated from the first step-down circuit ₃₂₁ to 323 once the second step-down circuit _{131-134 3} The connection can be made at the start of sensing when VINT2 falls due to the sensing operation.

Also in this configuration, the second step-down circuits 13 _{1 to} 13 ₃ improve the responsiveness of the first step-down circuit with respect to a sudden power drop for each BANK during sensing. Further, by providing the first step-down circuits 32 _{1 to} 32 ₃ and the second step-down circuits 13 _{1 to} 13 ₃ for each bank as in this example, the response improvement of the first step-down circuits 32 _{1 to} 32 ₃ is further improved. Can be increased.

(A) is a block diagram illustrating a semiconductor device according to an embodiment of the present invention, (b) is a schematic diagram illustrating a first step-down circuit, and (c) is a schematic diagram illustrating a second step-down circuit. FIG. 2 is a block diagram showing the step-down circuit part shown in FIG. 1 in more detail. It is a circuit diagram which shows the specific structure of the 1st voltage step-down circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the specific structure of the 2nd pressure | voltage fall circuit in Embodiment 2 of this invention. It is a figure which shows the sense amplifier in Embodiment 2 of this invention, a memory cell, and a multistage pressure | voltage fall circuit. It is a figure which shows the signal waveform each input into the 1st voltage | voltage fall circuit and the 2nd voltage | voltage fall circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the other specific structure of the 2nd step-down circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the specific structure of the 1st voltage step-down circuit concerning the modification of Embodiment 2 of this invention. It is a circuit diagram which shows the other specific structure of the 1st voltage step-down circuit concerning the modification of Embodiment 2 of this invention. It is a figure which shows the 1st voltage step-down circuit concerning Embodiment 3 of this invention. It is a figure which shows the 2nd pressure | voltage fall circuit concerning Embodiment 3 of this invention. It is a figure which shows the signal waveform each input into the 1st pressure | voltage fall circuit and the 2nd voltage | voltage fall circuit in Embodiment 3 of this invention. FIG. 6 is a circuit diagram showing a first step-down voltage circuit according to a fourth embodiment of the present invention. FIG. 10 is a circuit diagram showing a first step-down circuit according to a modification of the fourth embodiment of the present invention. It is a figure which shows the pressure | voltage fall circuit part concerning Embodiment 5 of this invention. It is a figure which shows the other example of the pressure | voltage fall circuit part concerning Embodiment 5 of this invention. It is a figure which shows the further another example of the pressure | voltage fall circuit part concerning Embodiment 5 of this invention. It is a figure which shows the step-down circuit provided in the conventional memory and its periphery. It is a figure explaining the overdrive described in patent document 2. FIG.

Explanation of symbols

10, 110 Step-down circuit unit 11, 111 Power supply terminals 12, 12 _{1 to} 12 ₃ First step-down circuit 13, 13 _{1 to} 13 ₄ Second step-down circuit 15 Switching circuit 16, 17 Power supply protection circuit 20 Peripheral logic circuit 21 Memory cell 22 Memory cell array 23 Row decoder 24 Command control unit 25 Column decoder 26 Reference voltage generation circuit 31 I / O interface 32 External terminals 121, 123, 125, 127, 131 Power supply detection circuits 122, 124, 126, 128, 132, driver

Claims (19)

A first step-down circuit for generating a first step-down voltage lower than a power supply voltage supplied from outside;
A second step-down circuit for generating a second step-down voltage lower than the first step-down voltage;
The first step-down circuit has a withstand voltage higher than the power supply voltage, and the second step-down circuit has a withstand voltage higher than the first step-down voltage. The first step-down circuit includes a transistor having a first oxide film thickness,
The semiconductor device according to claim 1, wherein the second step-down circuit includes a transistor having a second oxide film thickness that is smaller than the first oxide film thickness. The semiconductor device according to claim 1, wherein the first step-down circuit supplies a voltage to peripheral logic. The semiconductor device according to claim 1, wherein the second step-down circuit supplies a voltage to the memory cell. A switching circuit that further selects one of the power supply voltage supplied from the outside and the first step-down voltage generated by the first step-down circuit and supplies the selected voltage to the second step-down circuit; The semiconductor device according to claim 1. A first power supply protection circuit connected to the power supply voltage line; and a second power supply protection circuit connected to the first step-down voltage line;
When supplying the power supply voltage to the first step-down circuit, the first power supply protection circuit is turned on. When supplying the power supply voltage to the second protection circuit, the second power supply protection circuit is turned on. The semiconductor device according to claim 5. The first step-down circuit includes a driver and a power supply detection circuit that drives the driver,
The power supply detection circuit is connected in parallel to the first transistor for inputting a reference voltage to the gate and an amplifier having a second transistor that forms a differential pair with the first transistor, and adjusts the first step-down voltage. The semiconductor device according to claim 1, further comprising a voltage adjustment transistor. The second step-down circuit includes a driver and a power supply detection circuit that drives the driver,
The power supply detection circuit includes a first transistor that inputs a reference voltage to a gate, a second transistor that forms a differential pair with the first transistor, and a voltage adjustment transistor that is connected in parallel to the first transistor and adjusts a second step-down voltage. The semiconductor device according to claim 1, wherein the semiconductor device includes: 9. The semiconductor device according to claim 7, wherein a logical sum signal of each overcharge signal corresponding to a plurality of memory banks is input to the voltage adjustment transistor. The semiconductor device according to claim 7, further comprising a current adjustment transistor that adjusts a current flowing through the voltage adjustment transistor. The semiconductor device according to claim 7, further comprising a third transistor that controls on / off of the amplifier. The driver comprises a P-channel MOS transistor,
The semiconductor device according to claim 7, further comprising a forcible drive circuit that forcibly sets a gate voltage of the P-channel MOS transistor. The first step-down circuit includes a driver and a power supply detection circuit that drives the driver,
The power supply detection circuit includes: a first transistor that inputs a reference voltage to a gate; a second transistor that forms a differential pair with the first transistor; a first current source connected to ground; the first current source; A second current source transistor connected between the differential pair and a switching transistor connected in parallel to the second current source transistor and configured to switch whether the second current source transistor is valid or invalid. The semiconductor device according to claim 1, wherein: Further comprising (N-1) transistors connected in parallel to the voltage regulation transistor;
14. The semiconductor device according to claim 7, wherein an overcharge signal corresponding to each of N memory banks is input to the voltage adjustment transistor and (N−1) transistors. A first step-down circuit that is provided in common to a plurality of banks and generates a first step-down voltage lower than the power supply voltage from the power supply voltage;
A second step-down circuit that is individually provided in each bank and generates a second step-down voltage lower than the first step-down voltage from the first step-down voltage;
A plurality of memory banks driven by the second step-down voltage;
The memory in which the first step-down circuit has a withstand voltage higher than the power supply voltage and the second step-down circuit has a withstand voltage higher than the first step-down voltage. A first step-down circuit that supplies the first step-down voltage to peripheral logic and a first step-down circuit that supplies the first step-down voltage to the second step-down circuit are individually provided. The memory of claim 15. The memory according to claim 15 or 16, further comprising the first step-down circuit and the second step-down circuit for each bank of the memory banks. 18. The memory according to claim 15, further comprising a compensation capacitor connected between the first step-down circuit and the second step-down circuit. The memory according to claim 18, further comprising a switch that disconnects the first step-down circuit and the second step-down circuit for a predetermined period.

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