JPH06215571A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a peak current, to accelerate the operation and to reduce a layout area by supplying electric charge from both sides of a capacitor charged to VCC and a power source line to a load when a load circuit is driven. CONSTITUTION:The read operation is started when a signal RASB becomes from 3V to 0V after precharged. A memory signal appears on a data line when a word line WL is received with the RASB and raised from 0V to 4.5V. Q15, Q16 are turned on by that phi2 becomes from 0V to 3V and phi2b becomes from 3V to 0V. The level of CSP is raised to VCC, and the level of CSN is lowered to grounded potential. Thus, an SA is started, and the charge of the data line D1 and the discharge of the D2 are started according to the memory signal. At this time, the charge to the CSP is performed from both sides of the capacitor C1 and the power source line 200. Further, the potential of the CSP is raised to 2.5V. Thus, the conductance of the MOSFET in the sense amplifier becomes large, and the speed of the charge/discharge by the sense amplifier is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor integrated circuit which operates at high speed and low power consumption.

[0002]

2. Description of the Related Art As semiconductor integrated circuits (hereinafter referred to as LSIs) are highly integrated, power consumption increases and element breakdown voltage decreases. In order to deal with this problem, in recent years, there has been a trend toward lowering the power supply voltage of LSIs. On the other hand, due to the strong demand for improvement in the processing speed of computers, the operating speed of LSIs must be increased. As an example of an LSI that operates at high speed even under a low power supply voltage, for example, the digest of
Symposium on VYS SI Circuit (DIGEST OF SYMPOSIUM ON VLSI CIRCUITS 1991)
The circuit schemes described on pages 131 and 132 have been proposed.

The circuit configuration and operation of the above system will be described with reference to FIGS. In FIG. 4, reference numeral 100 denotes a DRAM memory array. MCA is a memory cell array portion, SA is a sense amplifier portion, PCIO is a data line precharge circuit portion, and data from the outside of the chip is written to the memory cell.
It is a switch portion that controls reading of memory cell signals to the outside of the chip. Reference numeral 101 indicates a drive circuit portion of the sense amplifier. The memory array is shown with only one pair of data lines and two word lines for the sake of simplicity.
In the memory cell array, MC is a memory cell, and WL1 and WL2
Is a word line, and D1 and D2 are data lines. In the sense amplifier portion, YS is a data line selection signal, is formed by a Y decoder, IO is a signal line for writing and reading a memory signal from outside the chip, and SAP and SAN are a large number of sense amplifier driving signal lines. The sense amplifier is connected. The drive circuit portion of the sense amplifier is a voltage VDL obtained by stepping down the power supply voltage VCC (3V) supplied from the outside of the chip.
(2V) step-down circuit, MOSFET Q1141, which connects CSP and power supply (VCC) wiring, and MOSFET Q151, CS, which connects the output terminal of the step-down circuit with CSP
It is composed of a MOSFET Q16 for connecting N to the ground wiring. The MOSFETs with arrows are P-channel MOSFETs, and those without arrows are N-channel MOSFETs. The feature of this configuration is that two kinds of voltages are prepared, a high voltage is supplied at the start of the operation of the sense amplifier, the gm of the sense amplifier is increased to speed up the operation, and then a low voltage is supplied to determine the final arrival voltage of the data line. This is intended to reduce power consumption. Next, the read operation of this memory circuit will be described with reference to FIG. RASB is high (Hi
gh, 3V), the memory is in a standby state. At this time, the data lines D1 and D2, the sense amplifier driving signal line CSN,
The CSP is in a precharge state of 1/2 VDL (1V). In addition, all word lines are low (Low, 0V). The operation starts when RASB changes from 3V to 0V. When the word line WL1 rises from 0V to 4.5V, a memory signal appears on the data lines D1 and D2. After that, when φ2 changes from 0V to 3V and φ2B2 changes from 3V to 0V, Q16 and Q1141 are turned on. As a result, CSP is pulled up to VCC (3V) and CSN is pulled down to the ground potential (0V). As a result, SA is driven and the potential of the data line is divided into high and low according to the memory signal. After a certain time, that is, the data line voltage is VD
When approaching L (2V), φ2B2 changes from 0V to 3V, φ
2B1 goes from 3V to 0V, Q1141 turns off, Q1
51 is turned on and VDL is supplied to the CSP. As described above, since VCC is supplied to the sense amplifier at the start of the operation, the gate-source voltage of the P-channel MOSFET of the sense amplifier increases, so that the drive capability of the sense amplifier increases. This speeds up the amplification speed of the memory signal. When the voltage of the data line rises to almost VDL, CSP
The voltage supplied to is switched to VDL, and the voltage of the data line finally becomes VDL.

The conventional example is effective in that the reduction of the operating speed can be suppressed even if the internal operating voltage is lowered in order to reduce the power consumption. However, in this method, the potential of CSP is raised to VCC during the operation of the sense amplifier in order to increase the speed, so that the current Ia flowing into the memory array which is a load at this time becomes very large. Since Ia uses the current Icc flowing from the outside as it is, Icc becomes equal to Ia. This transient current causes a voltage drop due to the inductance and resistance of the power supply wiring in the chip, the inner lead wires in the package, and the wiring on the board. This causes power supply noise and causes malfunction of the LSI on the board or a decrease in operating speed.

[0005]

As described above, the conventional technique is advantageous in terms of high-speed operation, but has a problem that the power supply noise is large and a malfunction is likely to occur. At the same time as driving the load circuit to increase the speed, the potential of CSP is changed to VC
Although it was raised to C, the current flowing into the load at this time was
It has a large peak in proportion to the applied voltage and because it concentrates in a short period of time. This peak current causes a large voltage drop in the power line due to the inductance and resistance components of the pins, lead wires, and wiring on the board. This causes power supply noise, which causes malfunction of the circuit or reduction in speed.

[0006]

To solve the above problems, a load circuit is provided with a capacitor for charging to a first voltage VCC before driving. When driving the load circuit, charges are supplied to the load from both the capacitor and the power supply line. After a certain time, the power supply wiring and the load circuit are disconnected and the power supply voltage VC
A second voltage obtained by stepping down C is supplied.

[0007]

In the above means, the capacitor is charged in advance, and at the start of driving the load circuit, the electric charge to the load is supplied from both the capacitor and the power supply line. Therefore, when viewed from the power source outside the chip, the electric charge is supplied in two steps, and the peak value of the transient current of the external power source becomes small. Therefore,
The voltage drop due to the resistance and inductance of the power supply lines inside and outside the chip is reduced, and the power supply noise is reduced. As a result, malfunction of the LSI on the board and reduction in operating speed can be suppressed.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a first embodiment of the present invention. 1 in FIG.
00 indicates a memory array of DRAM, MCA is a memory cell array portion, SA is a sense amplifier portion, PC
IO is a switch portion for controlling the data line precharge circuit portion and the writing of data from the outside of the chip to the memory cell and the reading of the memory cell signal portion outside the chip. Reference numeral 101 indicates a drive circuit portion of the sense amplifier. The memory array is shown with only one pair of data lines and two word lines for the sake of simplicity. In the memory cell array, MC is a memory cell, WL1 and WL2 are word lines,
D1 and D2 are data lines. YS in the sense amplifier part
Is a data line selection signal, which is created by a Y decoder
Is a signal line for writing and reading a memory signal from outside the chip, and CSP and CSN are drive signal lines for sense amplifiers, to which a large number of sense amplifiers are connected.

In this embodiment, the drive circuit 10 for the sense amplifier is used.
1 is different from the conventional circuit shown in FIG. The sense amplifier drive circuit 101 is a voltage step-down circuit BVD which is connected in parallel with the switching MOSFETs Q2 and Q2 for charging the power supply voltage VCC to the capacitors C1 and C1 and outputs the voltage VDL.
MOSFET for switch connecting L, capacitor C1, output terminal of step-down circuit and sense amplifier drive signal line CSP
It consists of Q15.

The memory signal reading operation of this circuit will be described with reference to the operation waveforms of FIG. When the RASB signal is high (3V) in the memory standby state, the data lines D1 and D2 and the sense amplifier drive signal lines CSN and CSP are precharged to 1 / 2VDL (1V). The word line is at 0V. At this time, in the capacitor C1 of the sense amplifier drive circuit portion 101, the signal φ1B is 0V and VCC (3V) is stored. The read operation starts when the signal RASB changes from 3V to 0V. Receiving RASB, word line WL
When 1 rises from 0V to 4.5V, a memory signal appears on the data line. When φ2 changes from 0V to 3V and φ2B changes from 3V to 0V, Q15 and Q16 are turned on.
This raises the level of CSP towards VCC,
The level of CSN decreases toward ground potential. This activates SA, and the data line D1 is activated in response to the memory signal.
Charging and discharging of D2 begin. At this time, the CSP is charged from both the capacitor C1 and the power supply wiring.
The potential of CSP rises to about 2.5V. Therefore, the conductance of the P-channel MOSFET of the sense amplifier is increased, and the charge / discharge speed of the data line by the sense amplifier is accelerated. Next, φ1B changes from 0V to 3V, and Q2 turns off. After that, the charge of the CSP flows into the high-side data line, and finally both the CSP and the high-side data line become VDL, that is, 2V.

Then, the read operation is completed by changing RASB from 0V to 3V, and the word line is changed from 4.5V to 0V.
It becomes V. Then φ2 changes from 3V to 0V and φ2B changes to 0V
To 3V, the amplification operation of the data line is completed. After that, the data lines D1, D2, the sense amplifier drive signal line CS
P and CSN are charged to 1V by the precharge circuit. On the other hand, φ1B changes from 3V to 0V, Q2 is turned on and the capacitor C1 is charged with 3V.

In FIG. 2, Icc indicates the current flowing through the power supply wiring when the data line is charged. The first peak is the current that charges the data line from the switching MOST Q2 and the voltage step-down circuit through the CSP. The latter peak is the current charging the capacitor C1 through Q2. In the figure, Ia
Is the capacitor C1 due to the charging current of the data line flowing through the CSP.
And the current from the power wiring. Here, the peak value of Icc is smaller than the peak value of Ia. This is because the charge of C1 flows into the data line as a part of Ia.
Therefore, when viewed from the external power supply, the peak value of the transient current Icc can be reduced. As a result, it is possible to reduce the fluctuation of the power supply voltage caused by the parasitic resistance and the parasitic inductance of the power supply wiring as shown in FIG. Therefore, it is possible to prevent the malfunction of the LSI on the same board and the reduction of the operation speed.
Writing to the memory cell is performed through the I / O line and the data line while the sense amplifier is operating.
And the voltage step-down circuit is in the ON state.

FIG. 3 is a result of calculating the peak value of the current Icc flowing through the power supply line by computer simulation when the conventional method and the present invention are applied to the same array. The horizontal axis represents the data line charging time, and the vertical axis represents the peak value of Icc. It can be seen that in the present invention, the peak value of Icc is reduced from 1/2 to 1/3 as compared with the conventional method.

FIG. 6 shows an example of chip layout of the circuit of the present invention. Here, the case where the memory array is divided into four is shown. In the figure, A1 to A4 are divided small memory arrays. 101 is a sense amplifier drive circuit. In the sense amplifier drive circuit, BVDL is a step-down circuit, Q2 is a switch MOSFET, and Q151 to Q154 are also switch MOS.
It is arranged for each memory array divided by the FET.
202 is a common sense amplifier drive wiring. Q1 here
51-Q154 turn on and supply current to them only when the connected memory array is selected.
On the other hand, Q2 is turned on from the precharge period of the memory until just before the data line of the selected array reaches VDL, as in the embodiment of FIG.

In this arrangement, the layout area can be reduced by sharing the sense amplifier drive circuit. Further, here, the capacitor C1 is arranged at one place, but if the capacitors C1 are distributed and arranged in the common sense amplifier drive wiring, the distance between the capacitor and the sense amplifier drive wiring becomes short, so that the parasitic resistance in the common sense amplifier drive wiring becomes small and the speed is higher. Can be converted.

FIG. 7 shows another example of the chip layout of the circuit of the present invention. In this embodiment, a sense amplifier drive circuit is provided for each of the divided small arrays (A1 to A4). A in the figure
1 to A4 are memory arrays. 101 is a sense amplifier drive circuit. BVDL1 to BVDL4 are step-down circuits,
Q201 to Q204 and Q151 to Q154 are switches M
OSFET. In this arrangement, since the memory array and the sense amplifier drive circuit are close to each other, there is an effect that a voltage drop due to resistance of wiring does not occur. Therefore, higher speed operation becomes possible.

FIG. 8 shows an embodiment of the voltage step-down circuit. The voltage step-down circuit is a differential amplifier (Q51 to Q55), an output stage P-channel MOSFET (Q56), and a reference voltage circuit V.
R, a phase compensation circuit CC. This circuit is an amplifier with a gain of 1, and the reference voltage VDL is the output voltage. The differential amplifier is pulse-driven by the signal φ, and power consumption can be reduced by turning off the differential amplifier when the memory is on standby.
Further, the capacitor of the phase compensation circuit can also be used as a part of the peak current reducing capacitor C1 of the first embodiment.

FIG. 9 shows another embodiment of the sense amplifier drive circuit. This embodiment differs from the first embodiment in that two voltage step-down circuits are provided and each is pulse-driven. AMP
Is an output circuit, and WRT is a writing circuit. The voltage step-down circuit has a large load driving capability and a large power consumption BVDL
1. BVDL with low load driving capability but low current consumption
It consists of two. These two voltage step-down circuits are used as follows. In the page mode operation of the DRAM, after the memory signal is latched by the sense amplifier, the data line selection signal YS is sequentially set to the high level to select the data line and read / write the memory signal. In this case, since the selected data lines are one pair or several pairs, the current charged from the CSP may be small. Therefore, until the memory signal is latched for the first time, the current is supplied to the array from Q2 and C1 as in the first embodiment, and Q2 is turned off after a certain period of time to turn off BVDL1.
To supply the step-down voltage. BVD when the latch is completed
Power consumption is reduced by turning off L1 and turning on BVDL2. Although the page mode operation has been described here, the power consumption can be reduced by driving only BVDL2 even in the burst operation mode in which data is sequentially read with RASB being 0V.

FIG. 10 shows another embodiment. This feature is that a plurality of (four in the embodiment) small memory arrays are grouped together (two in the embodiment) to provide a voltage step-down circuit having a large driving capability for each group, and a voltage step-down circuit having a smaller load driving capability. That is, one is provided. In the figure, a to d
Is a small memory array, BVDL2 is a step-down circuit with a small load driving capability, and BVDL1 is a step-down circuit with a large load driving capability. The output of BVDL2 is connected to the outputs of two BVDL1 via Q181 and Q182. here,
φ2BB1 and φ2BB2 are control signals for Q181 and Q182, which are high when the BVDL1 is operating and low when the BVDL1 is not operating. By sharing the BVDL 2 in this way, an increase in the chip area can be suppressed. Further, by providing the BVDL1 for each group of a plurality of small memory arrays, it is possible to suppress an increase in chip area, and at the same time, to prevent a decrease in driving capability of the sense amplifier due to wiring resistance.

Although the voltage of the power supply line is the external voltage VCC in the above description, it may be a voltage different from the VCC generated inside the chip.

[0021]

As shown in FIG. 3, according to the present invention,
The peak value of Icc can be reduced from 1/2 to 1/3 of the conventional value.

[Brief description of drawings]

FIG. 1 is a diagram of a sense amplifier drive circuit of a dynamic memory according to an embodiment of the present invention.

2 is a timing chart of a read operation of the sense amplifier drive circuit of FIG.

FIG. 3 is a characteristic diagram of a circuit according to the conventional method and the circuit according to the present invention.

FIG. 4 is a conventional sense amplifier drive circuit diagram.

FIG. 5 is a timing chart of a read operation of a conventional sense amplifier drive circuit.

FIG. 6 is a circuit diagram showing an example of a layout of an embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of a layout of an embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a differential amplifier according to an embodiment of the present invention.

FIG. 9 is a sense amplifier drive circuit diagram of a dynamic memory according to an embodiment of the present invention.

FIG. 10 is a circuit diagram of an embodiment of the present invention.

[Explanation of symbols]

101 ... Sense amplifier drive circuit, 100 ... Load circuit, B
VDL ... Voltage step-down circuit with large driving capability, BVDL1 ...
Voltage step-down circuit with large drive capacity, Q2 ... C1 set MO
SFET, Q15 ... CSP drive MOSFET, Q16 ...
CSN drive MOSFET, C1 ... Charging capacitance, WL1 ...
Word line, WL2 ... Word line, D1 ... Data line, D2 ...
Data line, MC ... Memory cell, MCA ... Memory cell array, IO ... Output line pair, SA ... Sense amplifier, PCIO ...
Precharge circuit and input / output circuit section, CSP ... MCA
Power line, CSN ... MCA ground line, YS ... Output line switch signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Tanaka 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Yoshinobu Nakagome Tokyo 1-280, Higashi Koigokubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Jun Eto 1-280, Higashi Koigokubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (72) Kazuyuki Miyazawa 2326 Imai, Ome City, Tokyo Address, Hitachi, Ltd. Device Development Center (72) Inventor, Yukie Hide Suzuki, 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo, Hiratsuka ELS Engineering Co., Ltd. (72) Inventor, warrior Tatsunori Tokyo 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Alling Co., Ltd. (72) Inventor Masakazu Aoki 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (72) Inventor Takashi Ebihara 5-20-1, Kamimizumoto-cho, Kodaira-shi, Tokyo Hiritsu Super LSI Engineering Co., Ltd.

Claims (5)

[Claims] 1. A power supply line that supplies a voltage of an arbitrary level, a voltage step-down means that is connected to the power supply line and outputs a voltage lower than the voltage, a capacitor connected to the output, between the power supply line and the output. A first switch means provided in
And a load drive circuit including second switch means provided between the output and the load circuit, wherein the first switch means is turned on before the load circuit is driven to charge the capacitor with the power supply voltage. , The second switch means is turned on when the load circuit is driven to supply a current to the load circuit, and the first switch means is turned on immediately before the output voltage of the load circuit reaches the output voltage of the voltage step-down circuit. A semiconductor integrated circuit characterized by being turned off. 2. The semiconductor integrated circuit according to claim 1, wherein the voltage of the power supply line is an external power supply voltage. 3. A semiconductor integrated circuit according to claim 1, wherein a plurality of said voltage step-down circuits having different driving capabilities are provided and their outputs are connected directly or by means of resistors or switch means. 4. The load switch circuit according to claim 1, wherein a plurality of the second switch means are provided, the load circuits are connected to each of the second switch means, and the second switch means connected to the load circuit is selectively operated when the load circuits are driven. A semiconductor integrated circuit that turns on. 5. A semiconductor integrated circuit according to claim 1, which has the plurality of load drive circuits and the plurality of load circuits connected to the load drive circuits and which selectively operate.