JPH07211895A - Conductivity modulation type field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a high-speed conductivity modulation field-effect transistor in which accumulated carriers have shorter lifetime by forming a p-type drain region and/or an n-type buffer region from polycrystalline or amorphous semiconductor silicon in which carrier lifetime is shorter than in a single-crystal silicon of the same impurity concentration. CONSTITUTION:A conductivity modulation type field-effect transistor 4 comprises a p-type drain region 21, an n-type buffer region 22, an n-type drain drift region 23, a p-type base region 24, and an n-type source region 25. The n-type drain drift region 23, the p-type base region 24, and the n-type source region 25 are formed of single-crystal silicon. The p-type drain region 21 and/or the n-type buffer region 22 is formed of polycrystalline or amorphous semiconductor silicon in which carrier lifetime is shorter than in a single-crystal silicon of the same impurity concentration. This structure improves operating speed without substantial deterioration of its characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductivity modulation type field effect transistor, and more particularly to a conductivity modulation type field effect transistor whose speed is increased.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional conductivity modulation type field effect transistor element (hereinafter simply referred to as a semiconductor element).
As shown, an N ⁺ type buffer region 2 and an N type drain drift region 3 are sequentially stacked on the upper surface of the P type drain region 1, and a P type base region 4 and an N type source region 5 are formed on the surface of the N type drain drift region 3. Is provided with a semiconductor substrate 6 composed of island-shaped single crystal silicon. Semiconductor substrate 6
The insulator layer 7, the gate electrode 8, the gate wiring electrode 9, and the source wiring electrode 10 are formed on one main surface, and the drain electrode 11 is formed on the other main surface.

In the above semiconductor device, when a voltage is applied to the gate electrode 8 to form a channel inversion layer on the surface of the base region 4 to make it conductive, electrons injected from the source region 5 through the channel inversion layer are drained. It is accumulated in the drift region 3. Along with this, the drain regions 1 and N
The PN junction between the ⁺ buffer regions 2 is forward biased and holes are injected from the drain region 1. As a result,
Electrons and holes are injected into the drain drift region 3 to modulate the conductivity and reduce the on-resistance.

[0004]

By the way, in the above semiconductor device, a so-called "tailing" phenomenon in which a relatively small current continues to flow in a tailing manner in the final stage of the off process (hereinafter, simply referred to as "tail"). There was a drawback. For this reason, it has been a hindrance to improvement of the switching-off characteristic, which has been a major obstacle to speeding up.
That is, when the voltage applied to the gate is set equal to or lower than the threshold voltage to turn off the semiconductor element, the channel inversion layer generated on the surface portion of the base region 4 disappears and electrons are injected from the source region 5 to the drain drift region 3. Stops. When the channel current starts to decrease, the potential of the drain drift region 3 becomes high, and the depletion layer based on the PN junction between the P-type base region 4 and the N-type drain drift region 3 having a lower impurity concentration than this is mainly drain. It spreads to the drift region 3 side. Therefore, the accumulated carriers (electrons and holes) in the drain drift region 3 are discharged to the P-type drain region 1 and the P-type base region 4. Therefore, the current continues to flow in the external circuit during the discharge period of the accumulated carriers. When almost all of the power supply voltage is applied to the semiconductor element and the depletion layer spreads to the maximum, the drain current sharply decreases. However, until the carriers in the drain drift region 3 where the depletion layer has not spread and the carriers in the N ⁺ -type buffer region 2 disappear by recombination, a small current continues to flow in a trailing manner, and a tail is generated. In order to suppress this tail, it is conceivable to increase the impurity concentration of the N ⁺ type buffer region 2 to shorten its lifetime. However, if the impurity concentration of the N ⁺ type buffer region 2 is too high, the injection of holes from the drain region 1 is suppressed and the desired conductivity modulation effect cannot be obtained. Therefore, there is a limit to increase the impurity concentration, and it has not been possible to achieve a sufficient speedup.

Therefore, an object of the present invention is to provide a conductivity modulation type field effect transistor which can realize high speed operation without substantially lowering other characteristics.

[0006]

The present invention for achieving the above object will be described with reference to the reference numerals of the drawings showing the embodiments. One of the first conductivity type drain region 21 and the drain 21 is provided. The second opposite to the first conductivity type adjacent to the main surface of the
Conductivity type buffer region 22 and the buffer region 22
The drain drift region 2 of the second conductivity type adjacent to the drain region 2 and having a lower impurity concentration than the buffer region 22.
3, a first conductivity type base region 24 adjacent to the drain drift region 23 and formed on the surface of the substrate so that a part of the drain drift region 23 is exposed and the base region 24. On a surface of a portion of the base region 24 between the drain drift region 23 and the source region 25, which has a second conductivity type source region 25 formed so as to be exposed to the substrate surface. A gate electrode 27 is disposed on the substrate via an insulator layer 26, the base region 24 and the source region 25 are electrically connected to a source electrode 29, and the drain region 21 is electrically connected to a drain electrode 30. In the conductivity modulation type field effect transistor which is electrically connected, the drain drift region 23, the base region 24 and the source region 25 are made of a single crystal. A polycrystalline silicon semiconductor or an amorphous silicon semiconductor that is made of a semiconductor and has one or both of the drain region 21 and the buffer region 22 having a carrier lifetime shorter than that of a single crystal silicon semiconductor having the same impurity concentration. The present invention relates to a conductivity modulation type field effect transistor made of a porous silicon semiconductor.

[0007]

According to the present invention, one or both of the drain region 21 and the buffer region 22 are formed of a polycrystalline silicon semiconductor or an amorphous silicon semiconductor having a shorter lifetime than a single crystal silicon semiconductor. Therefore, the disappearance time of accumulated carriers is shorter than that of a conventional field effect transistor formed of a single crystal silicon semiconductor, and the speed can be increased. Since the main part of the field effect transistor is a single crystal silicon semiconductor as in the conventional case, deterioration of various characteristics does not substantially occur as compared with the conventional case.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A conductivity modulation type field effect transistor device (hereinafter simply referred to as a semiconductor device) according to an embodiment of the present invention will be described with reference to FIGS. The semiconductor device of this embodiment is characterized in that the P-type drain region 1 and the N ⁺ -type buffer region 2 of the conventional semiconductor device shown in FIG. 1 are formed by using a polycrystalline silicon semiconductor. That is, the semiconductor device of this embodiment, a drain made of P ⁺ -type poly-from crystalline silicon semiconductor on the upper surface of the drain region 21 made of N ⁺ -type polycrystalline silicon semiconductor N ⁺ -type buffer region 22 and the N-type single crystal silicon semiconductor It has a structure in which the drift regions 23 are sequentially stacked. Drain drift region 23
A large number of base regions 24 made of a P-type single crystal silicon semiconductor are formed on the surface of the so as to be scattered in an island shape at a predetermined interval. The base region 24 has a structure in which the center side is formed relatively deep. Inside the base region 24, a source region 25 is formed in an annular shape along the edge of the base region 24. The source region 25 is a region made of a single crystal silicon semiconductor like the base region 24. The lifetimes of carriers in the P-type drain region 21 and the N ⁺ -type buffer region 22 made of a polycrystalline silicon semiconductor are shorter than the lifetimes of carriers in a single crystal silicon semiconductor having the same impurity concentration as those.

Source region 25 and drain drift region 2
An insulating layer 26 made of a silicon oxide film is formed on the surface of the base region 24 (on the channel inversion layer) between the first and second regions 3 and on the surface of the drain drift region 23 exposed in a lattice pattern between the plurality of base regions 24. A gate electrode 27 made of polycrystalline silicon is formed therethrough.

The upper surface of the gate electrode 27 is electrically connected to a gate wiring electrode 28 made of aluminum and formed in a strip shape. Source region 2 exposed from insulator layer 26
5 and the center side of the base region 24 are electrically connected to a source wiring electrode 29 made of aluminum and formed in a strip shape. Further, on the lower surface of the drain region 21, Ti, N
Drain electrode 3 formed by laminating metals such as i, Pd, and Au
0 is formed.

The above semiconductor device is manufactured, for example, as follows. First, as shown in FIG. 4, the drain region 21
On the upper surface of the P ⁺ -type polycrystalline silicon semiconductor substrate that constitutes the
First semiconductor substrate 3 having N ⁺ type buffer region 22 formed by epitaxially growing ⁺ type polycrystalline silicon semiconductor
Prepare 1. The N ⁺ type buffer region 22 can also be formed by introducing N type impurities into the upper surface of the P ⁺ type polycrystalline silicon semiconductor substrate by diffusion or the like.

Next, as shown in FIG. 4, an N-type single crystal silicon semiconductor substrate (second semiconductor substrate) 32 constituting the drain drift region 23 is directly bonded and integrated on the upper surface of the first semiconductor substrate 31. To do. This bonding is performed, for example, on both substrates 3
This can be achieved by mirror-bonding the bonding surfaces of Nos. 1 and 32 and superimposing them, and subjecting them to heat treatment. Instead of this junction, for example, the polycrystalline N ⁺ type buffer region 22 and the P type drain region 21 can be formed on the single crystal silicon semiconductor substrate for the drain drift region 23 and the like by a vapor phase growth method.

Next, a base region 24 and a source region 25 are formed on the surface of the drain drift region 23 by the well-known DSA technique, and further electrodes 28 to 30 are formed by sputtering, vacuum deposition or the like to complete the device of FIG. Let

The semiconductor device of this embodiment has the following actions and effects. (1) Since both the drain region 21 and the buffer region 22 are formed of a polycrystalline silicon semiconductor having a shorter carrier lifetime than a single crystal silicon semiconductor,
The tail period can be shortened by shortening the disappearance time of accumulated carriers without taking measures such as diffusion of heavy metals. Also,
Drain drift region 23 that predominantly determines other characteristics
Since is made of a single crystal silicon semiconductor as in the conventional case, these characteristics are not substantially deteriorated. As a result, it is possible to provide an element which has been accelerated while maintaining various characteristics. Even if only the buffer region 22 is a polycrystalline silicon semiconductor, the effect of shortening the tail period can be obtained to some extent. However, with this structure, the annihilation time of the electrons injected into the drain region 21 is not shortened, and the remarkable shortening effect as in this embodiment cannot be obtained. (2) The lifetime of the buffer region 22 is shortened by the material itself, so that the lifetime can be shortened to the same level as it is increased without increasing the impurity concentration. Therefore, the tail period can be shortened without making hfe of the parasitic transistor so low, and both reduction of on-resistance and high speed can be improved to a level that is practically satisfactory. The buffer area 2
In the structure in which only 2 is a polycrystalline silicon semiconductor, if the impurity concentration of the buffer region 22 is reduced, the drain region 2
Since electron injection into 1 increases and there is a tail resulting from this, it is difficult in design to improve both on-resistance reduction and high speed to a satisfactory level. (3) Since the polycrystalline silicon substrate is inexpensive, the cost of the device can be reduced even if the joining technique of the substrates is taken into consideration.

[0015]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) Buffer region 22 in the semiconductor device of FIG.
As shown in FIG. 5, the N ⁺ type region 2 having a high impurity concentration
2a and N-type regions 22b having an impurity concentration lower than that may be alternately formed. According to this element structure, since holes are injected from the drain region 21 through the N-type region 22b as a seed, the impurity concentration of the N ⁺ -type region 22a is increased without disturbing the conductivity modulation. It is possible to shorten the lifetime and improve the switching-off characteristics. Note that this element structure can be formed by selectively diffusing N-type impurities into the buffer region 22. (2) As shown in FIG. 6, the buffer area 22 of FIG.
The structure may be such that N ⁺ type regions 22a and P type regions 22c made of a polycrystalline silicon semiconductor are alternately formed. Even with this element structure, the same effect as that of the element of the modification (1) can be obtained. The N ⁺ type region 22a of FIG. 6 can be formed by selectively diffusing N type impurities into the P type drain region 21 of polycrystalline silicon. The N ⁺ type regions 22a in FIGS. 5 and 6 may be distributed in a large number of islands, or may be distributed in a lattice or mesh. (3) In the embodiment, the example in which the drain region 21 and the buffer region 22 are made of a polycrystalline silicon semiconductor layer is shown, but this may be replaced with an amorphous silicon (amorphous silicon) layer. Since the lifetime of electrons is small even in amorphous silicon, the same operational effect as in the case of using polycrystalline silicon can be obtained. Amorphous silicon can be easily formed by lowering the growth temperature. (4) Although an N-channel type is shown in the embodiment, it can also be used as a P-channel type in which the conductivity type of the semiconductor region is opposite. (5) A lifetime killer such as Au may be introduced to further increase the speed. In the present invention, the drain region 21 and the buffer region 2 of polycrystalline silicon are based on the difference in the diffusion coefficient between polycrystalline silicon and a single crystal silicon, which are lifetime killer (a substance that shortens the lifetime of metal).
2 can introduce a lifetime killer selectively. Therefore, it is possible to further speed up without deteriorating various characteristics. (6) The base region 24 can be formed in a lattice shape or a mesh shape.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a conventional field effect transistor.

FIG. 2 is a cross-sectional view showing a field effect transistor according to an embodiment of the present invention at a portion corresponding to line AA in FIG.

FIG. 3 is a plan view showing an arrangement of respective regions on a surface of a semiconductor substrate of the field effect transistor of FIG.

FIG. 4 is a cross-sectional view showing the method of manufacturing the field effect transistor of FIG.

FIG. 5 is a cross-sectional view showing a modified example of the buffer area 22.

FIG. 6 is a cross-sectional view showing another modification of the buffer area 22.

[Explanation of symbols]

 21 Polycrystalline Silicon Drain Region 22 Polycrystalline Silicon Buffer Region 24 Single Crystal Silicon Base Region 25 Single Crystal Silicon Source Region

Claims (1)

[Claims] 1. A drain region (21) of the first conductivity type.
And a buffer region (2) of a second conductivity type opposite to the first conductivity type adjacent to one main surface of the drain region (21).
2), a second conductivity type drain drift region (23) adjacent to the buffer region (22) and having a lower impurity concentration than the buffer region (22), and the drain drift region (23). ) And a first conductivity type base region (24) formed on the surface of the substrate so that a part of the drain drift region (23) is exposed together with the base region (24). A source region (25) of a second conductivity type is formed adjacent to and exposed to the surface of the substrate, and the drain drift region (23) and the source region (2) of the base region (24).
The gate electrode (27) is disposed on the surface of the portion between the electrodes (5) through the insulator layer (26), and the base region (24) and the source region (25) are the source electrode (2).
9) electrically connected to the drain region (2
1) is a conductivity modulation type field effect transistor electrically connected to a drain electrode (30), wherein the drain drift region (23), the base region (24) and the source region (25) are single crystals. The drain region (21) and the buffer region (22) are made of a silicon semiconductor.
And either or both of them are composed of a polycrystalline silicon semiconductor or an amorphous silicon semiconductor having a carrier lifetime shorter than that of a single crystal silicon semiconductor having the same impurity concentration. Field effect transistor.