JPH07210131A - Image processor, data processor and data processing system - Google Patents

Abstract

PURPOSE:To enable the plotting with excellent memory access efficiency by constituting so that the data of plural pixels are processed by readout, renewal, write processes. CONSTITUTION:The font data are expanded by a data expansion circuit 1402 according to a GBM signal, and are shifted to a bit position shown by a pixel address of a write party by a barrel shifter 1404 to be stored in a DLC 11405, and are synthesized, and information corresponding to the write data is generated to be sent to an LU 1416. Then, a kind of logical operation is selected by a mode specified by a DM 1411, and the specification of non-operation is performed in bit. The write party data are outputted in the non-operation, and by specifying the bit performing no write by a non-operation signal, it corresponds to even the case that the bit performing no write exists in one word. This system is constituted so that the output of the LU 1416 is set to a WDBR 1417, and the write and write party data are large/small decided for the non-operation signal, and the plotting is performed without injuring a background of a character.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device, a data processing device and a data processing system, and more particularly to a device suitable for improving the processing speed of the image processing device.

[0002]

2. Description of the Related Art A conventional apparatus is disclosed in Japanese Patent Application No. 58-24698.
As described in No. 6, a pixel address composed of address information designating an address of the image memory and pixel position designating information designating a pixel position in one word designated by the address is sequentially calculated, and the pixel address is calculated. The image data of one word designated by the address information of the pixel address is read from the image memory, and then a plurality of bit positions corresponding to designated pixel positions formed by decoding based on the pixel position designation information of the pixel address are designated. With the information, the drawing logical operation is performed only on a predetermined bit representing one pixel of the read image data, and the result of this logical operation is written again in the image memory and displayed.

[0003]

In the above-mentioned prior art, in the image data of one word in the image memory, the processing performance is considered to be equivalent to that of a binary image regardless of the number of bits forming one pixel. However, when the image data of one word in the image memory has information of a plurality of pixels, no consideration is given to processing these plurality of pixels in parallel at the same time. When processing a plurality of pixels consecutively, the image data of the same address in the image memory must be accessed and processed a plurality of times, which causes a problem that the processing speed becomes slow.

An object of the present invention is to expand font data consisting of binary information into a plurality of (n) -bit pixel data containing color or gradation information, and to extend a plurality of (m) pixels in one word of a processing unit. It is an object of the present invention to provide an image processing apparatus capable of processing at a high processing speed almost the same as in the case of a single pixel, and a data processing apparatus and a data processing system equipped with the apparatus even in the case of having a.

[0005]

SUMMARY OF THE INVENTION In the image processing device according to the present invention, the object is to set font data consisting of binary information and pixel data consisting of a plurality of (n) bits containing color or gradation information to one. An image memory that stores image data in which a plurality of (m) pixels are divided into word lengths, and different color or gradation information set corresponding to binary information of font data are associated with m pixels. 1 and a second color register each having a length of 1
And a processing device including a process for expanding font data consisting of value information to n-bit pixel data containing color or gradation information, the processing device comprising font data corresponding to m pixels to be processed. From the image memory, copy the font data for each pixel into n bits, and extend the data to 1 × word length data of m × n bits, and a 1-word length extended by the bit data extension means. A corresponding m × n multiplexer for selecting the corresponding first or second color register in accordance with the binary information for each bit and outputting the information of the bit at the same position of the selected color register. It can be achieved by writing the output information of the multiplexer in an image data area in the image memory.

[0006]

In the operation of the image processing apparatus according to the present invention, color or gradation information corresponding to any one of binary information of font data is stored in advance in the first and second color registers for m pixels. It

The bit data expansion means copies 1-bit font data for each pixel and expands it to n bits. That is, the n-bit font data of each pixel consists of the same data.

Therefore, the multiplexer selects the first or second color register for each bit, but it is substantially the same as selecting the color register on a pixel-by-pixel basis. Moreover, since the processing is performed in parallel for a plurality of pixels, image data for m pixels is simultaneously generated.

As a result, the processing of the image data consisting of a plurality of pixels can be performed within the same time as the processing of a single pixel, and the speed of the image processing can be increased.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an image processing apparatus according to an embodiment of the present invention. The processing device 10 is connected to a central control unit (CPU) 11 on the one hand and to an image memory 12 consisting of a font data area and a display area on the other hand. The image memory 12 is connected to the display device 14 via the display conversion device 13.

The processing unit 10 is composed of an arithmetic unit 100 for reading, rewriting and writing data in the image memory 12, and a control unit 110 for controlling the arithmetic unit 100 in a fixed order. Further, the arithmetic device 100 is divided into a logical address arithmetic unit 120, a physical address arithmetic unit 130, and a color data arithmetic unit 140.

The data stored in the font data area of the image memory 12 is stored in the arithmetic unit 10 of the processor 10.
0, that is, the logical address calculation unit 120 mainly calculates where the drawing point is on the screen according to the drawing algorithm, the physical address calculation unit 130 calculates the address, and the color data calculation unit 140 calculates the address. Calculates the color data to be written in the image memory 12. The calculation result by the arithmetic unit 100 is sent to the display area of the image memory 12 again according to an instruction from the central control unit (CPU) 11. The data in the image memory 12 is converted into display data by the display conversion device 13 and sent to the display device 14.

Next, basic matters relating to the image processing apparatus according to this embodiment will be described with reference to FIGS. FIG. 3 shows 1 in each pixel mode of the image memory 12.
FIG. 4 is a diagram showing a bit configuration of a word, FIG. 4 is a diagram showing pixel addresses corresponding to respective pixel modes, and FIG. 5 is a diagram showing a spatial arrangement of the image memory 12.

First, five types of pixel modes can be selected. That is, each pixel mode shown in FIGS. 3 (a) to 3 (e).

(A) 1-bit / pixel mode This is a mode used when 1 pixel is represented by 1-bit like a black and white image, and 1 word of the image memory 12 contains data of 16 consecutive images. It is stored. A GBM signal “000” indicating the number of bits forming one pixel
It corresponds to. (B) 2 bits / pixel mode This is
One pixel is represented by 2 bits, and 4 colors or 4
Used for displaying up to gradation. Therefore, the image memory 12
Data of 8 consecutive pixels are stored in one word.
The GBM signal is "001".

(C) 4 bits / pixel mode In this, one pixel is expressed by 4 bits, and one word of the image memory 12 stores data of four consecutive pixels. The GBM signal is "010".

(D) 8-bit / pixel mode This is for expressing one pixel by 8 bits, and one word of the image memory 12 stores data for two pixels. The GBM signal is "011".

(E) 16 bits / pixel mode In this, one pixel is expressed by 16 bits, and one word in the image memory 12 corresponds to one pixel data. The GBM signal is "100".

Secondly, pixel address is adopted.
This pixel address is, as shown in FIG. 4, address information MAD designating the address of the image memory 12,
It is composed of pixel position designation information WAD for designating which position within one word designated by the address. The pixel position designation information WAD is provided as a bit address, that is, a physical address in the lower 4 bits of the pixel address, and is calculated by the physical address calculation unit 130. The lower 4-bit pixel position designation information WAD is used to designate the pixel position within one word, and operates according to each bit / pixel mode. The "*" mark in FIG. 4 indicates that the bit is irrelevant to the operation.

Third, the address information MA of the pixel address
The image data of one word at the address of the image memory 12 designated by D is read from the image memory 12,
Next, based on the pixel position designation information WAD of the image address, the GBM signal indicating the number of bits forming one pixel, and the information indicating the number of pixels to be updated, only a predetermined bit portion of the image data is rewritten, Further, the rewritten image data is written in the address of the image memory 12 so that a plurality of bits for one pixel or a plurality of pixels are simultaneously processed in parallel.

The spatial arrangement of the image memory 12 when the pixel mode is 4 bits / pixel mode is shown in FIG. The address of the image memory 12 is attached as a linear address as shown in the memory map of FIG. 5 (A), and this is displayed as a two-dimensional image as shown in FIG. 5 (B). The horizontal axis MW of the screen indicates how many bits the horizontal width of the screen is composed of. Therefore, in the 4-bit / pixel mode, MW / 4 pixels are displayed in the horizontal direction. Since one pixel is displayed by 4 bits, the data of one word is displayed as data of four pixels which are continuous in the horizontal direction as shown in FIG. 5 (c).

To move the physical address by one pixel in the horizontal direction, the number of bits constituting one pixel may be added or subtracted, and to move one pixel in the vertical direction, the value of MW may be added or subtracted. Further, when processing a plurality of pixels for one word, the number of bits of one word may be added or subtracted.

Based on the above basic matters, the main part of the image processing apparatus according to this embodiment will be described.

FIGS. 1 and 6 are block diagrams showing the main parts of the image processing apparatus according to this embodiment.
In FIG. 1, the font data area of the image memory 12 is connected to the input of the color data calculation section 140 of the processing device 10, and the output of the color data calculation section 140 is connected to the display area of the image memory 12.

Further, referring to FIG. 6, the color data calculation unit 140 includes a font data register (FDR) 140.
1, data expansion circuit 1402, source latch (SLSF
T) 1403, barrel shifter (BARREL SFT)
1404, destination latch 1 (DLC1) 1
405, destination latch 2 (DLC2) 14
06, color register 0 (CL0) 1407, color register (CL1) 1408, multiplexer (MPX)
1409, graphic mask register (GMAS
K) 1410, drawing mode register (DM) 1
411, color data comparator (CLCMP) 1412, coincidence detection circuit 1413, condition determination circuit 1414, signal expansion circuit 1415, logical operation unit (LU) 1416, write data buffer (WDBR) 1417, read data buffer (RDBR) 1418, And a memory address register (MAR) 1419.

Next, the operation will be described with reference to FIGS. 7 to 9. First, a character pattern is stored in the font data area of the image memory 12 as a binary bit pattern consisting of "0" and "1" signals, that is, font data. Then, this font data is input to the color data calculation unit 140 from the font data area.

The input font data is first read out from the read data buffer (RDB) of the color data calculation unit 140.
R) 1418, and further stored in the font data register (FDR) 1401. Next, the stored font data is expanded by the data expansion circuit 1402 according to the GBM signal indicating the number of bits forming one pixel. For example, as shown in FIG. 7, each 1 bit of font data is expanded to 4 bits and stored in the source latch (SL SFT) 1403. This extended data is barrel-shifted (BARREL SF) in order to perform bit alignment with the write destination data.
T) 1404 is used to shift to the bit position indicated by the pixel address of the write destination. The result of this shift is
The data is temporarily stored in the destination latch 1 (DLC1) 1405, the data of (M) and (S) are combined, and the information corresponding to the write data is generated.

Further, it is determined whether the font data is a "0" signal or a "1" signal for each 1 bit. If the "0" signal, the value of the color data 0 is determined, and if the "1" signal, the color data 1 is determined. The value is selected. The values of color data 0 and color data 1 are respectively stored in color register 0 (CL0) 140.
7 and color register 1 (CL1) 1408. And the destination latch 1 (DLC
1) The data combined in 1405 is used as a signal for selecting color data 0 and color data 1 stored in these color register 0 (CL0) 1407 and color register 1 (CL1) 1408, respectively. As shown in FIG. 8, the multiplexer 1409 for selecting 1 bit is used for one word, and the color register 0
(CL0) 1407 and color register 1 (CL1)
Color data 0 and color data 1 respectively stored in 1408 are stored in the destination latch (DLC).
1) Based on the data 1405, each corresponding bit is independently selected, and write data is obtained.

The write data has a logical operation unit (LU) 1416 for performing a logical operation with the write destination data.
Sent to. The logical operation unit (LU) 1416 can select the type of logical operation according to the mode specified by the drawing mode register (DM) 1411 and can specify no operation in bit units. In the case of no calculation, the write destination data is output as it is. Therefore, by designating the bit which is not rewritten by the non-operation signal, it is possible to deal with the case where there is a bit which is not rewritten in one word. This non-computation signal is set in the graphic mask register (G MASK) 1410 by the control device 110 based on the GBM signal and information on the number of pixels to be processed. The output data of the logical operation unit (LU) 1416 is set in the write data buffer (WDBR) 1417 and written in the display area of the image memory 12.

An output signal from a color condition comparator composed of a color data comparator (CLCMP) 1412, a coincidence detection circuit 1413, a condition judgment circuit 1414 and a signal expansion circuit 1415 is connected to the non-calculation signal, The write data and the write destination data are grouped in units of pixels for one word, and the size is judged, and the drawing mode register (D
M) By making each bit of a pixel that does not match the condition specified by 1411 a no-operation signal, it is possible to draw without damaging the background color of the character.

Color condition comparator and logical operation unit (LU) 141
In the relationship of No. 6, as shown in FIG. 9, the color data comparator (CLCMP) 1412 of the color condition comparator regards the bits in one pixel as a binary code and judges the size of each pixel, If it is satisfied, a "1" signal is output, and if not satisfied, a bit of a "0" signal is output, and the logical operation unit (L
The U) 1416 performs a logical operation only on the "1" signal portion of the determination output bit, and transfers the result to the write destination.

In the data thus transferred to the display area of the image memory 12, the font data stored in the font data area of the image memory 12 is binary, whereas
It is multivalued, for example, converted into 4 bits / pixel as shown in FIG.

As described above, according to this embodiment, data of a plurality of pixels can be processed at once by one read, update, and write process, so that drawing with high memory access efficiency can be performed. Further, since the expansion of the font can be controlled according to the bit length of one pixel, the configuration has high versatility.

[0035]

According to the present invention, when the font data consisting of binary information is expanded to a plurality of bits of pixel data containing color or gradation information, it is used in units of a plurality of pixels forming one word of image data. Can be done at the same time. As a result, since the image data can be processed in a unit of a plurality of pixels forming one word in one processing, it is possible to obtain an effect of speeding up the image processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an image processing apparatus according to an embodiment.

FIG. 2 is a block diagram showing an overall configuration of an image processing apparatus according to an embodiment.

FIG. 3 is a diagram showing a bit layout of image data used in the image processing apparatus according to the embodiment.

FIG. 4 is a diagram showing a bit layout of a pixel address used in the image processing apparatus according to the embodiment.

FIG. 5 is a diagram for explaining the operation of the image processing apparatus according to the embodiment.

FIG. 6 is a block diagram showing a color data calculation unit of the image processing apparatus according to the embodiment.

FIG. 7 is a diagram for explaining the operation of the image processing apparatus according to the embodiment.

FIG. 8 is a diagram for explaining the operation of the image processing apparatus according to the embodiment.

FIG. 9 is a diagram for explaining the operation of the image processing apparatus according to the embodiment.

[Explanation of symbols]

 10 processing device 11 central control device 12 image memory 13 display conversion device 14 display device 100 arithmetic device 110 control device 120 logical address arithmetic unit 130 physical address arithmetic unit 140 color data arithmetic unit 1401 font data register 1402 data expansion circuit 1403 source latch 1404 Barrel shifter 1405 Destination latch 1 1406 Destination latch 2 1407 Color register 0 1408 Color register 1 1409 Multiplexer 1410 Graphic register 1411 Drawing mode register 1412 Color data comparator 1413 Match detection circuit 1414 Condition determination circuit 1415 Signal extension circuit 1416 Logical operation unit 1417 Write data buffer 1418 Read data buffer 141 Memory address register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Sato 1450 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Masahiko Kikuchi 3-2-1 Sachimachi, Hitachi, Ibaraki Hitachi Inside Engineering Co., Ltd.

Claims (3)

[Claims] 1. Font data consisting of binary information and image data obtained by dividing a plurality of (n) pixel data including color or gradation information and consisting of a plurality (n) bits into one word length are stored. Image memory and different color or gradation information set corresponding to the binary information of the font data are stored corresponding to m pixels, respectively, and the first and second color registers of one word length are stored. And a processing device including processing for expanding font data composed of binary information to n-bit pixel data containing color or gradation information, wherein the processing device The font data corresponding to the target m pixels is fetched from the image memory, the font data for each pixel is copied to n bits, and m × n bits of 1
Bit data expansion means for expanding to word length data, and the first or second corresponding corresponding to binary information for each bit of one word length expanded by the bit data expansion means.
And a multiplexer of m × n that outputs the information of the bit at the same position of the selected color register, and outputs the output information of the multiplexer to the image data area in the image memory. An image processing device characterized by writing. 2. Font data composed of binary information and image data composed of pixel data composed of a plurality of (n) bits containing color or gradation information and divided into a plurality of (m) pixels into one word length are stored. Image memory and different color or gradation information set corresponding to the binary information of the font data are stored corresponding to m pixels, respectively, and the first and second color registers of one word length are stored. And a central processing unit connected to the processing unit, the processing unit including a process for expanding the font data consisting of binary information to n-bit pixel data containing color or gradation information; A data processing device comprising a display conversion device for converting image data in the image data into display data, wherein the processing device outputs font data corresponding to m pixels to be processed from the image memory. Capture , 1 m × n-bit font data for each pixel is copied to the n-bit
Bit data expansion means for expanding to word length data, and the first or second corresponding corresponding to binary information for each bit of one word length expanded by the bit data expansion means.
And a multiplexer of m × n that outputs the information of the bit at the same position of the selected color register, and outputs the output information of the multiplexer to the image data area in the image memory. A data processing device characterized by writing. 3. Font data consisting of binary information and image data obtained by dividing a plurality of (n) pixel data containing color or gradation information into a plurality of (m) pixels into one word length are stored. Image memory and different color or gradation information set corresponding to the binary information of the font data are stored corresponding to m pixels, respectively, and the first and second color registers of one word length are stored. And a central processing unit connected to the processing unit, the processing unit including a process for expanding the font data consisting of binary information to n-bit pixel data containing color or gradation information; In a data processing system comprising a display conversion device for converting image data in the display data into display data, and a display device for outputting the display data converted by the display conversion device as an image, The processing The apparatus fetches font data corresponding to m pixels to be processed from the image memory, copies the font data for each pixel into n bits, and outputs m × n bits of 1
Bit data expansion means for expanding to word length data, and the first or second corresponding corresponding to binary information for each bit of one word length expanded by the bit data expansion means.
And a multiplexer of m × n that outputs the information of the bit at the same position of the selected color register, and outputs the output information of the multiplexer to the image data area in the image memory. A data processing system characterized by writing.