JPH07202147A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a flexible semiconductor device which is thinner than a prescribed value and high enough in strength by a method wherein an amorphous insulating layer is laminated on the upside and underside of a semiconductor integrated circuit where an active device provided with a single crystal Si thin film as an active layer is built in. CONSTITUTION:An N-MOS Tr 15 and re P-MOS Tr 16 are isolated from each other by a LOCOS layer 3, and moreover an Al wiring 22 is provided for forming a C-MOS inverter 19. An interlayer insulating layer 20 interposed between the Al wiring 22 and a gate wiring is formed of BPSG as thick as 4000Angstrom , and a last passivation layer 30 is formed of PSG as thick as 10000Angstrom . A wiring lead-out section 31 is provided by removing a part of the passivation layer 30, and a P-MOS Tr 17 is formed to serve as an output buffer. The thickness of this semiconductor device is represented by a formula, insulating layer 2 (8000Angstrom ) + LOCOS layer 3 (10000Angstrom ) + interlayer insulating film 20 (6000Angstrom ) + passivation layer 30 (6000Angstrom ) = 36000Angstrom .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-thin semiconductor device, and more particularly to a thin and flexible semiconductor device which is resistant to bending.

[0002]

2. Description of the Related Art In the field of semiconductors, so-called single crystal S
It is well known that various semiconductors are formed by implanting impurities such as phosphorus and boron into a single crystal Si thin film epitaxially grown on an i substrate.

Since a monocrystalline Si thin film can form a semiconductor active element having excellent element characteristics as compared with amorphous Si or polycrystalline Si, various manufacturing methods have been developed.

[0004]

In the semiconductor device using the above-mentioned single crystal Si thin film, the starting substrate is the single crystal S.
Since it is an i substrate, it is easily cracked along a specific orientation due to its crystallinity, and the strength is remarkably reduced when the substrate is thin. Therefore, the thickness of the finally obtained substrate is as thick as about 1 mm.

Further, the semiconductor device obtained by using the above-mentioned single crystal Si thin film has the following problem of strength reduction.

A plurality of semiconductor chips are simultaneously manufactured on one Si wafer, but the divided chips have defects at the dividing interface due to the step of dicing each chip (dicing). As a result, the theoretical strength is increased. The strength is reduced to 1/100 or less.

Since the chip thickness is large, it is easily cracked by bending.

The stress structure on the front and back surfaces of the substrate is different due to the fabrication of the element, and crystal defects are easily generated on the back surface of the substrate and are easily cracked.

A thick semiconductor device has a problem in the current high definition, such as poor heat dissipation, inability to achieve high density, and restricted mounting method.

For example, there is an IC card as an example of using a thin semiconductor device. However, even in this IC card, the thickness is about 1 mm and it is hard at present because of the manufacturing of the semiconductor device. It is desired that the thinness is 0.6 mm or less and that it is flexible in preventing damage.

In view of the above problems, it is an object of the present invention to provide an ultrathin and flexible semiconductor device having sufficient strength.

[0012]

Means and Actions for Solving the Problems The present inventors have
SOI (Silicon on Insulator)
While studying, the ultra-thin SOI structure was
Discovered that it is more flexible and less likely to break than the i-substrate,
The present invention has been achieved.

That is, the present invention is a semiconductor device in which an amorphous insulating layer is laminated above and below a semiconductor integrated circuit in which an active element using a single crystal Si thin film as an active layer is formed, and the layer thickness of the device is 100 μm. The semiconductor device is characterized by the following.

If the layer thickness of the device is thin, it is effective for bending, and the radius of curvature can be made small, as shown in Table 1 below. For example, an object having a thin film structure of SiO ₂ / SiN and a thickness of about 1 μm and a width of about 10 mm has a tensile breaking strength of about 100 g. A semiconductor device having a layer thickness of about 3 to 4 μm as shown in Example 1 to be described later has a strength of 300 to 400 g, and if manufactured carefully, has a strength capable of mass production.

However, in order to use these in the general market, the strength is further improved, empirically, the strength is about 1 kg, and as described later, there is an ionic effect on the semiconductor device. It is necessary to prevent it, and considering these, it is desirable to set the thickness to 100 μm or less including the organic protective layer.

Semiconductor or inorganic material (SiO ₂ , Si
Forming a thickness of about 100 μm only with N, SiON, BPSG, PSG) is very uneconomical when considering the film forming speed of these materials, and at the same time increasing the film thickness causes problems such as internal stress. On the contrary, a crack or the like is generated in the film, which causes a decrease in strength. In general, the inorganic film thickness formed by these film formations is empirically considered to be about 2 μm at the maximum. Therefore, in the embodiment described later, if all are made of inorganic film, the upper layer has a maximum thickness of about 4 μm. As described above, if the economic limit of the thermal oxidation process of Si is about 2 μm for the lower layer, the semiconductor layer and its LOCOS are formed.
It is considered that the maximum thickness including the oxide layer is about 6 μm.

Therefore, a strength of about 600 g can be obtained by the above strength calculation. On the other hand, the bending limit is a radius of curvature of 1 to
It becomes as large as 1.5 mm.

According to the above-mentioned rules of thumb, in order to be able to use the product in any market with peace of mind,
The breaking strength is preferably 1 kg or more, and it is desirable to use an organic protective layer together. Although the thickness of the organic protective layer depends on the film forming method, generally, when considering solvent coating such as spin coating and dip coating, the degree of freedom of coating is considered to be about 50 Å to 25 μm. By repeating thick coating, the degree of freedom in film thickness is expanded.

Therefore, if a film thickness of about 25 μm is added to each of the upper and lower layers, an inorganic film upper and lower layers of 6 μm, a semiconductor layer 2 μm, and an organic protective layer upper and lower layers of 50 μm each, a structure of about 60 μm can be formed. Further, for safety, by overcoating the upper and lower organic protective layers, a strong film semiconductor having a thickness of 100 μm or less can be formed.

An organic protective layer of about 25 μm × 2 = 50 μm is equivalent to the thickness of a flexible circuit which is widely used at present, and can be expected to be sufficiently marketed in consideration of strength and flexibility.

The semiconductor device using the thin film SOI structure according to the present invention has the following strength advantages.

(1) The front and back of the device have a glassy (amorphous) structure, and there are no defects due to crystallinity.

(2) Since the chip is thin, a wet or dry etching method can be selected instead of dicing for dividing the chip, and defects are unlikely to occur at the cutting interface.

(3) Since the single crystal Si layer for forming the element exists in the central portion of the layer, it is located in a portion where stress is small against bending.

Although Si is excellent in the strength (theoretical strength) peculiar to the material, when a semiconductor device is constructed, the strength is only 1/100 or less of the theoretical strength due to defects caused by the material, structure, and manufacturing process. Not shown, SiO ₂ ,
It is weaker than the strength of the film made of SiN, SiON, BPSG and PSG. This relationship is shown in Table 1.

Table 1 shows SiO ₂ , SiN, SiON and BP.
The Young's modulus E, Poisson's ratio ν, maximum breaking stress σ of each of SG and PSG films, the radius of rupture curvature when each film thickness is t, and the experimental strength are shown.

Here, the breaking radius of curvature R is assumed to be such that the maximum principal stress occurs on the film surface when the thin film is bent. The theoretical value was calculated by R = tE / [2 × σ × (1−ν2)].

[0028]

[Table 1]

As shown in Table 1, the relationship between each film thickness and the radius of curvature R has the following characteristics.

For each material, the rupture radius of curvature R becomes smaller both in theoretical and experimental values as the film thickness t becomes smaller.

For each material, the experimental value of the radius of curvature of fracture R is larger than the theoretical value, and the difference is remarkable especially in Si.

Therefore, the semiconductor device of the present invention can be bent with a curvature of about 0.3 to 1.5 mm by utilizing a substantially flexible amorphous film to reduce the film thickness. There are possible application fields that were not possible with semiconductor devices.

[0033]

【Example】

[Embodiment 1] FIG. 1 shows a sectional view of a first embodiment of the present invention. In FIG. 1, 2 is an insulating layer made of SiO ₂ having a film thickness of 8000 Å, 15 is an N-MOSTr region, and 10 is NM.
OSTr channel (film thickness 4000Å), 4 and 5 are N
The source and drain of the MOSTr, 8 is a gate oxide film made of SiO ₂ , and 9 is a gate electrode made of polycrystalline Si. 6 is a P-MOSTr region, 11 is a channel (film thickness 4000Å), and 6 and 7 are sources and drains. Trs 15 and 16 are element-isolated by three LOCOS layers, respectively.
An Al wiring 22 for forming 9 is provided. A
The interlayer insulating layer 20 between the L wiring 22 and the gate wiring has a thickness of 40
The 00 Å BPSG and final passivation layer 30 are 10000 Å thick PSG. Reference numeral 31 is a wiring lead portion, which is formed by partially removing the passivation layer 30. A P-MOSTr 17 is formed as an output buffer.

The semiconductor device thus formed has a film thickness of the insulating layer 2 (8000 Å) + LOCOS layer (1000
0 Å) + interlayer insulation layer 20 (6000 Å) + Al wiring 22
(6000Å) + passivation layer 30 (6000
Å) = 36000Å.

When the electrode was applied to the wiring lead-out portion 31 of the present semiconductor device and the electrical characteristics were examined, good characteristics were confirmed.

In this semiconductor device, the upper insulating layer sandwiching the semiconductor layer (channels 10 and 11) is the interlayer insulating layer 20.
And the passivation layer 30 is 12000 Å, the lower insulating layer is 8000 Å of the insulating layer 2, and the ratio of the upper and lower thickness is 3/2.
Is.

The bending rupture curvature of this embodiment is 0.6 mm, and it has sufficient flexibility for new applications.

FIG. 5 shows the change of the electric characteristics with respect to bending.
It shows in FIG. FIG. 5 shows a conventional semiconductor device (chip thickness 0.6 mm) showing almost the same characteristics as this embodiment, and FIG. 7 shows a semiconductor device (chip thickness 3.6 μm) of this embodiment in a parallel (non-bent) state. This is the V _D / I _D characteristic. When these semiconductor devices were changed to a convex shape by a bulge meter (device for changing the curvature) and the same characteristics were re-established, the V _D / I _D characteristics of the conventional semiconductor device changed greatly as shown in FIG. However, the V _D / I _D characteristics of this example were almost the same as those of FIG. 7 as shown in FIG. In this measurement, the two were compared with a curvature of 500 mm.

As described above, in the present embodiment, since the mechanical strength is sufficient for bending with a curvature of 0.6 mm, it can be bent to a small curvature, and its characteristic change does not exist in the conventional semiconductor device. It was found to have characteristic stability against changes.

The P-T is applied to the SOI wafer according to the present embodiment.
Known semiconductor forming processes can be used for the method of forming r, N-Tr, the element isolation method, the interlayer insulating layer forming method, and the Al wiring forming method.

FIG. 2 shows an example of the manufacturing process of the semiconductor device of this embodiment.

In FIG. 2, (a) is a starting substrate. In the present invention, the starting substrate is a Si substrate 1, an insulating layer (SiO 2
₂ ) 2 and a single crystal Si epitaxial layer 41 are used. The substrate having such a structure can be obtained by the SIMOX method, the substrate bonding method, and the method of epitaxially growing single crystal Si on porous Si previously proposed by the present applicant. In particular, the method proposed by the present applicant is excellent in that the quality of Si, the type of insulating layer, and the thickness thereof can be freely selected.

Tr25, 26, 27, 19 (semiconductor layer 42) is formed on the substrate (a) by a normal semiconductor process.
Also, the passivation layer 30 and the wiring lead-out portion 31 (insulating layer 43) were formed (b).

Next, as shown in (c), the Si substrate 1 is removed to thin the wafer. As disclosed in Japanese Patent Application Laid-Open No. 5-273591, there are various methods such as dry and wet methods for etching Si. In this example, the etching rate was changed between SiO ₂ / Si, and etching was performed using TMAH at a relatively low temperature and a high etching rate.

Specifically, the wafer surface shown in (b) is coated with Apiezon wax 44 and dried.
The etching was completed 14 hours after being placed in the H80 ° C. solution (d). After that, the etching resist 44 was peeled off with an acetone solution or the like to obtain a thin wafer (e).

In the above method, the entire surface of the wafer is etched, but the Si substrate 1 on the back surface may be etched after dividing it into chips.

Si wafer, Si thus obtained
When the electrical characteristics of the chip were measured, good characteristics that were the same as those with the Si substrate 1 were obtained.

[Embodiment 2] FIG. 3 shows a second embodiment of the present invention. This example uses a single crystal Si film formed by the method proposed by the applicant of the present invention.
In the starting substrate (a), the insulating layer is a SiO ₂ layer 51 (thickness 4000 Å) and a SiN layer 52 (thickness 4000 Å) 2.
It has a layered structure. With the two-layer structure as described above, the interface state of the single crystal Si layer can be reduced.

The formation of the semiconductor layer 42 and the insulating layer 43 is the same as that of the first embodiment (b), but in the etching removal process of the Si substrate 1, the SiN layer 52 is exposed to a strong alkaline solution such as KOH. It also acts as an etching stop layer against a strong acid such as HF + HNO ₃ . Therefore, the etching can be completed in a short time using KOH having a high etching rate. However, when KOH is used as an etching solution, an etching stop layer is required on the surface side instead of the apiezon wax. In this embodiment, the same SiN film 53 as that formed on the back surface is formed on the PSG film, which is the passivation layer, with a thickness of 2000 Å so as to form two layers (c).

Further, although the plasma SiN layer is used as the insulating layer in the present embodiment, the same effect can be obtained by using SiON or the like. Furthermore, in the present embodiment, as in the first embodiment, either wafer etching or chip etching may be used.

In this embodiment, the thickness ratio of the upper and lower insulating layers is 14,000Å in the upper layer and 8000Å in the lower layer, which is 7/4. However, the lower SiO ₂ layer is 14000Å to 200 in the substrate state.
If it is up to about 00Å, it can be formed practically without any problem.

[Embodiment 3] FIG. 4 shows a manufacturing process of a third embodiment of the present invention. In this embodiment, a SIMOX substrate is used as a starting substrate (a). In the SIMOX substrate, the SiO _{2 of the} insulating layer ₂ is a single layer film due to restrictions on the manufacturing process. It is also practical that the SiO ₂ layer has a relatively small thickness.

Similar to the first embodiment, a device was formed in the single crystal Si layer 61 by a normal semiconductor process, and then a passivation layer made of PSG was provided (b).

Next, a fluororesin 6 is used as an etching mask.
After coating 2 with 5 μm, the same procedure as in Example 1 was performed.
The Si substrate 1 on the back surface was removed by etching with MAH. The fluororesin may be formed by vacuum vapor deposition, thermal spraying, coating and drying of liquid resin, or the like. In this example, CYTOP manufactured by Asahi Glass Co., Ltd. was coated and dried to form the fluororesin layer 62. When an etching mask made of an organic resin is formed on the passivation layer as described above, pinholes cannot be formed, so that the yield of Si etching on the back surface can be increased. Further, since the fluororesin used in this example has high moisture resistance and mechanical strength,
It can be used as the second passivation film without being removed even after etching. As such a film, silicone resin or rubber can be used in addition to fluororesin.

[0055] Further, as SIMOX wafers used in this example was the, SiO ₂ from restriction of the manufacturing process
Since the thickness of the insulating layer is only 3000 Å, the single crystal S
The operation of the MOS-Tr built in the i layer may become unstable or the threshold voltage may change. This is because the thickness of the insulating layer is thin and contaminants and ions attached to the insulating layer affect the operation of the MOS-Tr. In order to prevent this, in the present embodiment, the fluorine resin 62 ′ is applied and formed on the surface of the insulating layer 2 exposed by removing the Si substrate 1 so that contaminants and ions do not affect the operation of the MOS-Tr. .

The upper and lower sides of the thin film semiconductor device are made of the same material and the difference in thickness between them does not become large.
The film can be curled and the characteristics of the semiconductor element can be stabilized. The fact that the p-n junction of a semiconductor undergoes various characteristic changes due to stress is obvious from the fact that the characteristics are applied to various semiconductor sensors in reverse. Therefore IC
In the case where the characteristics are used logically, or for applications such as amplification and comparison, it is important to make the stress due to bending uniform.

Since the semiconductor device of the present invention is thin and is positively bent and used, by limiting the difference in thickness between the upper and lower insulating layers within a certain range, a pn junction is formed. It is an important point to reduce the generated stress.

Further, as shown in the third embodiment, by further laminating a thin film made of an organic material on the outer side, it is possible to maintain the mechanical strength and protect from the influence of the external environment change. Also in this case, it is important to make the thickness of the organic thin film as uniform as possible.

[0059]

The semiconductor device of the present invention is extremely thin and flexible as compared with the conventional thin semiconductor device. Therefore, thin IC cards, etc.
In addition to realizing a thinner device, it can be applied to a high-definition device or a new field that was previously impossible by taking advantage of high heat dissipation and wiring flexibility.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing electrical characteristics of a conventional semiconductor device.

FIG. 6 is a diagram showing electrical characteristics of the semiconductor device of the first embodiment of the present invention.

FIG. 7 is a diagram showing electrical characteristics of a conventional semiconductor device in a bent state.

FIG. 8 is a diagram showing electrical characteristics of the semiconductor device of Example 1 of the present invention in a bent state.

[Explanation of symbols]

1 Si substrate 2 insulating layer 3 LOCOS layer 4 source of N-MOSTr 5 drain of N-MOSTr 6 source of P-MOSTr 7 drain of P-MOSTr 8 gate oxide film 9 gate electrode 10 channel of N-MOSTr 11 P-MOSTr Channel 15 N-MOSTr 16 P-MOSTr 17 P-MOSTr 19 C-MOS inverter 20 Interlayer insulating layer 22 Al wiring 30 Passivation layer 31 Wiring lead portion 41 Single crystal Si epitaxial layer 42 Semiconductor layer 43 Insulating layer 44 Apiezon wax layer 51 SiO ₂ layer 52 SiN layer 61 Single crystal Si layer 62, 62 ′ Fluororesin layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/786

Claims (2)

[Claims] 1. A semiconductor device in which an amorphous insulating layer is laminated on and under a semiconductor integrated circuit in which an active element using a single crystal Si thin film as an active layer is formed, and the layer thickness of the device is 100 μm or less. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, further comprising an organic thin film stacked above and below the upper and lower insulating layers.