JPH07201837A - Apparatus for manufacturing semiconductor device - Google Patents

Apparatus for manufacturing semiconductor device

Info

Publication number
JPH07201837A
JPH07201837A JP35042393A JP35042393A JPH07201837A JP H07201837 A JPH07201837 A JP H07201837A JP 35042393 A JP35042393 A JP 35042393A JP 35042393 A JP35042393 A JP 35042393A JP H07201837 A JPH07201837 A JP H07201837A
Authority
JP
Japan
Prior art keywords
space
reaction gas
wafer
porous plate
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35042393A
Other languages
Japanese (ja)
Inventor
Shinichi Araki
新一 荒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP35042393A priority Critical patent/JPH07201837A/en
Publication of JPH07201837A publication Critical patent/JPH07201837A/en
Pending legal-status Critical Current

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  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To make it possible to apply a reactive gas uniformly to a surface of a semiconductor wafer, by separating a first space, in which semiconductor wafers are arranged, and a second space, in which a reactive gas is supplied, and diffusing the gas through a porous plate from the second space to the first space. CONSTITUTION:In a semiconductor manufacturing apparatus 20, a flange of quartz glass is formed on an inner circumferential face of an inner tube 3. A porous plate 22 having a plurality of through holes 23 of 1mm or above in diameter is fixed around a quartz cap 6. The flow of a reactive gas through a nozzle 7 into a double reactive tube 8 is blocked by the porous plate 22, and the reactive gas can not diffuse immediately into a wafer-boat arranged space 25A and remains still in a nozzle arranged space 25B. After a while, the reactive gas, which is increasing in the space 25B, diffuses into the wafer- boat 4 arranged space 25A uniformly through the through holes 23 of the porous plate 22. In this way, the reactive gas is applied uniformly to a wafer 5, and thereby the an insulating film is formed uniformly in thickness.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体製造装置に関し、
例えば化学気相堆積(CVD(chemical vapor depositi
on) )装置に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus,
For example, chemical vapor deposition
on)) It is suitable to be applied to a device.

【0002】[0002]

【従来の技術】従来、縦型減圧CVD(化学気相堆積)
型の半導体製造装置としては、図4に示すような構成の
ものがある。すなわち図4において1は全体として半導
体製造装置を示し、アウタチユーブ2及びインナチユー
ブ3によつて構成された2重反応管8内に石英キヤツプ
6を台座としてボート4が設置されている。このボート
4には複数のウエハ5が所定間隔を隔てて積層状態に収
納されている。
2. Description of the Related Art Conventionally, vertical low pressure CVD (chemical vapor deposition)
2. Description of the Related Art A type semiconductor manufacturing apparatus has a structure as shown in FIG. That is, in FIG. 4, reference numeral 1 denotes a semiconductor manufacturing apparatus as a whole, and a boat 4 is installed in a double reaction tube 8 constituted by an outer tube 2 and an inner tube 3 with a quartz cap 6 as a pedestal. A plurality of wafers 5 are accommodated in the boat 4 in a stacked state at a predetermined interval.

【0003】かかる構成の2重反応管(2、3)内部に
は複数のノズル7が設けられており、当該ノズル7を介
してテトラエトキシオゾシラン(以下これをTEOSと
呼ぶ)系反応ガスを2重反応管8内部に導入することに
より、当該反応ガスによつてウエハ表面に絶縁膜を成膜
するようになされている。
A plurality of nozzles 7 are provided inside the double reaction tube (2, 3) having such a structure, and a tetraethoxy ozosilane (hereinafter referred to as TEOS) type reaction gas is supplied through the nozzles 7. By being introduced into the double reaction tube 8, an insulating film is formed on the wafer surface by the reaction gas.

【0004】[0004]

【発明が解決しようとする課題】ところでかかる構成の
半導体製造装置1においては、図5に示すように2重反
応管8の内部に反応ガスGAを導入する際、当該反応ガ
スGAの拡散特性悪く、ボート4に対して不均一に拡散
することになる。この結果図6に示すようにウエハ5の
表面に成膜される絶縁膜5Aの厚みが不均一になる問題
があつた。
By the way, in the semiconductor manufacturing apparatus 1 having such a structure, when the reaction gas GA is introduced into the double reaction tube 8 as shown in FIG. 5, the diffusion characteristic of the reaction gas GA is bad. , Will be unevenly diffused over the boat 4. As a result, there is a problem that the thickness of the insulating film 5A formed on the surface of the wafer 5 becomes uneven as shown in FIG.

【0005】この問題点を解決するための一つの方法と
して、反応ガスを2重反応管8内に導入するためのノズ
ル7を複数配置し、複数の噴射源から反応ガスGAを噴
射することによつて2重反応管8内における反応ガスG
Aの拡散を均一化する方法が考えられている。
As one method for solving this problem, a plurality of nozzles 7 for introducing the reaction gas into the double reaction tube 8 are arranged and the reaction gas GA is injected from a plurality of injection sources. Therefore, the reaction gas G in the double reaction tube 8
A method of making the diffusion of A uniform is considered.

【0006】ところがこのような構成においては、ノズ
ル7を複数配置する分、半導体製造装置1の構成が全体
として複雑化することを避け得ない問題があつた。
However, in such a structure, there is an unavoidable problem that the structure of the semiconductor manufacturing apparatus 1 is complicated as a whole because a plurality of nozzles 7 are arranged.

【0007】本発明は以上の点を考慮してなされたもの
で、簡易な構成によつて反応ガスを均一に拡散させ、半
導体ウエハ表面に均一に付着させることができる半導体
製造装置を提案しようとするものである。
The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a semiconductor manufacturing apparatus capable of uniformly diffusing a reaction gas and adhering it uniformly to the surface of a semiconductor wafer with a simple structure. To do.

【0008】[0008]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、反応ガスGAを用いて半導体ウエ
ハ表面に絶縁酸化膜5Aを成膜する半導体製造装置20
において、半導体ウエハ5を内部に配置し、所定の反応
ガスGAを導入することにより半導体ウエハ5に反応ガ
スGAを付着させる筐体8と、筐体8を半導体ウエハ5
が配置された第1の空間25Aと反応ガスGAを導入す
る第2の空間25Bとに分割すると共に、複数の貫通孔
23が形成された多孔板22とを備え、第2の空間25
Bに導入された反応ガスGAを、多孔板22の複数の貫
通孔23を介して第1の空間25Aに拡散させるように
する。
In order to solve such a problem, in the present invention, a semiconductor manufacturing apparatus 20 for forming an insulating oxide film 5A on the surface of a semiconductor wafer using a reaction gas GA.
In the above, the semiconductor wafer 5 is placed inside, and a housing 8 for adhering the reaction gas GA to the semiconductor wafer 5 by introducing a predetermined reaction gas GA;
Is divided into a first space 25A in which is arranged and a second space 25B into which the reaction gas GA is introduced, and a porous plate 22 in which a plurality of through holes 23 are formed is provided.
The reaction gas GA introduced into B is made to diffuse into the first space 25A through the plurality of through holes 23 of the porous plate 22.

【0009】また本発明においては、反応ガスGAは、
テトラトキシオゾシラン又はシラン系のガス及び所定の
ドーピングガスを混合してなるようにする。
Further, in the present invention, the reaction gas GA is
A mixture of tetratoxiosilane or a silane-based gas and a predetermined doping gas is used.

【0010】また本発明においては、貫通孔23は直径
が1[mm]以上でなり、かつ多孔板表面及び貫通孔23の
連接部に形成されたエツジを曲面加工する。
Further, in the present invention, the through hole 23 has a diameter of 1 mm or more, and the edge formed on the surface of the porous plate and the connecting portion of the through hole 23 is curved.

【0011】また本発明においては、貫通孔23及び多
孔板22は、表面にシリコン皮膜27を形成する。
Further, in the present invention, the through hole 23 and the perforated plate 22 form a silicon film 27 on the surface.

【0012】[0012]

【作用】第2の空間25Bに導入された反応ガスGAを
多孔板22の複数の貫通孔23を介して半導体ウエハが
配置された第1の空間25Aに拡散させることにより、
当該第1の空間25Aにおける反応ガスGAの拡散を均
一化することができる。
By diffusing the reaction gas GA introduced into the second space 25B into the first space 25A in which the semiconductor wafer is arranged through the plurality of through holes 23 of the porous plate 22,
The diffusion of the reaction gas GA in the first space 25A can be made uniform.

【0013】[0013]

【実施例】以下図面について、本発明の一実施例を詳述
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

【0014】図4との対応部分に同一符号を付して示す
図1において半導体製造装置20はインナチユーブ3の
内周面に石英ガラスでなるフランジ21が形成されてい
る。また石英キヤツプ6の外周面には直径が1[mm]以上
の貫通孔23が複数配列形成されてなる石英ガラスの多
孔板22がフランジ21の下側面に対して3〜5[mm]程
度の間隙を隔てて固定されている。従つて2重反応管8
内部は、多孔板22によつてボード4が配置されたボー
ト配置空間25Aと、ノズル7が配置されたノズル配置
空間25Bに分離される。
In FIG. 1 in which parts corresponding to those in FIG. 4 are designated by the same reference numerals, a flange 21 made of quartz glass is formed on the inner peripheral surface of the inner tube 3 in the semiconductor manufacturing apparatus 20. On the outer peripheral surface of the quartz cap 6, a perforated plate 22 of quartz glass, in which a plurality of through holes 23 having a diameter of 1 [mm] or more are arrayed, is formed on the lower surface of the flange 21 by about 3 to 5 [mm]. It is fixed across a gap. Therefore, double reaction tube 8
The inside is divided by the porous plate 22 into a boat arrangement space 25A in which the board 4 is arranged and a nozzle arrangement space 25B in which the nozzles 7 are arranged.

【0015】多孔板22は図2に示すように石英キヤツ
プ6の外周面に沿つて複数の貫通孔23を形成し、当該
貫通孔23を介してノズル7から2重反応管8内部に導
入された反応ガスをノズル配置空間25B及びボート配
置空間25A間に導入し得るようになされている。ここ
で反応ガスとしてはTEOS又はシラン(SiH4) 系のガ
スに対してB(C25)3 、PO(CH3)3、PH3 又はB2H6等のド
ーピングガスを混合したものを用いる。
As shown in FIG. 2, the perforated plate 22 has a plurality of through holes 23 formed along the outer peripheral surface of the quartz cap 6, and is introduced from the nozzle 7 into the double reaction tube 8 through the through holes 23. The reaction gas can be introduced between the nozzle arrangement space 25B and the boat arrangement space 25A. Here, the reaction gas is a mixture of TEOS or silane (SiH 4 ) based gas with a doping gas such as B (C 2 H 5 ) 3 , PO (CH 3 ) 3 , PH 3 or B 2 H 6. To use.

【0016】ここで多孔板22においては図3(A)に
示すように貫通孔23及び多孔板22の表面全体に反応
ガスによる絶縁膜が成膜することにより、貫通孔23が
長期使用によつて目詰まりすることがある。従つて図3
(B)に示すように貫通孔23をアニール加工してエツ
ジ部に曲面(ラウンド)を形成すると共に、当該貫通孔
23を含む多孔板22の表面全体に10〜20〔μm〕程度
のシリコン(Poly-Si)を被着させてシリコン膜27を生
成することにより、絶縁膜を成膜させ難く、また定期的
な石英部品のエツチングにおいても絶縁膜及びシリコン
膜との選択比が大きいことによつて下地は保護され加工
時の形状を維持することができる。
Here, in the porous plate 22, as shown in FIG. 3 (A), by forming an insulating film by a reaction gas on the entire surface of the through hole 23 and the porous plate 22, the through hole 23 can be used for a long time. This may cause clogging. Therefore, Figure 3
As shown in (B), the through hole 23 is annealed to form a curved surface (round) in the edge portion, and silicon of about 10 to 20 [μm] is formed on the entire surface of the porous plate 22 including the through hole 23. By forming a silicon film 27 by depositing (Poly-Si), it is difficult to form an insulating film, and the selection ratio between the insulating film and the silicon film is large even in the regular etching of quartz parts. Therefore, the base is protected and the shape during processing can be maintained.

【0017】以上の構成において、ノズル7から2重反
応管8内部に導入された反応ガスは多孔板22が設けら
れていることによつて直ちにボート配置空間25Aに拡
散せずにノズル配置空間25Bに留まる。このとき多孔
板22に形成された貫通孔23から僅かに反応ガスがボ
ート配置空間25Aに流出するが、この流出量はノズル
配置空間25Bに溜まる反応ガスの量に比べて微量であ
る。
In the above structure, the reaction gas introduced from the nozzle 7 into the double reaction tube 8 is not immediately diffused into the boat arrangement space 25A because the porous plate 22 is provided, and the nozzle arrangement space 25B is not immediately diffused. Stay in. At this time, the reaction gas slightly flows out from the through hole 23 formed in the porous plate 22 into the boat arrangement space 25A, but the outflow amount is a minute amount compared with the amount of the reaction gas accumulated in the nozzle arrangement space 25B.

【0018】やがて当該ノズル配置空間25Bに反応ガ
スが溜まると、当該ノズル配置空間25Bを反応ガスの
拡散源として多孔板22に形成された貫通孔23からボ
ート配置空間25A内に反応ガスが拡散する。
When the reaction gas accumulates in the nozzle arrangement space 25B, the reaction gas diffuses into the boat arrangement space 25A from the through hole 23 formed in the porous plate 22 using the nozzle arrangement space 25B as a diffusion source of the reaction gas. .

【0019】この結果ボート4の下方において当該ボー
ド4の周囲を取り巻く貫通孔23から反応ガスがボート
配置空間25A内に均一に拡散することにより、ボート
4に収納されたウエハ5に対して反応ガスが均一に付着
する。かくしてウエハ5の表面において反応ガスによつ
て成膜される絶縁膜の厚みが均一化する。
As a result, the reaction gas uniformly diffuses into the boat arrangement space 25A from the through holes 23 surrounding the board 4 below the boat 4, so that the reaction gas with respect to the wafers 5 accommodated in the boat 4 can be obtained. Adheres evenly. Thus, the thickness of the insulating film formed by the reaction gas on the surface of the wafer 5 becomes uniform.

【0020】以上の構成によれば、多孔板22を配置す
ることによつて2重反応管8内部をボート配置空間25
A及びノズル配置空間25Bに分割し、多孔板22に配
列形成された複数の貫通孔23を介してノズル配置空間
25Bに溜まつた反応ガスをボート配置空間25A内に
拡散させるようにしたことにより、当該ボード配置空間
25A内への反応ガスの拡散を均一化することができ、
これによりボート4に収納されたウエハ5に成膜される
絶縁膜5Aの厚みを均一化することができる。
According to the above construction, by disposing the perforated plate 22, the inside of the double reaction tube 8 is provided with the boat arrangement space 25.
A and the nozzle arrangement space 25B are divided, and the reaction gas accumulated in the nozzle arrangement space 25B is diffused into the boat arrangement space 25A through the plurality of through holes 23 arranged in the porous plate 22. The diffusion of the reaction gas into the board disposing space 25A can be made uniform,
As a result, the thickness of the insulating film 5A formed on the wafer 5 housed in the boat 4 can be made uniform.

【0021】なお上述の実施例においては、縦型の半導
体製造装置20に本発明を適用した場合について述べた
が、本発明はこれに限らず、ボード4を水平方向に配置
した横型の半導体製造装置においても本発明を適用する
ことができる。
In the above embodiment, the case where the present invention is applied to the vertical type semiconductor manufacturing apparatus 20 has been described, but the present invention is not limited to this, and a horizontal type semiconductor manufacturing in which the board 4 is arranged in the horizontal direction is used. The present invention can be applied to an apparatus.

【0022】[0022]

【発明の効果】上述のように本発明によれば、半導体ウ
エハの表面にテトラトキシオゾシラン又はシラン系の成
膜を行う2重反応管内部において、半導体ウエハを保持
するボートを配置したボート配置空間と反応ガスを導入
するノズル配置空間とを複数の貫通孔を形成した多孔板
によつて分割し、ノズルから2重反応管内部に導入され
た反応ガスを一旦ノズル配置空間内に溜め、当該ノズル
配置空間内に溜まつた反応ガスを多孔板の貫通孔を介し
てボート配置空間内に均一に拡散させるようにしたこと
により、半導体ウエハ表面に反応ガスを均一に付着させ
ることができる。かくして半導体ウエハ表面に成膜され
る成膜層の厚みを均一化することができる。
As described above, according to the present invention, a boat arrangement in which a boat for holding a semiconductor wafer is arranged inside a double reaction tube for forming a film of tetratoxiozosilane or silane on the surface of the semiconductor wafer. The space and the nozzle arrangement space for introducing the reaction gas are divided by a perforated plate having a plurality of through holes, and the reaction gas introduced from the nozzle into the double reaction tube is temporarily stored in the nozzle arrangement space. Since the reaction gas accumulated in the nozzle arrangement space is uniformly diffused into the boat arrangement space through the through holes of the perforated plate, the reaction gas can be uniformly attached to the surface of the semiconductor wafer. Thus, the thickness of the film-forming layer formed on the surface of the semiconductor wafer can be made uniform.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体製造装置の一実施例を示す
断面図である。
FIG. 1 is a sectional view showing an embodiment of a semiconductor manufacturing apparatus according to the present invention.

【図2】本発明による多孔板の構成を示す斜視図であ
る。
FIG. 2 is a perspective view showing a configuration of a perforated plate according to the present invention.

【図3】貫通孔の構成を示す断面図である。FIG. 3 is a cross-sectional view showing the structure of a through hole.

【図4】従来の半導体製造装置を示す断面図である。FIG. 4 is a sectional view showing a conventional semiconductor manufacturing apparatus.

【図5】反応ガスの不均一拡散状態を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a non-uniform diffusion state of a reaction gas.

【図6】ウエハ表面に成膜された絶縁層の不均一状態を
示す断面図である。
FIG. 6 is a cross-sectional view showing a non-uniform state of an insulating layer formed on the surface of a wafer.

【符号の説明】[Explanation of symbols]

1、20……半導体製造装置、2……アウタチユーブ、
3……インナチユーブ、4……ボート、5……ウエハ、
5A……成膜層(絶縁層)、6……石英キヤツプ、7…
…ノズル、8……2重反応管、21……フランジ、22
……多孔板、23……貫通孔、27……シリコン膜。
1, 20 ... Semiconductor manufacturing equipment, 2 ... Outer tube,
3 ... Inner tube, 4 ... boat, 5 ... wafer,
5A ... film forming layer (insulating layer), 6 ... quartz cap, 7 ...
… Nozzle, 8 …… Double reaction tube, 21 …… Flange, 22
…… Perforated plate, 23 …… Through hole, 27 …… Silicon film.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】反応ガスを用いて半導体ウエハ表面に絶縁
酸化膜を成膜する半導体製造装置において、 上記半導体ウエハを内部に配置し、所定の反応ガスを導
入することにより上記半導体ウエハに上記反応ガスを付
着させる筐体と、 上記筐体を上記半導体ウエハが配置された第1の空間と
上記反応ガスを導入する第2の空間とに分割すると共
に、複数の貫通孔が形成された多孔板とを具え、上記第
2の空間に導入された上記反応ガスを、上記多孔板の複
数の貫通孔を介して上記第1の空間に拡散させるように
したことを特徴とする半導体製造装置。
1. A semiconductor manufacturing apparatus for forming an insulating oxide film on a surface of a semiconductor wafer by using a reaction gas, wherein the semiconductor wafer is placed inside, and a predetermined reaction gas is introduced into the semiconductor wafer to cause the reaction. A housing for adhering gas, a housing for dividing the housing into a first space in which the semiconductor wafer is arranged, and a second space for introducing the reaction gas, and a perforated plate having a plurality of through holes formed therein. The semiconductor manufacturing apparatus according to claim 1, wherein the reaction gas introduced into the second space is diffused into the first space through a plurality of through holes of the porous plate.
【請求項2】上記反応ガスは、 テトラトキシオゾシラン又はシラン系のガス及び所定の
ドーピングガスを混合してなることを特徴とする請求項
1に記載の半導体製造装置。
2. The semiconductor manufacturing apparatus according to claim 1, wherein the reaction gas is a mixture of tetratoxiozosilane or a silane-based gas and a predetermined doping gas.
【請求項3】上記貫通孔は直径が1[mm]以上でなり、か
つ多孔板表面及び貫通孔の連接部に形成されたエツジを
曲面加工してなることを特徴とする請求項1に記載の半
導体製造装置。
3. The through hole having a diameter of 1 [mm] or more, and the edge formed on the surface of the perforated plate and the connecting portion of the through hole is curved to form a curved surface. Semiconductor manufacturing equipment.
【請求項4】上記貫通孔及び上記多孔板は、表面にシリ
コン皮膜を形成してなることを特徴とする請求項1に記
載の半導体製造装置。
4. The semiconductor manufacturing apparatus according to claim 1, wherein the through-hole and the perforated plate have a silicon coating formed on the surface thereof.
JP35042393A 1993-12-31 1993-12-31 Apparatus for manufacturing semiconductor device Pending JPH07201837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35042393A JPH07201837A (en) 1993-12-31 1993-12-31 Apparatus for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35042393A JPH07201837A (en) 1993-12-31 1993-12-31 Apparatus for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH07201837A true JPH07201837A (en) 1995-08-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP35042393A Pending JPH07201837A (en) 1993-12-31 1993-12-31 Apparatus for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH07201837A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100340910B1 (en) * 1999-11-12 2002-06-20 박종섭 A furnace for low pressure chemical vapor deposition
JP2009081457A (en) * 2008-11-25 2009-04-16 Hitachi Kokusai Electric Inc Substrate treating apparatus and manufacturing method of semiconductor device
JP2014534644A (en) * 2011-11-17 2014-12-18 ユ−ジーン テクノロジー カンパニー.リミテッド Substrate processing apparatus including auxiliary gas supply port

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100340910B1 (en) * 1999-11-12 2002-06-20 박종섭 A furnace for low pressure chemical vapor deposition
JP2009081457A (en) * 2008-11-25 2009-04-16 Hitachi Kokusai Electric Inc Substrate treating apparatus and manufacturing method of semiconductor device
JP2014534644A (en) * 2011-11-17 2014-12-18 ユ−ジーン テクノロジー カンパニー.リミテッド Substrate processing apparatus including auxiliary gas supply port

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