JPH0720136B2 - Packet communication method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a packet used for data transmission via a common transmission line.

[Technical Background of the Invention and Problems Thereof] When data is transmitted from a certain terminal device to a terminal device at a geographically distant place via a common transmission line and a node provided on this transmission line, The data from the device is once stored in the node and then placed on the common transmission line. For that purpose, each node is provided with a buffer memory for accumulating data from the terminal and the transmission path. Between this buffer memory and the terminal, there is an interface to which multiple terminals can be connected and handles all data from the terminal. When one node handles a large amount of data by a large number of terminals, a large capacity buffer memory for accumulating the data becomes necessary. On the contrary, even if a small number of terminals are connected, a large capacity buffer memory is required even when one terminal handles a large amount of data such as image and audio data. In addition, data communication between a plurality of nodes connected to a conventional common transmission line is the sixth
As shown in the figure, the packet 51 is composed of a header 52, a tail 54, and a data portion 53 filled with meaningful data between them. In other words, the information to be sent from the own node to another node is put on the data section 53 to perform packet exchange between the nodes.

In such a packet configuration, if the data transfer rate between the node performing data communication and its terminal is slower than the data transfer rate of the transmission path, the amount of data that can be transferred at one time is determined by the buffer memory. Depends on the size of. Therefore, in order to transfer a large amount of continuous data such as image data of several megabytes, it is necessary to divide the buffer memory size and transfer it many times. The additional information is added, and the software overhead increases, so that the transmission efficiency decreases. If it is avoided, a large capacity buffer memory corresponding to the size of data to be transferred is required.

[Object of the Invention] The present invention has been made based on such a situation, and even when each node connected to a common transmission line continuously performs a large amount of data communication, a memory of a buffer in the node is provided. An object of the present invention is to provide a packet communication method capable of reducing the capacity.

SUMMARY OF THE INVENTION In order to achieve this object, the present invention provides a plurality of nodes to which terminals can be connected and a common transmission line connected to the plurality of nodes, and the node via the common transmission line. In a packet communication system that performs data transmission between the nodes, an idle packet of an amount based on the ratio of the transmission rate of the common transmission line and the transfer rate from the terminal is inserted between data from the terminals, and between the nodes. A packet communication method characterized by performing data transmission.

[Embodiment of the Invention] Hereinafter, the first embodiment of the present invention will be described with reference to FIG. 4, FIG. 1, and FIG.
An example will be described.

In the network block diagram of FIG. 4, there is a common transmission line 30 for transmitting data and control commands. The transmission path 30 is provided with a plurality of taps 39 and 70. The node 31 is connected to each tap 39 and also connected to the terminals 37 and 38. In the node 31, an input / output interface circuit 32 connected to the tap 39, an input / output buffer circuit 33 connected to this input / output interface circuit, and idle packet insertion circuits 40 and 2 connected to this buffer circuit 33.
These terminal interface circuits 34, 35 and these circuits 32,
Control circuit 36 that appropriately controls the signal flow of 33, 34, 35, 40
There is. The terminals 37 and 38 are connected to the terminal interface circuits 34 and 35, respectively.

In the operation in such a configuration, for example, when transmitting data from the terminal 37 to the terminal 67 connected to the node 61, first, the data generated from the terminal 37 is transferred to the input / output buffer circuit 33 via the terminal interface circuit 34. Accumulated. Next, by the control circuit 36 and the idle packet insertion circuit 40,
The stored data is divided into packets as described later, idle packets are inserted, and headers and tails are added. The data thus modified is sent to the tap 39 via the input / output interface circuit 32. The tap 39 is a data inlet / outlet for inputting / outputting data or commands to / from the common transmission path 30.
The data sent from the node 31 to the tap 39 is the transmission line 30.
Through the tap 70 to the node 61 connected to the target terminal 67. The configuration of the node 61 is the same as the configuration of the node 31. The data sent from the tap 70 to the node 61 is once stored in the input / output buffer circuit via the input / output interface circuit (not shown) in the node 61. Therefore, the input / output buffer circuit 33 removes the modifier added to the data and outputs the data to be sent to the terminal 67. Although data transmission between the terminals 37 and 67 is performed in this manner, such transmission can be performed between all the nodes connected to the common transmission line 30. Therefore, if the terminal is connected to the node, data communication can be performed between terminal devices located at a remote place via the transmission path.

Next, regarding packet division and idle packet insertion
It will be described with reference to the drawings. Packet division and idle packet insertion are performed by the idle packet insertion circuit 40 on the data stored in the input / output buffer circuit 33. The packet 1 has a header 2 at the beginning, a data part 3, an idle packet part 4, a data part 5, and a tail 6 at the end. Here, the header 2 is a node address of the receiving side of the packet 1 and a node address of the transmitting side, a mode of transfer speed,
Contains packet length information. The data sections 3 and 5 are meaningful data from the terminal 37. The idle packet section 4 is sandwiched between the data section 3 and the data section 5 and filled with meaningless data. The meaningless data referred to here are, for example, “1,1,1 ... 1” or “0,0,0 ...
It is data such as "0" or "1,0,1,0 ...", which may be arranged in any way, and when this data is received by the receiving node, it will be erased without being used. The transmission speed of this idle packet part 4 is
It is the same speed as 3,5. Further, the ratio between the amount of the idle packet portion 4 and the amount of the data portions 3 and 5 is determined by the transmission rate of the common transmission line and the transfer rate when the data is sent from the terminal to the node. The transmission speed of the common transmission line is shown in FIG.
Indicates the ratio of the data amount and idle packet amount for 100 (Mbps). The equation for obtaining this ratio can be obtained, for example, by the following equation.

Idle packet amount / data amount = common transmission rate−terminal data transfer rate / terminal data transfer rate For example, the data transfer rate from the terminal 37 to the node 31 is 60.
When (Mbps), idle packets are inserted so that the ratio of the amount of data to the amount of idle packets is 3: 2.

When the data parts 3 and 5 are continuously sent from the terminal to the node 31, the node 31 sends this data part 3 to the common transmission line 30 at 100 (Mbps) when all the data parts 3 are sent. Then, the idle packet 4 is output until all the data parts 5 are sent to the node 31, and then the data part 5 is continuously output. While the idle packet 4 is being transferred from the node 31 to the common transmission path 30, the data 5 to be transferred next is stored in the input / output buffer memory 33 circuit from the terminal 37. When the input / output buffer memory circuit 33 is divided into two and they are alternately switched for data transfer, the input / output buffer memory circuit 33 may be switched during the idle packet 4 transfer. In this way, the node 31 performs asynchronous transfer while absorbing the difference between the transmission speed of the common transmission path 30 and the data input / output speed of the terminal 37. With such idle packet 4 inserting means, the memory capacity of the input / output buffer memory circuit 33 can be greatly reduced. For example, when transmitting a 1-megabyte image, even if one of the communicating nodes only has a buffer memory of 100 kilobytes, it is not necessary to divide the amount of data by the size of the buffer memory and transmit multiple times, so software overhead ( Dead time) is also reduced. Further, since the buffer memory is small, there is no need to return an acknowledgment (acknowledge) that occurs, and therefore the transmission time can be greatly shortened. In FIG. 1, m idle packet units 4 are inserted with respect to n data units 3 and 5, but the smaller the data and idle packets are, the smaller the buffer memory size is. For example, after the header H, D1 to D6, I1 to I4, D7 to D1
It may be done as 2, I5 to I8, ..., T.

The discrimination between the data part and the idle packet part is as follows.
It is put in the header 2 in the transmission side node 31 as a mode of transfer rate. Then, the receiving side node 61 reads this mode and distinguishes the data and the idle packet and takes them in.

Next, a second embodiment of the present invention will be described with reference to FIG.

The packet of FIG. 2 has a meaningful data portion 15 and a header and tail 16 at both ends. And idle packet 1
3,17 are between packets. That is, the space between the tail 12 at the end of the packet and the head of the next packet is filled with idle packets. By performing such packet transmission, even when optical communication using a laser is performed, the setup time of pre-bias (synchronization establishment, etc.) required for each transmission is eliminated, so that transmission efficiency can be improved.

Further, a third embodiment of the present invention will be described with reference to FIG.

The information transfer system shown in FIG. 5 is an advantageous system for transmitting a large amount of data at high speed, such as image transfer. This information transfer system is roughly divided into a header section 100, a frame section 150, and a dummy section 151. A marker 104 for notifying that the frame portion 150 is the frame portion 150 is attached to the head of the frame portion 150. The number in parentheses of MK (0) of this marker 104 is previously determined by the following table, for example.

Marker Meaning MK (0) Start of frame MK (1) Data packet MK (2) Idle packet MK (3) Start of block MK (4) End of frame According to the above table, in case of MK (0), It can be seen that it is the beginning of the frame. A frame consists of several blocks and MK (3) markers at the beginning of each block. At the end of the frame, a marker MK (4) for notifying the end is attached.

The dummy unit 151 corresponds to the time required to read the data of the frame 2 from the memory, during which the marker MK (2) for inserting the idle packet 126 and notifying that it is the idle packet 126 is the idle packet. It is attached at the beginning.

The header section 100 includes a pre-bias 101, an automatic gain control 102, and a word synchronization establishment 103.

The pre-bias 101 is for establishing pulse synchronization in optical communication,
The auto gain control 102 is used to eliminate the intensity of light due to the length of the fiber and the characteristics of the photoelectric conversion semiconductor. Subsequent word synchronization establishment 103 is used to parallelize serial bit signals back into words.

One block consists of some data packets and some idle packets. The amount of data packets is equal to the buffer memory size. In addition, the number of idle packets is inserted so that the average data transfer rate within the block does not exceed the transfer rate within each node. There is a marker MK (1) before the data packet and a marker MK (2) before the idle packet. Immediately after the data packet, there are dead error detection symbols 107, 110, 113, and it is determined whether or not the data is correct.

By attaching such a marker to each packet, block, or frame, it becomes easy to identify a data packet from an idle packet, block, or frame. The ratio of the data packet to the idle packet may be notified to a target node in advance by providing a control packet or a net dedicated to control before the data packet is sent.

The present invention is not limited to the embodiments described above and shown in the drawings, and various modifications can be made without departing from the scope of the invention.

For example, by combining the first embodiment and the second embodiment, it is possible to perform data communication with higher transmission efficiency.

[Effects of the Invention] As described above, according to the present invention, the capacity of the buffer memory in the node can be reduced and the data transmission can be performed even when the nodes connected to the common transmission line continuously perform a large amount of data communication. Highly efficient communication can be performed.

[Brief description of drawings]

FIG. 1 is a packet configuration diagram according to a first embodiment of the present invention, FIG. 2 is a packet configuration diagram according to a second embodiment of the present invention, and FIG. 3 is a data amount and idle packet amount according to the present invention. FIG. 4 is an explanatory diagram showing an example of the ratio, FIG. 4 is a configuration diagram of a network according to the present invention, FIG. 5 is a packet configuration diagram according to a third embodiment of the present invention, and FIG. 6 is a conventional packet configuration. It is a figure. 1 …… Packet, 2 …… Header 3,5,15 …… Data 4,13,17 …… Idle packet 6 …… Tail, 30 …… Common transmission line 33 …… Input / output buffer circuit 40 …… Idle packet insertion Circuit 37,38 …… Terminal, 36 …… Control circuit 31 …… Node

Claims (1)

[Claims] 1. A plurality of nodes, each of which is connectable to a terminal and has a buffer memory for temporarily storing data transferred from the terminal, and a common transmission line connected to the plurality of nodes, are provided. In a packet communication method in which a data transfer rate with the node is configured to be slower than a data transfer rate of the common transmission line, and data transmission between the nodes is performed via the common transmission line, the terminal and the node A packet communication system comprising idle packet inserting means for inserting an idle packet in an amount based on a ratio between a transfer rate between the terminals and a transmission rate of the common transmission path between data from the terminal.