JP3467863B2 - Control data transmission / reception circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control data transmitting / receiving circuit, and more particularly to a control data transmitting / receiving circuit provided in a subscriber circuit of an ATM exchange.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing an example of a conventional ATM switch. ATM switch (1) shown in FIG.
Comprises a subscriber circuit (BSLIC) (2), an ATM switch (ATM) (3), a signal controller (BSGC) (4) and a switch processor (BCPR) (5).

A subscriber circuit (BSLIC) (2) is a broadband terminal (BTE) that transmits and receives cellized data.
It is provided for accommodating (6) in the ATM exchange (1). The ATM switch (ATM) (3) exchanges cells which the broadband terminal (BTE) (6) transmits and receives via the subscriber circuit (BSLIC) (2).

In the signal controller (BSGC) (4), the broadband terminal (BTE) (6) is a switch processor (BCP).
R) (5) The various cellized control information to be transmitted is received via the subscriber circuit (BSLIC) (2) and the ATM switch (ATM) (3), restored to the non-cell format, and the exchange. The ATM switch (ATM) converts various non-cell type control information transmitted to the processor (BCPR) (5) and also transmitted to the broadband terminal (BTE) (6) by the exchange processor (BCPR) (5) to a cell format. ) (3)
And to the broadband terminal (BTE) (6) via the subscriber circuit (BSLIC) (2).

The Switch Processor (BCPR) (5) is
It generally controls the call setting process in the ATM exchange (1). In such an ATM switch (1), a subscriber circuit (BSLIC) (2) and a switch processor (BCPR)
Switch processor (BCPR) between (5)
(5) Various control information for controlling the subscriber circuit (BSLIC) (2), and monitoring information for the subscriber circuit (BSLIC) (2) to notify the switch processor (BCPR) (5) of the internal state. Are transferred via the dedicated communication path (10).

The above-mentioned control information and monitoring information are collectively referred to as control data (DCC) [DCC is a mere code, not an abbreviation of English words. Control data (DC
C) has a variable length of a predetermined data length (for example, 4096 bytes) or less.

[0007]

As is apparent from the above description, in the conventional ATM switch, each subscriber circuit (BSLIC) (2) and switch processor (BCP) are used.
Since a dedicated communication path (10) for transferring control data (DCC) is provided between R) and (5), the exchange processor (BCPR) (5) and each subscriber circuit (B)
It is necessary to provide a dedicated interface for connecting the communication path (10) to the SLIC (2), which causes a problem of impairing the economical efficiency of the ATM exchange (1).

It is an object of the present invention to allow control data to be transferred between a subscriber circuit and a switch processor without compromising the economics of an ATM switch.

[0009]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, 100 is a data transmission / reception means, 200 is a storage means, 300 is an address conversion means, 4
Reference numeral 00 is a communication order data inserting means, and 500 is a cell assembling / disassembling means, which constitutes a control data transmitting / receiving circuit which is a subject of the present invention.

[0010]

The data transmitting / receiving means (100) inputs control data having a predetermined length or less together with a series of continuous address groups and stores it in the storage means (200), and also inputs the continuous address group into the storage means (200). To extract the control data being accumulated.

A storage means (200) stores control data. The address conversion means (300) converts the control data into a partial data having a predetermined data length, the continuous address group output by the data transmission / reception means (100) for storing or extracting the control data in the storage means (200). Divide
A blank area into which communication order data indicating the order of each partial data in the control data can be inserted is provided at the beginning of each partial data, and the blanking area is converted into a group address group for storing in the storing means (200). 200).

The communication order data inserting means (400) indicates the order in the control data of each partial data at the head of each partial data (dcc) accumulated in the accumulating means (200) from the data transmitting / receiving means (100). Add communication order data.

The cell assembling / disassembling means (500) extracts each partial data with communication order data accumulated in the accumulating means (200) from the data transmitting / receiving means (100), assembles the partial data into cells of a predetermined length, and transfers cells. To the storage unit (200) for decomposing the cell-type control data that has been transmitted to the cell transfer path and arriving from the cell transfer path to extract the partial data with the communication sequence data.
Accumulate in.

It is considered that the address conversion means (300) can change the length of the blank area into which the communication sequence data can be inserted according to an instruction from the data transmission / reception means (100).

The storage means (200) is stored by the data transmitting / receiving means (100), and the cell assembling / disassembling means (500).
It is considered that dedicated data storage means are provided for the data extracted by the cell assembling / disassembling means (500) and the data extracted by the data transmitting / receiving means (100).

The storage means (200) is stored by the data transmitting / receiving means (100), and the cell assembling / disassembling means (500).
It is considered that a common storage means is provided for the data extracted by the cell assembling / disassembling means (500) and the data extracted by the data transmitting / receiving means (100).

Further, the storage means (200) is stored by the data transmitting / receiving means (100), and the cell assembling / disassembling means (500).
It is considered to provide a dedicated storage means and a common storage means for the data extracted by the cell assembling / disassembling means (500) and the data stored by the cell assembling / disassembling means (500) respectively.

Therefore, by providing the control data transmitting / receiving circuit according to the present invention to each subscriber circuit in the ATM exchange, it becomes possible to make the control data which each subscriber circuit exchanges with the exchange processor into cells. The broadband terminal accommodated in the ATM switch can be transferred via the same cell transfer path as the cell-type control information exchanged with the switch processor, and control is performed between each subscriber circuit and the switch processor. Since it is not necessary to provide a dedicated communication path for data transfer, the economical efficiency of the ATM switch is greatly improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing an ATM switch according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of an ATM cell format in FIG. 2, and FIG. 4 is a diagram showing an embodiment of the present invention (claim 1). 6 is a diagram showing a control data transmitting / receiving circuit, FIG. 5 is a diagram showing a control data transmitting / receiving circuit according to an embodiment of the present invention (claim 2), and FIG. 6 is a diagram showing an embodiment of the present invention (claim 4). 7 is a diagram showing a control data transmitting / receiving circuit, FIG. 7 is a diagram showing an example of a transmitting / receiving data memory in FIG. 6,
8 is a diagram showing an example of the line address table in FIG. 6, FIG. 9 is a diagram showing an example of the network address table in FIG. 6, and FIG. 10 is an embodiment of the present invention (claim 5). FIG. 3 is a diagram showing a control data transmitting / receiving circuit according to FIG. 1, and FIG. A is a diagram showing a principle of switching memory banks. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, each subscriber circuit (BSLIC) (2) of the ATM exchange (1) is provided with a control data transmitting / receiving circuit (ADP) (7). The subscriber circuit (BSLIC) (2) is a switch processor (BCP).
R) and (5) transmit and receive control data (DCC) as shown in FIG. 3, but unlike the conventional ATM switch (1) [see FIG. 11], control data (DCC)
A dedicated communication path (10) for transfer is not provided, and the control data transmission / reception circuit (ADP) (7) converts it into an ATM cell format as shown in FIG.
TM) (3) and signal controller (BSGC) (4).

Control data transmitting / receiving circuit (ADP) (7)
Is a fixed length [43 bytes length in FIG. 3] control data (DCC) having a variable length of 4096 bytes or less.
Section data (hereinafter referred to as partial control data (dcc)), and communication order data (CSD) [for example, 1-byte length] indicating the order in the control data (DCC) is added to the payload part (P) [ For example, a 44-byte length] is formed, and a predetermined header section (H) [8-byte length] and trailer section (T) [2-byte length] are added and assembled into an ATM cell (C) [for example, 54-byte length]. , ATM switch (ATM) (3), signal control device (BSG
C) Transfer to (4).

As is well known, the signal controller (BSGC) (4) transfers the payload from the ATM cell (C) transferred from the subscriber circuit (BSLIC) (2) through the ATM switch (ATM) (3). The part (P) is extracted, the partial control data (dcc) is assembled into the control data (DCC) based on the communication sequence data (CSD), and then transmitted to the exchange processor (BCPR) (5).

On the other hand, exchange processor (BCPR) (5)
Sends the control data (DCC) to be transferred to the subscriber circuit (BSLIC) (2) to the signal controller (BSGC) (4).
Communicate to.

The signal controller (BSGC) (4) transfers the control data (DCC) transmitted from the exchange processor (BCPR) (5) to the control data transceiver circuit (ADP).
As in (7), it is divided into partial control data (dcc), and communication sequence data (CSD), header section (H) and trailer section (T) are added to assemble an ATM cell (C) (in). , ATM switch (ATM) (3) to the subscriber circuit (BSLIC) (2).

In the subscriber circuit (BSLIC) (2), the control data transmitting / receiving circuit (ADP) (7) transfers the signal from the ATM cell (C) transferred from the signal controller (BSGC) (4) to the signal controller. As in (BSGC) (4), the payload part (P) is extracted and the partial control data (dcc) is assembled into control data (DCC) based on the communication sequence data (CSD).

Thereafter, the control data (DCC) to be transferred from the subscriber circuit (BSLIC) (2) to the exchange processor (BCPR) (5) is transmitted control data (DCC _S ), and the exchange processor (BCPR) (5) is used by the subscriber. Circuit (BSL
The control data (DCC) transferred to the IC) (2) may be distinguished from the reception control data (DCC _R ).

First, an embodiment of the present invention (claim 1) will be described with reference to FIGS. 3 and 4. The control data transmitting / receiving circuit (ADP) (7) shown in FIG. 4 includes a line interface (LIF) (71), a network interface (NIF) (72), and a transmission data memory (SDM).
(73), receive data memory (RDM) (74), data control processor (DPU) (75) and address translation memory (ACM) (76).

Line interface (LIF) (71)
Plays the role of the data transmitting / receiving means (100) in FIG. Network interface (NIF) (7
2) plays the role of the cell assembling / disassembling means (500) in FIG.

A transmission data memory (SDM) (73) for storing transmission control data (DCC _S ) and a reception data memory (RDM) for storing reception control data (DCC _R )
(74) serves as the storage means (200) in FIG.

That is, the transmission data memory (S
DM) (73) and receive data memory (RDM) (7
4) is a storage means (200) according to the present invention (claim 3).
It can also be considered as the embodiment of.

Data Control Processor (DPU) (75)
Serves as a communication sequence data insertion means (400) in FIG. 1 and also serves as a control data transmission / reception circuit (ADP).
Controls the overall control of (7).

Address translation memory (ACM) (76)
Serves as the address translation means (300) in FIG. 3 and 4, the line interface (LIF) (71) is a switch processor (BCP).
R) Transmission control data (DCC _S ) to be transferred to (5)
When [4096 bytes long] is generated, the data control processor (DPU) (75) is requested to store in the transmission data memory (SDM) (73).

Data Control Processor (DPU) (75)
Controls when storing and extracting control data (DCC) between the line interface (LIF) (71) and the transmission data memory (SDM) (73) or the reception data memory (RDM) (74). Specify only the storage start address of data (DCC) and the data length, and then continuously update the address to store or extract 1 byte.
Since the so-called DMA transfer system is adopted, the transmission data memory (SDM) (73) or the reception data memory (RD
The storage address or extraction address input to M) (74) is a continuous address.

Data Control Processor (DPU) (75)
Is a line interface (LIF) (71) based on a request from the line interface (LIF) (71).
Extract the transmission control data (DCC _S ) from 1 byte to
Send data memory (SDM) (SDM) (73) Transfer data memory (SDM) that stores each byte
Addresses of (73) that change continuously, for example, from the 0th address to the 4095th address [the subsequent address (a _DCC )
Called], and the transmission data memory (SDM) (7
Address translation memory (ACM) instead of sending to 3)
Transfer to (76).

Address translation memory (ACM) (76)
The continuous address (a _DCC ) transmitted from the data control processor (DPU) (75) is 1 for every 43 addresses.
The address is converted into a _divided address (a _dcc ) provided with a blank area and transmitted to the transmission data memory (SDM) (73).

The division address (a _dcc ) uses the first address 0 as a blank area, and the first 4 addresses of the continuous address (a _DCC ).
3 addresses [0th to 42nd addresses] are converted into 1st to 43rd addresses of the division address (a _{dc c} ), the following 44th address is made a blank area, and the next address of the continuous address (a _DCC ) 43 addresses [43rd to 85th addresses] are converted to 45th to 87th addresses of the division address (a _dcc ),
The following 88th address is set as a blank area, and the next 43th address of the continuous address (a _DCC ) [86th to 128th addresses]
Address] to the 89th address through the 1st address (a _dcc )
Convert to address 31, and repeat the same conversion.

As a result, the data control processor (DP
U) (75) is the line interface (LIF) (7
Extract 1 byte from 1) and send data memory (SD
M) Transmission control data (DCC _S ) transmitted to (73)
Is divided into partial control data (dcc) addressed to 43 bytes, and a blank area for one byte is provided at the beginning of each partial control data (dcc) to provide a transmission data memory (SDM) (7
It is accumulated in 3).

Data Control Processor (DPU) (75)
When all the transmission control data (DCC _S ) have been accumulated in the transmission data memory (SDM) (73), the communication sequence data indicating the sequence of each partial control data (dcc) in the transmission control data (DCC _S ) (CSD) [for example, No. 0 to No. 95] is created, and transmission data memory (SDM) (7
3) The partial control data (dcc) in (3) is sequentially accumulated in each blank area provided at the head.

From the above, the line interface (LI
F) (71) to transmission data memory (SDM) (73)
The transmission control data (DCC _S ) transmitted to the ATM is divided into partial control data (dcc) addressed to 43 bytes, the communication sequence data (CSD) is added to the head, and each ATM cell (C) has a length of 44 bytes. Of the transmission data memory (SDM) (73) with a configuration corresponding to the payload section (P) of
It has been accumulated in.

Data Control Processor (DPU) (75)
After storing the transmission control data (DCC _S ) in the format of the payload section (P) in the transmission data memory (SDM) (73), the network interface (NIF)
Switch Processor (BCPR) for (72) (5)
Request transfer to.

Network interface (NIF)
(72) sequentially extracts a payload portion (P) having a length of 44 bytes from the transmission data memory (SDM) (73), and a header portion (H) [8 byte length] and trailer portion (T) [of a predetermined format]. 2 bytes length] is added to assemble an ATM cell (C), and the ATM cell (C) is transferred to the signal controller (BSGC) (4) via the ATM switch (ATM) (3).

A network interface (NI
F) (72), the signal control device (BSGC) (4) from the ATM switch (ATM) (3) receiving control data transferred via the (DCC _R) ATM cells for transfer (C)
When it receives, it is decomposed into a header part (H), a payload part (P) and a trailer part (T), and the payload part (P) is received in a reception data memory (RDM) (74) in the order of arrival [or communication sequence data ( (According to the order indicated by CSD)].

One line system interface (LIF) (7
1) The extraction of the reception control data (DCC _R ) transferred from the exchange processor (BCPR) (5) and accumulated in the reception data memory (RDM) (74) to the data control processor (DPU) (75). Request.

Data Control Processor (DPU) (75)
Is the line-based interface (LIF) (71) based on a request from the reception data memory (RDM) received control data from (74) to (DCC _R) and 1 byte addressed extraction, line-based interface (LIF) (71) Continuous address (a _DCC ) for transfer to the address conversion memory (AC
M) (76) and line interface (LIF)
Transmit to (71).

Address translation memory (ACM) (76)
Is a data control processor (DPU), as described above.
The continuous address (a _DCC ) transmitted from (75) is set to 4
Received data memory (RDM) by converting into a _divided address (a _dcc ) with a blank area of 1 address for every 3 addresses
(74).

As a result, the reception data memory (RDM)
From (74), the network interface (NI
F) Only partial control data (dcc) excluding the communication sequence data (CSD) of each payload part (P) continuously accumulated from (72) is extracted to 1 byte, and the line interface (LIF) (71).

Line interface (LIF) (71)
Restores the reception control data (DCC _R ) by the partial control data (dcc) transmitted to 1 byte. Next, an embodiment of the present invention (claim 2) will be described with reference to FIG.

The control data transmission / reception circuit (A
The DP) (7) differs from the control data transmission / reception circuit (ADP) (7) shown in FIG. 4 only in the address translation memory (ACM) (76).

The address translation memory (AC
M) (76) is a continuous address (a) input from the data control processor (DPU) (75) as described above.
_DCC ) was converted into a fixed section address (a _dcc ) with one blank area inserted for every 43 addresses.

The data lengths of the control data (DCC) and the partial control data (dcc) are as shown in FIG.
In the case of 4096 bytes and 43 bytes, respectively, the total number of partial control data (dcc) divided from the control data (DCC) becomes 96, and the 1-byte length communication sequence data (CSD) identifies a sufficient sequence. However, when the data length of the control data (DCC) increases, the total number of partial control data (dcc) divided from the control data (DCC) becomes 256 or more, and the communication of 1-byte length is possible. It becomes impossible to identify the sequence by the sequence data (CSD), and the communication sequence data (C
It becomes necessary to adopt SD).

In FIG. 5, communication sequence data (CS
An address conversion memory (ACM) (76) is adopted which is capable of converting into a division address ( _adcc ) which can be dealt with when the data length of D) is variable.

That is, the data control processor (DPU) (7
5) analyzes the data length of the control data (DCC) to be transferred, calculates the required data length [number of bytes] of the communication sequence data (CSD), and uses the calculated data length for the division address ( _adcc ) Is the address translation memory (AC
M) (76) is stored corresponding to each continuous address (a _DCC ).

That is, 2 bytes of communication order data (CSD)
Classification address (a _dcc) Is the first
Addresses 0 and 1 are blank areas and continuous addresses
(A_{DC C}) First 43 addresses [0th to 42nd
Ground] to the classification address (a_dcc) No. 2 to No. 44
Converted to land and blank the following 45th and 46th
And the continuous address (a_DCC43) next to [)
No. 43 to No. 85] are classified addresses (a_dcc)of
Converted from No. 47 to No. 89 and continue to No. 90
Addresses 91 and 91 are blank areas and continuous addresses
(A_DCC) Next 43 addresses [86th to 128th]
Address]_dcc) No. 92 to No. 1
Convert to address 34, and repeat the same conversion.

More generally, consecutive addresses (a _DCC )
The relationship between the address and the section address (a _dcc ) is expressed by the following equation. a _dcc = {INT [a _DCC / b _dcc ] +1} b _CSD + a
_DCC However, b _dcc : Data length of partial control data (dcc) b _CSD : Data length of communication sequence data (CSD) INT [a _DCC / b _dcc ]: a _DCC / b _dcc Maximum integer less than Since this is the same as the control data transmitting / receiving circuit (ADP) (7) according to the embodiment of the present invention (Claim 1), detailed description of the operation will be omitted.

Next, an embodiment of the present invention (claim 4) will be described with reference to FIG.
Will be explained. The control data transceiver circuit (ADP) (7) shown in FIG. 6 is different from the control data transceiver circuit (ADP) (7) shown in FIG.
0) is a portion corresponding to [FIG. 1].

The control data transmission / reception circuit (A
DP) (7), send data memory (SDM)
(73) and the reception data memory (RDM) (74) played the role of the storage means (200) [FIG. 1], whereas the control data transmission / reception circuit (ADP) shown in FIG.
In (7), the transmission / reception data memory (CDM) (7
7), line system address table (LAT) (78), network system address table (NAT) (79), line system data buffer (LDB) (7A) and network system data buffer (NDB) (7B). 200).

In FIG. 4, the subscriber circuit (BSLI
C) The transmission control data (DCC _S ) that the (2) transfers to the exchange processor (BCPR) (5) is stored in the transmission data memory (SDM) (73), and the exchange processor (BCPR) (5) is the subscriber. Circuit (BSLIC) (2)
The reception control data (DCC _R ) to be transferred to the device was stored in the reception data memory (RDM) (74).

Each of the transmission data memory (SDM) (73) and the reception data memory (RDM) (74) has a storage capacity capable of sufficiently storing a required amount of transmission control data (DCC) or reception control data (DCC). However, it is unlikely that the transmission data memory (SDM) (73) and the reception data memory (RDM) (74) simultaneously store control data (DCC) close to the storage capacity, either one or both. Often leaves a lot of free storage space.

The control data transmission / reception circuit (A
DP) (7) is such a transmission data memory (SDM)
(73) and the receiving data memory (RDM) (74) are used in consideration of the usage state of the storage means (200).

In FIG. 6, the storage means (200) is
Transmission control data (DCC_S) And reception control data (D
CC_RTransmission / reception data memory (CDM) shared by
(77), the transmission control data (DCC
_S) And reception control data (DCC _R) Is the sent / received data
It is stored in the memory (CDM) (77).

As a result, the transmission / reception data memory (CDM)
The storage capacity of (77) can be determined in consideration of the fluctuation of the total transfer amount of the transmission control data (DCC _S ) and the reception control data (DCC _R ), and the transmission data memory (SDM)
(73) and the reception data memory (RDM) (74) have a smaller storage capacity than the total storage capacity, and the utilization efficiency is improved.

A transmission / reception data memory (CDM) (7
If the utilization improvement of 7) is extremely pursued, the total transfer amount of the transmission control data (DCC _S ) and the reception control data (DCC _R ) is more likely to exceed the storage capacity of the transmission / reception data memory (CDM) (77). Transmission / reception data memory (C
DM) (77) cannot be stored, and control data (DC
The risk of C) being discarded increases.

The control data transmission / reception circuit (A
DP) (7), the line system data buffer (LDB) in order to relieve the discard of the transmission control data (DCC)
(7A) is provided, and a network data buffer (N) is provided to relieve the discard of the reception control data (DCC).
DB) (7B) is provided, and when the transmission / reception data memory (CDM) (77) is completely blocked, the line data buffer (LDB) (7A) or network data buffer (NDB) (7B) ), And the transmission / reception data memory (CDM) (77) becomes available from the line data buffer (LDB) (7A) or network data buffer (NDB) (7B) as soon as the transmission / reception data memory (CDM) (77) becomes available. 77).

A transmission / reception data memory (CDM) (7
7), the transmission control data (DC
C _S) and receive control data (DCC _R) because it becomes possible to accumulate a mix, the data control processor (DP
U) (75) and network interface (N
IF (72) is the transmission / reception data memory (CDM) (7
In order to always identify the storage areas of the transmission control data (DCC _S ) and the reception control data (DCC _R ) in ₇ ), the line address table (LAT) (78) and the network address table (NAT) (79) Is provided.

As shown in FIG. 8, the line address table (LAT) (78) includes a transmission / reception data memory (CD).
M) When storing transmission control data (DCC _S1 ) and (DCC _S2 ) in (77), each transmission control data (DCC _S1 )
C _S1 ) and (DCC _S2 ) start addresses (sa ₁ ) and (sa ₄ ) and data lengths (b _DCCS1 ) and (b)
_DCCS2 ) is stored in the network address table (NAT) (79), as shown in FIG.
When storing the reception control data (DCC _R1 ) and (DCC _R2 ) in the transmission / reception data memory (CDM) (77),
The start address (sa ₂ ) and (sa ₃ ) of each reception control data (DCC _R1 ) and (DCC _R2 ) and the data length (b _DCCR1 ) and (b _DCCR2 ) are stored.

Data Control Processor (DPU) (75)
Or network interface (NIF) (7
2) is a transmission / reception data memory (CDM) (7) for transmitting control data (DCC _S ) or receiving control data (DCC _R ).
When extracting from 7), the line address table (LAT)
(78) or network address table (NAT)
By referring to (79), the storage areas of the transmission control data (DCC _S ) and the reception control data (DCC _R ) can be confirmed.

Other functions are the same as those of the control data transmission / reception circuit (ADP) (7) according to the embodiment of the present invention (claim 1), and thus detailed description of the operation is omitted. On the other hand, FIG.
Shows a control data transmitting / receiving circuit (ADP) (7) according to an embodiment of the present invention (claim 5).

The control data transmission / reception circuit (ADP) (7) shown in the communication path (10) has a transmission data memory (SDM) (73) and a reception data memory (R) shown in FIG.
The DM) (74) and the transmission / reception data memory (CDM) (77) shown in FIG. 6 are both provided.

However, the transmission data memory (SDM) (73)
The storage capacity of the reception data memory (RDM) (74) is equal to that of the transmission data memory (SDM) (73) in FIG.
And a smaller capacity than the reception data memory (RDM) (74), and the transmission / reception data memory (CDM)
The storage capacity of (77) is also set smaller than that of the transmission / reception data memory (CDM) (77) in FIG.

In the control data transmission / reception circuit (ADP) (7) shown in FIG. 10, the transmission control data (DC
C _S) is first stored in the transmission data memory (SDM) (73), the first received data memory at the time of the transmission data memory (SDM) (73) is all blocked (CDM) (77)
Further, the reception control data (DCC _R ) is first accumulated in the reception data memory (RDM) (74), and the transmission / reception data memory (CDM) (CDM) (CDM) ( 77).

As described above, the transmission data memory (SDM)
(73), the reception data memory (RDM) (74) and the transmission / reception data memory (CDM) (77) are always used at a high rate, and as a result, each storage capacity is also reduced.

A transmission / reception data memory (CDM) (7
With the use of 7), the line address table (LAT)
(78) and network address table (NAT)
(79), and the line data buffer (LDB) (7
A) and network data buffer (NDB)
The point of using (7B) together is that the control data transmitting / receiving circuit (ADP) (7) according to the embodiment of the present invention (claim 4) [FIG.
See) is no different.

Since the other functions are the same as those of the control data transmitting / receiving circuit (ADP) (7) according to the embodiment of the present invention (claim 1), detailed description of the operation will be omitted. As is clear from the above description, according to the embodiment of the present invention (Claim 1), the control data transmitting / receiving circuit (ADP) (7) should transfer the control data (DCC) to the exchange processor (BCPR) (5). Of the partial control data (dc
c), each of which is added with communication sequence data (CSD) and once stored in the transmission data memory (SDM) (73), and then assembled into an ATM cell (C), and then an ATM switch (ATM) (3) and a signal. Controller (BSGC)
Switch Processor (BCPR) via (4) (5)
Control data (DCC) transmitted from the switch processor (BCPR) (5) through the signal controller (BSGC) (4) and the ATM switch (ATM) (3) in the ATM cell (C) format. ), The payload part (P) is once stored in the reception data memory (RDM) (74), and only the partial control data (dcc) is extracted to restore the control data (DCC). (ATM) (3) and signal controller (BSG
C) It becomes unnecessary to provide a communication path (10) [see FIG. 11] dedicated to control data (DCC) transfer in addition to the general cell transfer path passing through (4).

Further, according to the embodiment of the present invention (claim 2), even when the communication sequence data (CSD) requires 2 bytes or more, it can be sufficiently processed. According to the embodiments of the present invention (claim 3) to (claim 5), the storage means (200) includes a transmission data memory (SDM) (73), a reception data memory (RDM) (74) and a transmission / reception data memory. (CDM) (77) is realized by a part or all of the above, thereby saving the storage capacity of the storage means (200),
The utilization rate can be improved.

2 to 10 are merely examples of the present invention, and the data lengths of the control data (DCC) and the partial control data (dcc) are not limited to those shown in the drawings. However, many other modifications can be considered, but the effect of the present invention does not change in any case. Needless to say, the ATM exchange which is the subject of the present invention is not limited to the one shown in the figure.

[0076]

As described above, by providing the control data transmission / reception circuit according to the present invention to each subscriber circuit in the ATM switch, it is possible to convert the control data which each subscriber circuit exchanges with the switch processor into cells. Then, the broadband terminal accommodated in the ATM exchange can transfer data via various cell transfer paths similar to the control information in the cell format exchanged with the exchange processor, and between the subscriber circuit and the exchange processor. Since it is not necessary to provide a dedicated communication path for control data transfer, the economical efficiency of the ATM switch is greatly improved.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing an ATM exchange according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of an ATM cell format in FIG.

FIG. 4 is a diagram showing a control data transmission / reception circuit according to an embodiment of the present invention (claim 1).

FIG. 5 is a diagram showing a control data transmitting / receiving circuit according to an embodiment of the present invention (claim 2).

FIG. 6 is a diagram showing a control data transmission / reception circuit according to an embodiment of the present invention (claim 4).

7 is a diagram showing an example of a transmission / reception data memory in FIG.

8 is a diagram showing an example of a line address table in FIG.

9 is a diagram showing an example of a network address table in FIG.

FIG. 10 is a diagram showing a control data transmission / reception circuit according to an embodiment of the present invention (claim 5).

FIG. 11 is a diagram showing an example of a conventional ATM exchange.

[Explanation of symbols]

1 ATM switch 2 Subscriber circuit (BSLIC) 3 ATM switch (ATM) 4 Signal control device (BSGC) 5 Switch Processor (BCPR) 6 Broadband terminal (BTE) 7 Control data transceiver circuit (ADP) 10 communication channels 71 Line interface (LIF) 72 Network interface (NIF) 73 Transmission data memory (SDM) 74 Received data memory (RDM) 75 Data Control Processor (DPU) 76 Address conversion memory (ACM) 77 Transmission / Reception Data Memory (CDM) 78 Line address table (LAT) 79 Network Address Table (NAT) 7A Line system data buffer (LDB) 7B Network data buffer (NDB) 100 data transmission / reception means 200 storage means 300 address conversion means 400 Communication sequence data insertion means 500 cell assembly / disassembly means

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-8-18568 (JP, A) JP-A-3-106247 (JP, A) JP-A-2-123850 (JP, A) JP-A-7- 177155 (JP, A) JP-A-5-268253 (JP, A) Patent 3357423 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/56 300 H04L 12/24

Claims (5)

(57) [Claims] 1. An ATM switch constituting a speech path switch.
Control circuit between the subscriber circuit and the switch processor via the switch.
A control data transmission / reception circuit that transfers data, dividing variable-length control data into fixed-length partial control data.
Data transmission / reception means for inputting control data having a predetermined length or less together with a series of consecutive address groups and accumulating in accumulating means, and inputting the consecutive address groups into the accumulating means for extracting the control data being accumulated, A storage unit that stores the control data, and the continuous address group that the data transmission / reception unit outputs to store or extract the control data in the storage unit, the control data being a partial data having a predetermined data length. In the beginning of each partial data, a blank area in which communication order data indicating the order of each partial data in the control data can be inserted is provided and converted into a group of address groups for storing in the storing means. Address converting means for inputting to the accumulating means, and at the head of each partial data accumulated in the accumulating means from the data transmitting / receiving means, A communication order data insertion unit for adding communication order data indicating the order in the control data, and each partial data with the communication order data accumulated in the accumulating unit from the data transmitting / receiving unit, and a cell of a predetermined length. A cell assembling / disassembling means for assembling and transmitting to the cell transfer path, disassembling the cell type control data arriving from the cell transfer path to extract the partial data with the communication sequence data, and storing the partial data in the storage means. A control data transmission / reception circuit characterized by being provided. 2. The control data according to claim 1, wherein the address conversion means can change the length of a blank area into which the communication sequence data can be inserted, in accordance with an instruction from the data transmission / reception means. Transceiver circuit. 3. The data stored in the data transmitting / receiving means and extracted by the cell assembling / disassembling means is stored in the storing means,
2. The control data transmission / reception circuit according to claim 1, wherein dedicated storage means is provided for each of the data stored by the cell assembling / disassembling means and extracted by the data transmitting / receiving means. 4. The storage means stores the data stored in the data transmitting / receiving means and extracted by the cell assembling / disassembling means,
2. The control data transmitting / receiving circuit according to claim 1, wherein the cell assembling / disassembling means stores the storage data, and the storage means is shared with the data extracted by the data transmission / reception means. 5. The data stored in the data transmitting / receiving means and extracted by the cell assembling / disassembling means are stored in the storing means.
2. The control data transmitting / receiving circuit according to claim 1, wherein the cell assembling / disassembling means stores the data and the data transmitting / receiving means extracts a dedicated storing means and a common storing means.