JPH07201184A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the chip area, to enhance economy and to accelerate the word line selection operation by performing the connecting inside division memory cell array driven by a common address decoder in a prescribed manner. CONSTITUTION:Plural division memory cell arrays ARY0-ARY3 are driven by the common address decider XD. A word line decoding signal being the output of the decoder XD is transmitted to a sub-word drive circuit SD0 through main word lines MW0B-MW511B arranged on an upper layer of a memory cell MC in the memory cell array ARY0. On the other hand, the sub-word lines SW0-SW511 constituting the ARY0 form gates of selection FETs of cells MC by a single polysilicon layer, and are connected to word shunt lines SSW 0-SSW511 of the upper layer of the sub-word lines. Similar connection is executed in the arrays ARY1-ARY3, and by such a connection, contraction at the process of wafer is prevented, and no reliability is reduced, and a layout area is reduced, and the distribution resistance of the sub-word lines are reduced, and economy and the operation speed are enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a static RAM (random access memory) adopting a so-called divided word line system, and a technique particularly effective when used for speeding up and cost reduction thereof. Is.

[0002]

2. Description of the Related Art There is a static type RAM having a memory array in which static type memory cells are arranged in a lattice as a basic constituent element. Further, in such a static RAM or the like, there is a divided word line system in which the memory array is divided in the extension direction of the word lines to reduce the load on the word lines and to speed up the word line selection operation.

Static type R adopting a divided word line system
Regarding AM, for example, "IEEE JOURNAL
OF SOLID STATE CIRCUIT O
ct. 1990, Vol. 25, No. 5, pp. 10
57-1062 ".

[0004]

Prior to the present invention, the inventors of the present invention developed a high-speed static type RAM adopting the above-mentioned divided word line system. For example, as shown in FIG. 7, this static RAM includes X address decoders XD0 and the like provided corresponding to memory arrays ARY0L and ARY0R, and these X address decoders include word lines W0L to W511L and W.
Unit word line drive circuits UWD0 to UWD511 provided corresponding to 0R to W511R, respectively. The unit word line drive circuits UWD0 to UWD511 receive a 2-input NAND gate for receiving the predecode signals XP0 to XPk in a corresponding predetermined combination, and an output signal of the NAND gate corresponding to one of its input terminals, and the other one. Inversion selection drive signal WD0B corresponding to the input terminal of
(Here, a so-called inverted signal or the like that is selectively brought to a low level when it is validated is indicated by adding B to the end of the name. The same applies hereinafter) and the like, a pair of NOR gates. Including and

As a result, the word lines W0L to W511L and W0R to W511R forming the memory arrays ARY0L and ARY0R are predecode signals XP0 to XP0.
When XPk is set to the high level in the corresponding combination and the corresponding inversion selection drive signal WD0B or the like is set to the low level, the selection state of the high level is selectively established. At this time, word lines W0L to W511L and W0R to W
The selection operation of the 511R or the like is accelerated by reducing the load by dividing the word lines and providing the X address decoder XD0 or the like corresponding to each memory array, thereby accelerating the access time of the static RAM. It will be one.

However, when the static RAM is increased in scale and speed and the number of word lines, that is, the number of divided memory arrays is increased, an X address decoder is provided for each memory array in the system of FIG. The number of circuit elements in the array and the X address decoder section increases, the required layout area increases, the chip area of the static RAM and the like increases, and the cost reduction is restricted.

In order to deal with this, for example, as shown in FIG. 8, the X address decoder XD is shared by a plurality of memory arrays, and its output signal, that is, the word line decode signal is transmitted via a plurality of main word lines MW0B to MW511B. Memory array AR
A method of reducing the chip area is provided by providing a sub word line drive circuit SD0 or the like having no substantial decoding function corresponding to Y0L and ARY0R and the like. However, in this case, the sub-word lines SW0L to SW511L and SW0 forming the memory arrays ARY0L and ARY0R, etc.
Since R to SW511R and the like are formed in a single pattern as the gate of the selection MOSFET by using polysilicon or the like having a relatively large distributed resistance value, the resistance of the sub-word line becomes large and the selection operation becomes slow, and the static RA
Speeding up of M etc. is restricted. In addition, the memory arrays ARY0L and A that form a pair with the sub-word line drive circuit SD0 and the like.
Since it is arranged in the middle of RY0R and the like, the number of junctions between the memory array that is relatively easy to highly integrate and the logic circuit that is difficult to highly integrate is large, the layout efficiency is reduced, and the chip area such as static RAM is expected. Not reduced to.

Further, in order to deal with this problem, sub word lines SW0L to SW511L and SW0R to SW are provided.
A method of backing the 511R or the like with a silicide or the like having a relatively small distributed resistance value to reduce the resistance value is also adopted, but in this case, the silicide shrinks in the wafer process or the like to damage the gate oxide film. On the contrary, there arises a problem that the reliability of the static RAM is lowered.

An object of the present invention is to reduce the chip area and reduce the cost without deteriorating the reliability of a static type RAM adopting the divided word line system, and speeding up the word line selecting operation. To speed up access time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like adopting the divided word line system, an X address decoder is provided commonly to a plurality of divided memory arrays, and its output signal, that is, a word line decoded signal, is stored in a corresponding memory cell formed of a metal wiring layer. While transmitting to the plurality of sub-word line drive circuits via the main word line arranged in the upper layer, the sub-word lines forming each memory array are formed of polysilicon in a single layer in a single pattern as the gate of the selection MOSFET of the memory cell. Corresponding to each sub-word line, a word shunt line, which is formed of a metal wiring layer and is arranged in the upper layer of the corresponding memory cell, is coupled to the corresponding sub-word line at a plurality of positions. Further, the sub-word line drive circuit provided corresponding to each memory array is arranged inside a pair of memory arrays arranged adjacent to each other.

[0012]

According to the above-mentioned means, the required layout area of the memory array and the X address decoder can be reduced while preventing the wiring layer from shrinking in the wafer process.
The distributed resistance of the sub-word lines forming each memory array can be reduced, and the operation of selecting the word lines can be speeded up.
As a result, the static type RA adopting the divided word line system
It is possible to reduce the chip area, reduce the cost, and speed up the access time without reducing the reliability of M and the like.

[0013]

1 is a block diagram of an embodiment of a static RAM to which the present invention is applied. 2 and 3 are respectively a circuit diagram and a connection diagram of one embodiment of the memory array ARY0 included in the static RAM of FIG. 1, and FIG. 4 includes the static RAM of FIG. The circuit diagram of one embodiment of the X address decoder XD is shown. Based on these figures, first, the structure and operation of the static RAM of this embodiment and its structural features will be described. The circuit elements forming each block in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. Also, in the circuit diagram below, the channel (back gate)
MOSFET (metal oxide semiconductor type field effect transistor. In this specification, the
Is collectively referred to as an insulated gate field effect transistor), which is a P-channel type and is shown separately from an N-channel MOSFET without an arrow. Furthermore, the following description regarding the memory arrays ARY0 to ARY3 will be given.
The memory array ARY0 can be taken as an example, but since the memory arrays ARY1 to ARY3 have the same configuration as this, it should be analogized.

In FIG. 1, the static RAM of this embodiment is not particularly limited, but is divided into four memory arrays ARY0 divided in the extension direction of word lines and arranged in series.
~ ARY3 is its basic component. The static RAM further includes four sub word line drive circuits SD0 to SD0 provided corresponding to the memory arrays ARY0 to ARY3.
SD3 is provided, and these sub-word line drive circuits have a corresponding selection drive signal W from a mat selection circuit MS described later.
D0 to WD3 are supplied respectively.

The memory arrays ARY0 to ARY3 are shown in FIG.
As represented by the memory array ARY0, 512 sub word lines SW0 to SW511 arranged in parallel in the horizontal direction of the figure and 128 sets of complementary bit lines B0 arranged in parallel in the vertical direction. * To B127 * (Here, for example, the non-inverted bit line B0T and the inverted bit line B0
B is also indicated by adding * like complementary bit line B0 *. Further, a so-called non-inverted signal or the like which is selectively set to a high level when it is validated is indicated by adding T to the end of its name. The same applies hereinafter) and 512 × 128 or 65536 static memory cells MC arranged in a grid pattern at the intersections of these sub-word lines and complementary bit lines, respectively. As a result, each of the memory arrays ARY0 to ARY3 has 65536
Bits, or so-called 64 kilobits, has a storage capacity, and static RAM has a storage capacity of 4 × 64 kilobits, or 256 kilobits.

As illustrated in FIG. 2, the memory cells MC forming the memory arrays ARY0 to ARY3 respectively include a pair of N-channel type drive MOSFETs N1 and N2 whose gates and drains are cross-coupled to each other. The sources of drive MOSFETs N1 and N2 are coupled to the circuit ground potential. In addition, its drain is coupled to the power supply voltage of the circuit through the corresponding high resistance load R1 or R2, and also an N-channel type selection MOSFET.
Corresponding complementary bit lines B0 * to B via N3 or N4
It is coupled to the 127 * non-inverting or inverting signal line. Choice M
The gates of the OSFETs N3 and N4 are coupled to the corresponding sub word lines SW0 to SW511. The power supply voltage of the circuit is a positive power supply voltage such as + 5V.

In this embodiment, the sub word line SW0
.. to SW511 are composed of a polysilicon single layer as will be described later, and 128 selection MOSFETs N3 and N arranged in corresponding rows of the memory arrays ARY0 to ARY3.
The four gates are formed in a single pattern.
Further, the memory arrays ARY0 to ARY3 are further provided in parallel with the sub word lines SW0 to SW511, and 512 word shunt lines SSW0 to SSW511 coupled to the corresponding sub word lines SW0 to SW511 at three locations including the central portion thereof. including. These word shunt lines are made of a first aluminum wiring layer having a distribution resistance value sufficiently smaller than that of the polysilicon layer. As a result, the sub-word lines SW0 to SW511, as shown in FIG. 3, correspond to the corresponding word shunt lines SSW0 to SS.
The shape is lined with W511, which reduces the substantial distributed resistance value.

By the way, the sub-word line drive circuits SD0 to SD0
As represented by the sub-word line drive circuit SD0 in FIG. 2, SD3 includes 512 unit sub-word line drive circuits provided corresponding to the word shunt lines SSW0 to SSW511 of the memory arrays ARY0 to ARY3, that is, the sub word lines SW0 to SW511. It includes USD0 to USD511, respectively. These unit sub word line drive circuits are shown in FIG.
Of the unit sub-word line drive circuit USD0, the P-channel MOSFET P6 provided between the selection drive signal lines WD0 to WD3 and the corresponding word shunt lines SSW0 to SSW511 and the corresponding word shunt lines SSW0 to. Two N-channel MOSs provided in parallel between the SSW 511 and the ground potential of the circuit
It includes FETs N5 and N6, respectively. Of these, MO
The selection drive signals WD0 to WD are provided to the gate of the SFETN5.
The inverted signal from the inverter V1 of 3 is supplied. The gates of the MOSFETs P6 and N6 are connected to the corresponding main word line MW0B through the X address decoder XD.
Corresponding word line decode signals MW0B to MW511B are commonly supplied via MW511B.

Incidentally, the main word lines MW0B to MW51.
As will be described later, 1B is formed of a first aluminum wiring layer, and is linearly arranged in a layer above a total of 512 memory cells MC arranged in corresponding rows of memory arrays ARY0 to ARY3. In addition, word line decode signals MW0B to MW transmitted via these main word lines.
511B is at a high level like the power supply voltage of the normal circuit, and when the static RAM is in the selected state, X
According to the address signals AX0 to AX8, that is, the internal address signals X0 to X8, it is alternatively set to the low level like the ground potential of the circuit. Furthermore, the selection drive signals WD0 to WD
3 is normally at a low level, and when the static RAM is in a selected state, Z address signals AZ0 to AZ1.
That is, it is alternatively set to the high level according to the internal address signals Z0 to Z1.

From these facts, the memory array ARY0
To sub-word lines SW0 to SW511 forming ARY3
Indicates that the corresponding selection drive signals WD0 to WD3 are at high level and the corresponding word line decode signals MW0B to MW0.
On condition that W511B is at the low level, in other words, if the logical levels of the X address signals AX0 to AX8 and the Z address signals AZ0 to AZ1 are in a corresponding combination, the selected state of the high level is selectively selected. It will be what is said. As described above, the sub word lines SW0 to SW511 are connected to the corresponding word shunt line S.
It is lined with SW0 to SSW511, and its distributed resistance value is reduced. Therefore, the high level change of the sub word lines SW0 to SW511 according to the above conditions is correspondingly speeded up, and the selection operation thereof is speeded up accordingly.

The X address decoder XD has 9-bit internal address signals X0 to X from the X address buffer XB.
8 is supplied, and the internal control signal CS1 is supplied from the timing generation circuit TG. Also, the X address buffer XB
Are supplied with X address signals AX0 to AX8 via address input terminals AX0 to AX8.

The X address buffer XB has an address input terminal A when the static RAM is selected.
X address signal AX0 supplied via X0 to AX8
.About.AX8 are fetched and held, and internal address signals X0 to X8 are formed based on these X address signals and supplied to the X address decoder XD.

As shown in FIG. 4, the X address decoder XD has a total of 24 NAND gates NA00 to NA0.
7, NA10-NA17 and NA20-NA27
And 512 main word line drive circuits UMD0 provided corresponding to the main word lines MW0B to MW511B.
~ UMD511. Of these, Nand Gate NA
The internal control signal C is connected to the first input terminals of 00 to NA07.
S1 is commonly supplied, and non-inverted or inverted signals of the 3-bit internal address signals X0 to X2 are supplied to the second to fourth input terminals in a predetermined combination. Also,
Non-inverted or inverted signals of the 3-bit internal address signals X3 to X5 are supplied to the first to third input terminals of the NAND gates NA10 to NA17 in a predetermined combination, and the first to third input terminals of the NAND gates NA20 to NA27 are supplied. Non-inverted or inverted signals of the 3-bit internal address signals X6 to X8 are supplied to the input terminal in a predetermined combination. The output signals of the NAND gates NA00 to NA07 are predecode signals XPD00 to XPD07. Further, the output signals of the NAND gates NA10 to NA17 are predecode signals XPD10 to XPD17, and the NAND gate N
The output signals of A20 to NA27 are predecode signals XP.
D20 to XPD27.

As a result, the predecode signal XPD00
To XPD07 are the 3-bit internal address signals X0 to X2 in which the internal control signal CS1 is at a high level.
When the non-inverted or inverted signals of are simultaneously set to the high level in the corresponding combination, they are selectively set to the low level.
Further, the predecode signals XPD10 to XPD17 are selectively set to low level when the non-inverted or inverted signals of the corresponding 3-bit internal address signals X3 to X5 are set to high level all at once, and the predecode signals XPD10 to XPD17 are predecoded. The signals XPD20 to XPD27 are selectively set to the low level when the non-inverted or inverted signals of the corresponding 3-bit internal address signals X6 to X8 are simultaneously set to the high level in a corresponding combination.

On the other hand, the main word line drive circuits UMD0 to UMD0
The UMD 511 is the main word line drive circuit UMD of FIG.
As represented by 0, P-channel MOSFE
TP7 to P9, N-channel MOSFETs N7 to N9, and an inverter V2, which are substantially three-input OR gates, are the constituent elements. The first input terminals of these OR gates, namely MOSFETs P7 and N7
The corresponding predecode signals XPD00 to XPD07 are supplied to the common-coupled gates of the respective gates, and their second and third input terminals, that is, MOSFETs P8 and N8.
The corresponding predecode signals XPD10 to XPD17 or XPD20 to XPD27 are supplied to the commonly connected gates of P9 and N9, respectively. The output signal of each OR gate is output to the corresponding main word line MW0B to MW511B as the corresponding word line decode signal MW0B to MW511B.

As a result, the main word lines MW0B-M
W511B, that is, the word line decode signals MW0B to MW
511B is a predecode signal XPD00 to XPD0.
7, XPD10 to XPD17 and XPD20 to XP
When D27 is simultaneously set to the low level in a corresponding combination, in other words, when the internal control signal CS1 is set to the high level and the logical levels of the X address signals AX0 to AX8 are set to the corresponding combination, the combination is selectively set to the low level. Will be done.

As described above, in this embodiment, the X address decoder XD having the decoding function is the memory array A.
While being shared by RY0 to ARY3, the sub word line drive circuits SD0 to SD3 do not have a decoding function, and accordingly the circuit configuration thereof is simplified. As a result,
It is possible to reduce the required layout area of the memory array and the X address decoder section, thereby reducing the chip area of the static RAM and promoting its cost reduction.

Next, the complementary bit lines B0 * to B127 * forming the memory arrays ARY0 to ARY3 correspond to the corresponding bit line precharge circuit BPC0 in the upper part of FIG.
~ BPC127, and corresponding switch MO of Y switches YS0 to YS3 (not shown) below it.
Coupled to the SFET.

Here, the bit line precharge circuit BPC
0 to BPC127 are, as represented by the bit line precharge circuit BPC0 in FIG. 2, represented between the power supply voltage of the circuit and the corresponding non-inverted and inverted signal lines of the complementary bit lines B0 * to B127 *, and the corresponding bit lines. Complementary bit line B0 *
~ B127 * total of five P-channel MOSFETs P1 to P5 provided between the non-inverting and inverting signal lines
Including each. Of these, MOSFETs P1 and P2
Has its gate and drain cross-coupled to form a so-called latch form. Further, the internal control signals PC0 to PC3 are commonly supplied to the gates of the MOSFETs P3 to P5. The internal control signals PC0 to PC3
Is normally at the low level, the static RAM is in the selected state, and the corresponding selection drive signals WD0 to WD3
Is set to a high level, in other words, when the corresponding memory arrays ARY0 to ARY3 are activated, it is selectively set to a high level at a predetermined timing.

As a result, the MOSFETs P3 to P5 are
Upon receiving the low level of the corresponding internal control signals PC0 to PC3, the memory cells ARY0 to ARY0 are selectively turned on.
The non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to B127 * of ARY3 are equalized to a high level like the power supply voltage of the circuit. Also, MOSFETs P1 and P
2 indicates the selected sub-word lines SW0 to SW511 when the corresponding MOSFETs P3 to P5 are turned off.
It acts as an auxiliary amplifier circuit in order to expand the level difference of the minute read signals output from the 128 memory cells MC coupled to the corresponding complementary bit lines B0 * to B127 *.

On the other hand, the Y switches YS0 to YS3 are connected to the complementary bit lines B0 * to B of the memory arrays ARY0 to ARY3.
Each of 128 sets of N-channel type and P-channel type switch MOSFETs provided corresponding to 127 * is included. Of these, N-channel type switch MOSF
The other of the ETs is sequentially and commonly coupled to eight sets of complementary common data lines for writing (not shown) every eight pairs. Further, the gates thereof are sequentially commonly connected in pairs of eight, and corresponding write bit line selection signals are commonly supplied from the Y address decoders YD0 to YD3. Similarly, the other of the P-channel type switch MOSFETs is not shown in FIG.
Every eight pairs of pairs of complementary common data lines for reading are sequentially commonly coupled. Further, the gates thereof are sequentially commonly connected in pairs of eight, and corresponding read bit line selection signals are commonly supplied from the Y address decoders YD0 to YD3.

As a result, the N-channel type switch MOSFETs forming the Y switches YS0 to YS3 are selectively turned on by 8 pairs by setting the corresponding write bit line selection signal to the high level, and the corresponding switches are turned on. The eight complementary bit lines and the write complementary common data line designated in the memory arrays ARY0 to ARY3 are selectively connected. Similarly, Y switches YS0 to YS3
The P-channel switch MOSFET that constitutes
When the corresponding read bit line selection signal is set to the high level, eight pairs are selectively turned on, and the eight complementary bit lines and the read complementary common data line designated by the corresponding memory arrays ARY0 to ARY3 are designated. And are selectively connected.

The Y address decoders YD0 to YD3 include
The 4-bit internal address signals Y0 to Y3 are commonly supplied from the Y address buffer YB, the internal control signal CS2 is commonly supplied from the timing generation circuit TG, and the corresponding mat selection signal M is supplied from the mat selection circuit MS.
0 to M3 are supplied respectively. The Y address buffer YB is supplied with Y address signals AY0 to AY3 via address input terminals AY0 to AY3. on the other hand,
The 2-bit internal address signals Z0 to Z1 are supplied from the Z address buffer ZB to the mat selection circuit MS, and the internal control signals CS1B and C from the timing generation circuit TG.
S2B is supplied. Further, Z address signals AZ0 to AZ1 are supplied to the Z address buffer ZB via address input terminals AZ0 to AZ1.

The Z address buffer ZB has an address input terminal A when the static RAM is in the selected state.
Z address signal AZ0 supplied via Z0 to AZ1
.About.AZ1 are fetched and held, and internal address signals Z0 to Z1 are formed based on these Z address signals and supplied to the mat selection circuit MS. Further, the mat selection circuit MS is selectively operated in response to the low level of the internal control signal CS1B, and the Z address buffer ZB
The internal address signals Z0 to Z1 supplied from the above are decoded. Then, the corresponding mat selection signals M0 to M3 are alternatively set to the high level in synchronism with the low level of the internal control signal CS1B, and the corresponding selection drive signal WD0 is triggered by the low level change of the internal control signal CS2B. ~ WD3 is alternatively set to a high level at a predetermined timing.

On the other hand, the Y address buffer YB takes in and holds the Y address signals AY0 to AY3 supplied through the address input terminals AY0 to AY3 when the static RAM is in the selected state, and at the same time, these Y addresses are stored. Internal address signals Y0 to Y3 based on the address signal
Are formed and supplied to the Y address decoders YD0 to YD3. The Y address decoders YD0 to YD3 are selectively activated by the internal control signal CS2 being high level and the corresponding mat selection signals M0 to M3 being high level, and supplied from the Y address buffer YB. The internal address signals Y0 to Y3 are decoded to selectively set the write or read bit line selection signal to a high level under a predetermined condition.

The write complementary common data lines to which the designated eight sets of complementary bit lines of the memory arrays ARY0 to ARY3 are selectively connected are write amplifiers WA0 to WA.
The output terminals of the corresponding unit write amplifiers of A3 are respectively coupled. Further, the read complementary common data line to which the designated eight sets of complementary bit lines of the memory arrays ARY0 to ARY3 are selectively connected is the sense amplifier SA.
0 to SA3 are respectively coupled to the input terminals of the corresponding unit sense amplifiers.

Each of the write amplifiers WA0 to WA3 includes eight unit write amplifiers provided corresponding to the write complementary common data line. Input terminals of these unit write amplifiers correspond to corresponding data input / output buses DB0 * to D0.
B7 *, the output terminal of which is coupled to the corresponding write complementary common data line as described above. On the other hand, the sense amplifiers SA0 to SA3 respectively include eight unit sense amplifiers provided corresponding to the read complementary common data lines. As described above, the input terminals of these unit sense amplifiers are coupled to the corresponding read complementary common data lines, and the output terminals thereof are coupled to the corresponding data input / output buses DB0 * to DB7 *. Data input / output buses DB0 * to DB7 * are coupled to the output terminals of the corresponding unit data input buffers of data input buffer IB and the input terminals of the corresponding unit data output buffers of data output buffer OB.

The unit write amplifiers forming the write amplifiers WA0 to WA3 are commonly supplied with an internal control signal WP (not shown) from the timing generation circuit TG, and the corresponding mat selection signal M from the mat selection circuit MS.
0 to M3 are commonly supplied. Further, the unit sense amplifiers forming the sense amplifiers SA0 to SA3 include
An internal control signal RP (not shown) is commonly supplied from the timing generation circuit TG, and the mat selection circuit MS is also provided.
To the corresponding mat selection signals M0 to M3 are commonly supplied. The output control signal DOC is supplied from the timing generation circuit TG to the data output buffer OB.

The data input buffer IB fetches the write data supplied via the corresponding data input / output terminals IO0 to IO7 when the static RAM is selected in the write mode, and the data input / output bus DB0.
It is transmitted to the corresponding unit write amplifier of the write amplifiers WA0 to WA3 via * to DB7 *. At this time, each of the unit write amplifiers of the write amplifiers WA0 to WA3 is selectively activated by setting the internal control signal WP to the high level and the corresponding mat selection signals M0 to M3 to the high level. The write data transmitted from the input buffer IB via the corresponding data input / output buses DB0 * to DB7 * is converted into a predetermined complementary write signal, and then the corresponding memory array ARY0 to ARY3 via the corresponding write complementary common data line. Write to the selected eight memory cells.

On the other hand, in the unit sense amplifiers forming the sense amplifiers SA0 to SA3, when the static RAM is selected in the read mode, the internal control signal RP is at the high level and the corresponding mat selection signals M0 to M are generated.
When 3 is set to a high level, the read signal output from the selected eight memory cells of the memory arrays ARY0 to ARY3 via the corresponding complementary complementary common data lines is amplified. After that, the data is transmitted to the corresponding unit data output buffer of the data output buffer OB via the corresponding data input / output buses DB0 * to DB7 *. At this time, each unit data output buffer of the data output buffer OB is selectively activated by receiving the high level of the output control signal DOC, and the sense amplifier SA
Read signals output from the corresponding unit sense amplifiers of 0 to SA3 via the data input / output buses DB0 * to DB7 * are sent to the outside of the static RAM from the corresponding data input / output terminals IO0 to IO7.

The timing generation circuit TG has a chip selection signal CSB, a write enable signal WEB and an output enable signal OEB which are externally supplied as a start control signal.
Based on the above, the various internal control signals or output control signals are selectively formed and supplied to each part of the static RAM.

FIG. 5 shows a substrate layout view of an embodiment of the static RAM of FIG. 1, and FIG. 6 shows a partial plan layout view of an embodiment of the memory array portion. There is. Based on these figures, the substrate arrangement of the static RAM of this embodiment, the plane arrangement of the memory array portion, and the features thereof will be described. Note that in FIG. 6, the N-type diffusion layer is shown by a dotted line. Further, the thin solid lines indicate the first and second polysilicon layers, and the thick solid lines indicate the first and second metal wiring layers, that is, the aluminum wiring layers, respectively. Further, in the following description, the vertical and horizontal directions on the surface of the semiconductor substrate will be expressed with the positional relationship shown in FIGS.

In FIG. 5, the static RAM is
Although not particularly limited, the four memory arrays ARY0 to ARY3 arranged along the upper side of the semiconductor substrate SUB are the basic constituent elements. Below these memory arrays, corresponding Y switches YS0 to YS3, Y address decoders YD0 to YD3, write amplifiers WA0 to WA3 and sense amplifiers SA0 to SA3 are arranged, and an X address decoder XD is arranged on the left side thereof. Will be placed. The X address buffer X is provided to the left of the X address decoder XD.
B, timing generation circuit TG and Z address buffer Z
B is arranged, and further below that, a data input buffer IB, a data output buffer OB, and a mat selection circuit MS.
And a Y address buffer YB are arranged.

In this embodiment, the memory array ARY
A corresponding sub-word line drive circuit SD0 is arranged on the right side of 0, and a corresponding sub-word line drive circuit SD1 is arranged on the left side of the memory array ARY1. Similarly, a corresponding sub word line drive circuit SD2 is arranged on the right side of the memory array ARY2, and a corresponding sub word line drive circuit SD3 is arranged on the left side of the memory array ARY3. That is, in the static RAM of this embodiment, the sub-word line drive circuits SD0 to SD3 are arranged adjacent to each other as a pair of memory arrays ARY0 and A.
It is arranged inside RY1 or ARY2 and ARY3, and is relatively higher than the conventional static RAM arranged in the central portion of the corresponding memory arrays ARY0 to ARY3 in which these sub-word line driving circuits are arranged. It is possible to reduce the number of junctions between the memory array portion that is easily integrated and the logic portion that is relatively difficult to be highly integrated to one half, and thereby improve the layout efficiency of the static RAM.

By the way, the memory arrays ARY0 to ARY
N-channel drive M that constitutes memory cell MC of 3
As illustrated in FIG. 6, the OSFET N1 has the right half of the N-type diffusion layer ND3 as its source and drain regions,
The drive MOSFET N2 uses the N-type diffusion layer ND2 as its source and drain regions. The N-channel type selection MOSFET N3 has the left half of the N-type diffusion layer ND3 as its source and drain regions, and the selection MOSFET
N4 uses the N-type diffusion layer ND1 as its source and drain regions. On the upper layer of the diffusion layer ND3, a first-layer polysilicon layer PS12 to be the gate of the drive MOSFET N1 is formed across a predetermined insulating film, and a selective MO layer is formed.
A first-layer polysilicon layer PS11 to be the gate of the SFET N3, that is, the sub-word line SW0 and the like is formed. The polysilicon layer PS11 becomes the gate of the selection MOSFET N4 in the upper layer of the N-type diffusion layer ND1. Similarly, on the upper layer of the N-type diffusion layer ND2, a first-layer polysilicon layer PS12 to be the gate of the drive MOSFET N2 is formed with a predetermined insulating film interposed therebetween.

The lower right portion of the N-type diffusion layer ND3 serving as the source of the drive MOSFET N1 is coupled to the first-layer aluminum wiring layer AL13, that is, the ground potential VSS of the circuit, via the contact CON7. Also, the drive MOSFET N1
Of the N-type diffusion layer ND3 that is the drain of the selection MOSFET N3, that is, the center of the polysilicon layer PS12, that is, the drive MOSFET
It is coupled to the gate of TN2 and to the power supply voltage VCC of the circuit through the second polysilicon layer PS21. This polysilicon layer PS21 becomes a high resistance load R1 on the upper layer of the polysilicon layer PS12. Further, the upper left portion of the N-type diffusion layer ND3 that serves as the drain of the selection MOSFET N3 is coupled to the first-layer aluminum wiring layer AL15 via the contact CON1 and then to the second-layer aluminum wiring layer via the through hole TH1. AL
21, that is, the non-inverted bit line B0T or the like.

On the other hand, the lower left part of the N-type diffusion layer ND2 serving as the source of the drive MOSFET N2 is coupled to the aluminum wiring layer AL13 of the first layer, that is, the ground potential VSS of the circuit via the contact CON6. In addition, drive MOSFE
The right side of the N-type diffusion layer ND2 serving as the drain of TN2 is coupled to the polysilicon layer PS13, that is, the gate of the drive MOSFET N1 via the contact CON5, and further to the source of the selection MOSFET N4 via the polysilicon layer PS13 and the contact CON4. N-type diffusion layer N
It is coupled below D1. The contact CO is provided above the N-type diffusion layer ND1 serving as the drain of the selection MOSFET N4.
After being coupled to the first-layer aluminum wiring layer AL16 via N2, it is coupled to the second-layer aluminum wiring layer AL22, that is, the inverted bit line B0T, etc., through the through hole TH2. In addition, N which is the source of the selection MOSFET
Below the type diffusion layer ND1, the contact CON
4 to the polysilicon layer PS21, which is connected to the polysilicon layer PS21.
A high resistance load R2 is provided in the upper layer.

In this embodiment, the word shunt line SSW0 is further provided on the N-type diffusion layers ND2 and ND3.
And the like, and a first-layer aluminum wiring layer AL12, which becomes the main word line MW0B and the like, is formed. Among these, the aluminum wiring layer AL11 to be the word shunt line SSW0 and the like is coupled to the polysilicon layer PS11 to be the sub word line SW0 and the like via a predetermined through hole on the left side (not shown) and to the right two (not shown). After being coupled to the polysilicon layer PS11 to be the sub-word line SW0 and the like through a predetermined through hole at a portion, it is coupled to the corresponding unit sub-word line drive circuit USD0 and the like of the sub-word line drive circuit SD0. As a result, the polysilicon layer PS11 to be the sub-word line SW0 and the like has the word shunt line SS with a small distributed resistance value.
It is lined with W0 and the like, which speeds up the selection operation of the sub word line SW0 and the like.

In this embodiment, the selection MOSFET
First polysilicon layer P to be the gates of N3 and N4
S11 is formed in a single pattern by a single layer of polysilicon only. As a result, the manufacturing process for the memory array can be simplified, the shrinkage of the wiring layer in the wafer process can be prevented, the damage to the gate oxide film can be prevented, and the reliability of the static RAM can be improved.

The operational effects obtained from the above embodiments are as follows. That is, (1) In a static RAM or the like that adopts the divided word line system, an X address decoder is provided commonly to a plurality of divided memory arrays, and its output signal, that is, the word line decoded signal is made up of a metal wiring layer and corresponds. While transmitting to the plurality of sub-word line drive circuits via the main word line arranged in the upper layer of the memory cell, the sub-word line constituting each memory array is formed as a gate of the selection MOSFET of the memory cell by a single layer of polysilicon. By forming the word shunt lines formed in one pattern and corresponding to each sub-word line in the upper layer of the corresponding memory cell which is made of a metal wiring layer and is coupled to the corresponding sub-word line at a plurality of positions, the wafer process can be performed. A memory array and X address decoder are required while preventing shrinkage of the wiring layer. The effect is that the layout area can be reduced.

(2) According to the above item (1), the distributed resistance of the sub word lines forming each memory array can be reduced, and the word line selecting operation can be speeded up. (3) In the above items (1) and (2), the sub word line drive circuits provided corresponding to the respective memory arrays are arranged inside a pair of memory arrays which are arranged adjacent to each other. As a result, it is possible to reduce the number of junctions between the memory array portion that is easily highly integrated and the logic portion that is relatively hard to be highly integrated, and improve the layout efficiency in the memory array portion and the peripheral portion. (4) According to the above items (1) to (3), the chip area is reduced to reduce the cost and the access time is reduced without lowering the reliability of the static RAM adopting the divided word line system. The effect of speeding up is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory array can be divided into an arbitrary number in the extending direction of the word lines, and can also be divided in the extending direction of the bit lines. In addition, the memory array ARY
The storage capacities of 0 to ARY3 and the static RAM as a whole can be arbitrarily set, and the bit configuration thereof is also arbitrary. The Z address signals AZ0 to AZ1 may be regarded as a part of the Y address signal, and the number of bits thereof also changes according to the number of divisions of the memory array. Furthermore, the static RAM can have any block configuration, and various embodiments can be adopted for the combination of the start control signal and the internal control signal.

In FIGS. 2 and 3, the memory array AR
The numbers of sub-word lines and complementary bit lines forming Y0 to ARY3 can be set arbitrarily. Also, the sub word line SW
0 to SW511 and corresponding word shunt lines SSW0 to
The number of coupling portions with the SSW 511 can be provided in any position and in any number. In FIG. 4, the inverter for obtaining the inversion signal of the internal address signals X0 to X8 is X
You may provide in common to the address buffer XB. further,
The specific configurations of the memory arrays ARY0 to ARY3 and the X address decoder XD are not restricted by these embodiments, and the polarity and absolute value of the power supply voltage, the logic level of the main word line and the internal control signal, and the conductivity type of the MOSFET. Etc. may take various embodiments.

In FIG. 5, the substrate layout of the static RAM is not restricted by this embodiment. In FIG. 6, when three or more metal wiring layers are prepared for the static RAM, for example, the word shunt line SSW0 and the main word line MW0B may be formed of different metal wiring layers. The material of each wiring layer can be arbitrarily selected, and its specific arrangement, shape, etc. can adopt various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the static RAM which is the field of application which is the background of the invention has been described.
For example, BiCMOS is not limited to this.
The present invention can be applied to various memory integrated circuit devices such as (bipolar CMOS) static RAM and logic integrated circuit devices including such memory integrated circuit devices. This invention
The present invention can be widely applied to at least a semiconductor memory device adopting the divided word line system and devices and systems including such a semiconductor memory device.

[0056]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like adopting the divided word line system, an X address decoder is provided commonly to a plurality of divided memory arrays, and its output signal, that is, a word line decoded signal, is stored in a corresponding memory cell formed of a metal wiring layer. The data is transmitted to the plurality of sub word line drive circuits via the main word line arranged in the upper layer. In addition, the sub-word lines forming each memory array are formed in a single pattern as the gates of the selection MOSFETs of the memory cells by a single layer of polysilicon, and each sub-word line is formed of a metal wiring layer and has a corresponding memory cell. A word shunt line is provided in the upper layer and is coupled to the corresponding sub word line at a plurality of positions. Further, the sub-word line drive circuit provided corresponding to each memory array is arranged inside a pair of memory arrays arranged adjacent to each other. As a result, it is possible to reduce the required layout area of the memory array and the X address decoder while preventing the contraction of the wiring layer in the wafer process, reduce the distributed resistance of the sub-word lines forming each memory array, and select the word line. Can be speeded up. As a result, the static type RA adopting the divided word line system
It is possible to reduce the chip area, reduce the cost, and speed up the access time without reducing the reliability of M and the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

2 is a circuit diagram showing an embodiment of an X address decoder included in the static RAM of FIG.

3 is a partial circuit diagram showing an embodiment of a memory array included in the static RAM of FIG.

FIG. 4 is a connection diagram showing an embodiment of the memory array of FIG.

5 is a board layout diagram showing an embodiment of the static RAM of FIG. 1. FIG.

FIG. 6 is a partial plan view showing an embodiment of a memory array section of the static RAM shown in FIG.

FIG. 7 is a connection diagram showing an example of a conventional static RAM memory array.

FIG. 8 is a connection diagram showing another example of a conventional static RAM memory array.

[Explanation of symbols]

ARY0 to ARY3 ... Memory array, SD0 to SD
3 ... Sub word line drive circuit, XD ... X address decoder, XB ... X address buffer, YS0-Y
S3 ... Y switch, YD0-YD3 ... Y address decoder, YB ... Y address buffer, ZB ...
・ Z address buffer, MS ... Mat selection circuit, W
A0-WA3 ... Write amplifier, SA0-SA3 ...
・ Sense amplifier, IB ... Data input buffer, OB
... Data output buffer, TG ... Timing generation circuit. MC: Memory cell, SW0 to SW511 ...
Sub word line, SSW0 to SSW511 ... Word shunt line, B0 * to B127 * ... Complementary bit line, BPC0 to BPC127 ... Bit line precharge circuit, USD0 to USD511 ... Unit sub word line drive circuit . MW0B to MW511B ... Main word line, UMD0 to UMD511 ... Main word line drive circuit, NA00 to NA07, NA10 to NA17, N
A20 to NA27 ... NAND gate. P
1-P9 ... P-channel MOSFETs, N1-N9
... N-channel MOSFET, V1 to V2 ... Inverter, R1 to R2 ... High resistance load. SUB ...
Semiconductor substrate. ND1 to ND3 ... N type diffusion layer, PS1
1-PS13 ... First-layer polysilicon layer, PS21
..Second polysilicon layers, AL11 to AL16 ...
First layer aluminum wiring layer, AL21 to AL22 ...
Second layer aluminum wiring layer, CON1 to CON5 ...
Contact, TH1-TH2 ... through hole, VC
C ... Power supply voltage of the circuit, VSS ... Ground potential of the circuit. ARY0L, ARY0R ... Memory array, W0
L to W511L, W0R to W511R ... Word line,
SW0L to SW511L, SW0R to SW511R ...
-Sub word line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical indication location H01L 27/10 471 7210-4M (72) Inventor Satoshi Kawabata 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture (72) Inventor Yoshiaki Umekawa, Nakajima, Nanae-cho, Kameda-gun, Hokkaido 145 Nakajima, Hitachi North Sea Semiconductor Co., Ltd. (72) Yasuhiko Sugimura, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Hitachi Hokai Semiconductor Within

Claims (3)

[Claims] 1. A static type memory cell arranged in a lattice, a sub-word line formed in a single pattern as a gate of a selection MOSFET of a predetermined number of the static type memory cells arranged in a corresponding row, and A plurality of memory arrays, each of which includes a word shunt line provided corresponding to the sub-word line and coupled to the corresponding sub-word line at a plurality of locations, and arranged in series in the extension direction of the word line, and the memory array. A plurality of sub-word line driving circuits each including a plurality of unit sub-word line driving circuits which are provided to receive at least the effective level of a corresponding word line decode signal and selectively set the corresponding word shunt line to a selection level; Main word line for transmitting the above word line decode signal corresponding to the sub word line drive circuit of And a word line and a main word line are arranged in an upper layer of the corresponding static memory cell of the plurality of memory arrays. 2. The semiconductor memory according to claim 1, wherein the sub-word line is made of a polysilicon single layer, and the word shunt line and the main word line are made of a metal wiring layer. apparatus. 3. The semiconductor memory device according to claim 1, wherein the sub-word line drive circuit is arranged inside a pair of the memory arrays arranged adjacent to each other.