CN103460373A - Semiconductor storage device - Google Patents

Semiconductor storage device Download PDF

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Publication number
CN103460373A
CN103460373A CN2012800091090A CN201280009109A CN103460373A CN 103460373 A CN103460373 A CN 103460373A CN 2012800091090 A CN2012800091090 A CN 2012800091090A CN 201280009109 A CN201280009109 A CN 201280009109A CN 103460373 A CN103460373 A CN 103460373A
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CN
China
Prior art keywords
aforementioned
diffusion layer
type
transistor
access transistor
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Pending
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CN2012800091090A
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Chinese (zh)
Inventor
舛冈富士雄
新井绅太郎
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

The present invention provides a loadless 4T-SRAM configured from a vertical transistor SGT, the loadless 4T-SRAM having a small SRAM cell area. A static-type memory cell is configured by four MOS transistors, wherein the MOS transistors are SGTs which are formed on a bulk substrate and of which the drain, gate, and source are arranged in a perpendicular direction; the gate of an access transistor functioning as a wide line is shared by multiple cells that are adjacent to one another in the horizontal direction; and one contact to the wide line is formed per multiple cells. As a consequence, it is possible to provide a CMOS-type loadless 4T-SRAM having an extremely small memory cell area.

Description

Semiconductor storage unit
Technical field
The present invention relates to a kind of semiconductor storage unit, relate in particular to the semiconductor storage unit formed by SRAM (Static Random Access Memory, static RAM).
Background technology
In order to realize highly integrated, the high performance of semiconductor device, a kind of SGT (Surrounding Gate Transistor that belongs to vertical gate transistor (gate transistor) has been proposed, the all around gate transistor) scheme, this SGT forms columnar semiconductor on the surface of Semiconductor substrate, and has and form the grid that surrounds columnar semiconductor layers (for example patent documentation 1: Japanese kokai publication hei 2-188966 communique) at the sidewall of this columnar semiconductor.Therefore because in SGT being is disposed at vertical direction by drain electrode (drain), grid, source electrode (source), compared to plane (planar) transistor npn npn in the past, footprint area significantly can be dwindled.
Use SGT and while forming LSI (large scale integrated circuit), must use the cache (cache) that is used as these LSI with the SRAM that combination was formed of SGT to use memory.In recent years, because the demand of the high capacity of the SRAM for being equipped on LSI is very strong, therefore be necessary also to realize thering is the SRAM than junior unit (cell) area when using SGT.
Patent documentation 2 (TOHKEMY 2011-61110 communique) shows that 4 SGT of use are formed at the non-loaded 4T-SRAM on matrix (bulk) substrate.The equivalent circuit diagram of Fig. 1 shows non-loaded (Loadless) 4T-SRAM.In addition, Figure 20 shows the plane graph of the non-loaded 4T-SRAM of patent documentation 2, and Figure 21 shows the profile of the non-loaded 4T-SRAM of patent documentation 2.
Below with the equivalent electric circuit of the non-loaded 4T-SRAM shown in Fig. 1, show the operating principle of non-loaded 4T-SRAM.Non-loaded 4T-SRAM is by being formed for 2 access transistors in order to access memory (access transistor) of PMOS and 4 transistors altogether in order to 2 driver transistors (driver transistor) of driving memory for NMOS.
Below explanation stores data, and the maintenance action of data when memory node Qb1 stores the data of " H " of " L " at memory node (node) Qa1, as an example of the action of the memory cell of Fig. 1.During data keep, word (word) line WL1, position (bit) line BL1 and BLB1 all drive the current potential into " H ".It is than the shutoff leakage current of driver transistor 10 times to 1000 times left and right greatly for example also that (off leak) current settings is leaked in the shutoff of access transistor (Qp11, Qp21).Therefore, " H " level (level) of memory node Qb1 is to be circulated to memory node Qb1 via access transistor Qp21 from bit line BLB1 by the shutoff leakage current to keep.On the other hand, " L " level of memory node Qa1 stably keeps by driver transistor Qn11.
Figure 20 shows layout (layout) figure of SRAM memory cell of the embodiment 1 of patent documentation 2.In sram cell array (array), repeated configuration has the unit cell shown in Figure 20 (unit cell) UC.Figure 21 (a) is the profile construction of line of cut (cut line) A-A ', the B-B ', C-C ' and the D-D ' that show respectively the layout of Figure 20 to Figure 21 (d).
At first, the layout of sram cell of the embodiment 1 of patent documentation 2 is described with Figure 20 and Figure 21.Form the n trap of promising the 1st trap (well) 601a in the sram cell array of substrate, and the diffusion layer on substrate separates by element separating layer 602.By the diffusion layer on substrate and the 1st memory node Qa6 formed is by 1p+ diffusion layer 603a and 1n+ diffusion layer 604a and form, and connect by the 1st silicide layer 613a that is formed at substrate surface.Similarly, the 2nd memory node Qb6 formed by the diffusion layer on substrate forms by 2p+ diffusion layer 603b and 2n+ diffusion layer 604b, and connects by the 2nd silicide layer 613b that is formed at substrate surface.For suppress from have be the n+ diffusion layer of n trap same conductivity of the 1st trap 601a towards the leakage of substrate, form the diffusion layer (the 1st Leakage prevention diffusion layer 601b or the 2nd Leakage prevention diffusion layer 601c) with conductivity type different from the 1st trap on the top of the 1st trap.The the 1st and the 2nd Leakage prevention diffusion layer is to separate according to the diffusion layer on each substrate by element separating layer 102.
Qp16 and Qp26 are the access transistor in order to access memory unit that belongs to PMOS, Qn16 and Qn26 be belong to NMOS in order to drive the driver transistor of memory cell.
1 unit cell UC possesses the transistor that is arranged in 2 row (row), 2 row (column) on substrate.At the 1st row, upper in the 1st memory node Qa6, be arranged with respectively access transistor Qp16 and driver transistor Qn16 from the upside of figure.In addition, at the 2nd row, upper in the 2nd memory node Qb6, be arranged with respectively access transistor Qp26 and driver transistor Qn26 from the upside of figure.The sram cell array of the present embodiment is to have 4 transistorized unit cell UC continuous arrangements always to form at the upper and lower of figure by this kind possessed.
Contact (contact) 610a be formed on the 1st memory node Qa6 connects distribution Na6 and is connected with the contact 611b being formed on the gate wirings of extending from the gate electrode of driver transistor Qn26 by node.In addition, the contact 610b be formed on the 2nd memory node Qb6 connects distribution Nb6 and is connected with the contact 611a being formed on the gate wirings of extending from the gate electrode of driver transistor Qn16 by node.The contact 606a that is formed at access transistor Qp16 top is connected in bit line BL6, and the contact 606b that is formed at access transistor Qp26 top is connected in bit line BLB6.The common contact 607 be formed on the gate wirings of extending from the gate electrode of access transistor Qp16 and access transistor Qp26 is connected in word line WL6.The contact (608a, 608b) that is formed at driver transistor (Qn16, Qn26) top is the wiring layer Vss6 be connected in as earthing potential.
Next, the structure of the sram cell of patent documentation 2 is described with the profile of Figure 21.As shown in Figure 21 (a), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap 601a, and by the diffusion layer on element separating layer 602 separate substrate.In the 1st memory node Qa6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 1p+ drain diffusion layer 603a, and in the 2nd memory node Qb6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 2p+ drain diffusion layer 603b.In addition, the 1st, 2p+ drain diffusion layer (603a, 603b) is upper, is formed with respectively the 1st, the 2nd silicide (silicide) layer (613a, 613b).Be formed with the column silicon layer 621a that forms access transistor Qp16 on p+ drain diffusion layer 603a, and be formed with the column silicon layer 621b that forms access transistor Qp26 on p+ drain diffusion layer 603b.
Be formed with gate insulating film 617 and gate electrode 618 around each column silicon layer.On column silicon layer top, be formed with p+ drain diffusion layer 616 by implanted dopant etc., be formed with silicide layer 615 on source diffusion layer surface.The contact 606a be formed on access transistor Qp16 is connected in bit line BL6, the contact 606b be formed on access transistor Qp26 is connected in bit line BLB6, and the contact 607 be formed on the gate wirings 618a extended from the grid of access transistor Qp16 and Qp26 is connected in word line WL6.
As shown in Figure 21 (b), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap 601a, and by the diffusion layer on element separating layer 602 separate substrate.In the 1st memory node Qa6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 1n+ drain diffusion layer 604a, and in the 2nd memory node Qb6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 2n+ drain diffusion layer 604b.In addition, the 1st, on the 2n+ drain diffusion layer, be formed with respectively the 1st, the 2nd silicide layer (613a, 613b).The contact 611a be formed on the 1st drain diffusion layer 604a is formed near the going up in boundary of 1p+ drain diffusion layer 603a and 1n+ drain diffusion layer 604a, and connects distribution Nb6 and be connected in the contact 611a gate wirings 618b that is formed at extended from the gate electrode of driver transistor Qn16 via memory node.
In order to suppress from thering is the leakage towards substrate with the 1n+ diffusion layer 604a of the 1st trap same conductivity, in the bottom of 1n+ diffusion layer and be that the 1st Leakage prevention diffusion layer 601b with conductivity type different from the 1st trap is formed at the top of the 1st trap, and in order to suppress from thering is the leakage towards substrate with the 2n+ diffusion layer 604b of the 1st trap same conductivity, in the bottom of 2n+ diffusion layer and be that the 2nd Leakage prevention diffusion layer 601c with conductivity type different from the 1st trap is formed at the top of the 1st trap.
As shown in Figure 21 (c), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap, and by the diffusion layer on element separating layer 602 separate substrate.In the 1st memory node Qa6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 1n+ drain diffusion layer 604a, and in the 2nd memory node Qb6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 2n+ drain diffusion layer 604b.In addition, the 1st, 2n+ drain diffusion layer (604a, 604b) surface, be formed with respectively the 1st, the 2nd silicide layer (613a, 613b).In order to suppress from thering is the leakage towards substrate with the 1n+ diffusion layer 604a of the 1st trap same conductivity, in the bottom of 1n+ diffusion layer and be that the 1st Leakage prevention diffusion layer 601b with conductivity type different from the 1st trap is formed at the top of the 1st trap, and in order to suppress from thering is the leakage towards substrate with the 2n+ diffusion layer 604b of the 1st trap same conductivity, in the bottom of 2n+ diffusion layer and be that the 2nd Leakage prevention diffusion layer 601c with conductivity type different from the 1st trap is formed at the top of the 1st trap.
Form in order to form the column silicon layer 622a of driver transistor Qn16 at 1n+ drain diffusion layer 604a, and form in order to form the column silicon layer 622b of driver transistor Qn26 at 2n+ drain diffusion layer 604b.Be formed with gate insulating film 617 and gate electrode 618 around each column silicon layer.On column silicon layer top, be formed with n+ source diffusion layer 614 by implanted dopant etc., be formed with silicide layer 615 on source diffusion layer surface.The contact (608a, 608b) be formed on driver transistor (Qn16, Qn26) all is connected in power supply potential distribution Vss6 via wiring layer.
As shown in Figure 21 (d), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap, and by the diffusion layer on element separating layer 602 separate substrate.In the 2nd memory node Qb6 that the diffusion layer on substrate forms, be formed with 2p+ drain diffusion layer 603b and 2n+ drain diffusion layer 604b by implanted dopant etc.Be formed with the 2nd silicide layer 613b on drain diffusion layer, and 2p+ drain diffusion layer 603b directly is connected by the 2nd silicide layer 613b with 2n+ drain diffusion layer 604b.In order to suppress from thering is the leakage towards substrate with the 2n+ diffusion layer 604b of the 1st trap same conductivity, in the bottom of 2n+ diffusion layer and be that the 2nd Leakage prevention diffusion layer with conductivity type different from the 1st trap 601a is formed at the top of the 1st trap.
Form the column silicon layer 622b that forms access transistor Qp26 on 2p+ drain diffusion layer 603b, and form the column silicon layer 622b that forms driver transistor Qn26 on 2n+ drain diffusion layer 604b.Form gate insulating film 617 and gate electrode 618 around each column silicon layer, and form the source diffusion layer on each column silicon layer top by implanted dopant etc., and be formed with silicide layer 615 on source diffusion layer surface.The contact 608b be formed on access transistor Qp26 is connected in bit line BLB6, and the contact 608b be formed on driver transistor Qn26 is connected in earthing potential Vss6.
The gate wirings 618c extended at the gate electrode from driver transistor Qn26 is formed with contact 610b, and contact 610b connects distribution Na6 and is connected in the contact 611a be formed on the 1st drain diffusion layer via memory node.Be formed with contact 611b on 2n+ drain diffusion layer 604b, and connect distribution Nb6 and be connected in the contact 611a be formed on the gate wirings 618b extended from the gate electrode of driver transistor Qn16 via memory node.
[prior art document]
[patent documentation]
Patent documentation 1: Japanese kokai publication hei 2-188966 communique
Patent documentation 2: TOHKEMY 2011-61110 communique
Summary of the invention
[problem that invention institute wish solves]
In the 4T-SRAM unit of Figure 20 and Figure 21, due to the word line contact on the grid be formed between access transistor, at above-below direction, produce idle space (dead space), and can't form less sram cell in efficiency ground.
Because above situation, the non-loaded 4T-SRAM that the objective of the invention is to realize a kind of use SGT more in the past proposed is used the non-loaded 4T-SRAM unit of the SGT that cellar area is less.
[solving the means of problem]
The invention provides a kind of semiconductor storage unit, it possesses a plurality of static type memory cells that are arranged with 4 MOS transistor on substrate,
Each person performance of aforementioned 4 MOS transistor as the 1st and the access transistor of 2PMOS, with the 1st and the function of the driver transistor of 2NMOS, the 1st and the access transistor of 2PMOS in order to keep memory cell data in order to supply with electric charge and access memory, and the 1st and the driver transistor of 2NMOS for the data of read memory unit in order to drive memory node;
The access transistor of supplying with the 1st and 2PMOS that electric charge and access memory use in order to keep memory cell data is
P type the 1st diffusion layer, the 1st columnar semiconductor layers and P type the 2nd diffusion layer vertically are configured on substrate to stratum, and aforementioned the 1st columnar semiconductor layers be configured in the bottom that is formed at aforementioned the 1st columnar semiconductor layers aforementioned the 1st diffusion layer, and be formed between aforementioned the 2nd diffusion layer on top of aforementioned the 1st columnar semiconductor layers, be formed with the 1st grid in the sidewall of aforementioned the 1st columnar semiconductor layers;
For the data of read memory unit, drive the 1st and 2NMOS driver transistor of memory node to be
N-type the 3rd diffusion layer, the 2nd columnar semiconductor layers and N-type the 4th diffusion layer vertically are configured on substrate to stratum, and aforementioned the 2nd columnar semiconductor layers be configured in the bottom that is formed at aforementioned the 2nd columnar semiconductor layers aforementioned the 3rd diffusion layer, and be formed between aforementioned the 4th diffusion layer on top of aforementioned the 1st columnar semiconductor layers, be formed with the 2nd grid in the sidewall of aforementioned the 2nd columnar semiconductor layers;
The arrangement that is adjacent to each other of the access transistor of aforementioned 1PMOS and the driver transistor of aforementioned 1NMOS;
The arrangement that is adjacent to each other of the access transistor of aforementioned 2PMOS and the driver transistor of aforementioned 2NMOS;
Be formed with to give in a plurality of memory cells common 1st trap of current potential to this substrate in aforesaid substrate;
Being formed at aforementioned P type the 1st diffusion layer of bottom of access transistor of aforementioned 1PMOS and aforementioned N-type the 3rd diffusion layer of bottom that is formed at the driver transistor of aforementioned 1NMOS is connected to each other;
Aforementioned aforementioned P type the 1st diffusion layer connected to one another and N-type the 3rd diffusion layer performance are as the function of the 1st memory node of the data that are stored in memory cell in order to maintenance;
In order to prevent the leakage between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap, between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap with than the element separating layer also shallow mode form the bottom had with the 1st Leakage prevention diffusion layer of aforementioned the 1st trap opposite conductivity type;
Aforementioned the 1st Leakage prevention diffusion layer directly is connected with aforementioned P type the 1st diffusion layer or N-type the 3rd diffusion layer;
Being formed at aforementioned P type the 1st diffusion layer of bottom of access transistor of aforementioned 2PMOS and aforementioned N-type the 3rd diffusion layer of bottom that is formed at the driver transistor of aforementioned 2NMOS is connected to each other;
Aforementioned aforementioned P type the 1st diffusion layer connected to one another and N-type the 3rd diffusion layer performance are as the function of the 2nd memory node of the data that are stored in memory cell in order to maintenance;
In order to prevent the leakage between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap, between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap with than the element separating layer also shallow mode form the bottom had with the 2nd Leakage prevention diffusion layer of aforementioned the 1st trap opposite conductivity type;
Aforementioned the 2nd Leakage prevention diffusion layer directly is connected with aforementioned P type the 1st diffusion layer or N-type the 3rd diffusion layer;
The aforementioned the 1st and each person's of the driver transistor of aforementioned 2PMOS grid be to be connected to each other by the 1st gate wirings, aforementioned the 1st gate wirings is that the grid by each person of the access transistor of the aforementioned the 1st and aforementioned 2PMOS in a plurality of memory cells more than 2 with adjacency is connected to each other and forms the word line;
To each group of a plurality of memory cells of the adjacency more than 2, form the 1st contact on aforementioned the 1st gate wirings that is the word line.
In the semiconductor storage unit of foregoing invention, can, in being formed with the zone of aforementioned the 1st contact on aforementioned the 1st gate wirings of aforementioned word line, with memory cell, similarly configure pillar (pillar).
In the semiconductor storage unit of foregoing invention, can make:
The 2nd gate wirings of extending from the grid of the driver transistor of aforementioned 1NMOS is to be connected with the diffusion layer of bringing into play as the function of aforementioned the 2nd memory node by the 2nd common contact;
The 3rd gate wirings of extending from the grid of the driver transistor of aforementioned 2NMOS is to be connected with the diffusion layer of bringing into play as the function of aforementioned the 1st memory node by the 3rd common contact.
In the semiconductor storage unit of foregoing invention, can make:
Form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the driver transistor of 2NMOS around length have be equal to or greater than form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the access transistor of 2PMOS around the value of length;
Perhaps
Perhaps form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the driver transistor of 2NMOS around length have be equal to or less than form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the access transistor of 2PMOS around the value of length.
In the semiconductor storage unit of foregoing invention, can make: aforementioned 4 MOS transistor can be arranged in 2 row 2 row on the aforementioned dielectric film; The access transistor of aforementioned 1PMOS is arranged in the 1st row (row) the 1st row (column); The driver transistor of aforementioned 1NMOS is arranged in the 2nd row the 1st row; The access transistor of aforementioned 2PMOS is arranged in the 1st row the 2nd row; The driver transistor of aforementioned 2NMOS is arranged in the 2nd row the 2nd row.
In the semiconductor storage unit of foregoing invention, can make: the access transistor that aforementioned 4 MOS transistor are aforementioned 1PMOS and the access transistor of aforementioned 2PMOS are in abutting connection with arrangement;
In the side's in abutting connection with the direction quadrature of the access transistor of the access transistor with aforementioned 1PMOS and aforementioned 2PMOS direction, the driver transistor of aforementioned 1NMOS and the access transistor of aforementioned 1PMOS are in abutting connection with arrangement;
In the opposing party's in abutting connection with the direction quadrature of the access transistor of the access transistor with aforementioned 1PMOS and aforementioned 2PMOS direction, the driver transistor of aforementioned 2NMOS and the access transistor of aforementioned 2PMOS are in abutting connection with arrangement.
The accompanying drawing explanation
Fig. 1 is for showing the equivalent electric circuit of SRAM of the present invention.
Fig. 2 is the plane graph of the SRAM of demonstration the 1st embodiment of the present invention.
In Fig. 3, (a) reaches the plane graph of the SRAM that is (b) demonstration the 1st embodiment of the present invention.
Fig. 4 (a) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 4 (b) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 4 (c) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 4 (d) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 4 (e) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 5 (a) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 5 (b) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 5 (c) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
Fig. 5 (d) is the profile of the SRAM of demonstration the 1st embodiment of the present invention.
In Fig. 6, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Fig. 7, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Fig. 8, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Fig. 9, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Figure 10, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Figure 11, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Figure 12, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Figure 13, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
In Figure 14, (a) reaches (b) for show the block diagram of manufacture method of the present invention according to sequence of steps.
Figure 15 is the plane graph of the SRAM of demonstration the 2nd embodiment of the present invention.
Figure 16 is the plane graph of the SRAM of demonstration the 3rd embodiment of the present invention.
Figure 17 is the plane graph of the SRAM of demonstration the 4th embodiment of the present invention.
Figure 18 is the plane graph of the SRAM of demonstration the 5th embodiment of the present invention.
In Figure 19, (a) reaches the plane graph of the SRAM that is (b) demonstration the 5th embodiment of the present invention.
Figure 20 is for showing the plane graph of the SRAM that uses SGT in the past.
Figure 21 (a) is for showing the profile of the SRAM that uses SGT in the past.
Figure 21 (b) is for showing the profile of the SRAM that uses SGT in the past.
Figure 21 (c) is for showing the profile of the SRAM that uses SGT in the past.
Figure 21 (d) is for showing the profile of the SRAM that uses SGT in the past.
(main element symbol description)
101a, 210a, 601a: the 1st trap
101b, 201b, 601b: the 1st Leakage prevention diffusion layer
101c, 201c, 601c: the 2nd Leakage prevention diffusion layer
102,202,302,402,502,602: the element separating layer
103,103a, 103b, 203a, 203b, 603a, 603b:p+ diffusion layer
104a, 104b, 204a, 204b, 604a, 604b:n+ diffusion layer
106,106a, 206a, 306a, 406a, 506a, 606a, 106b, 206b, 306b, 406b, 506b, 606b: access transistor column silicon layer upper contact
107: word line contact
108a, 208a, 308a, 408a, 508a, 608a, 108b, 208b, 308b, 408b, 508b, 608b: driver transistor column silicon layer upper contact
110a, 210a, 410a, 610a, 110b, 210b, 410b, 610b: memory node upper contact
111a, 211a, 411a, 611a, 111b, 211b, 411b, 611b: gate wirings upper contact
310a, 310b, 510a, 510b: common contact
107,507: word line contact
113,113a, 113b, 115,213a, 213b, 215,613a, 613b, 615: silicide layer
114,214,614: pillar top N+ diffusion layer
116,216,616: pillar top P+ diffusion layer
117,217,617: gate insulating film
118,218,618: gate electrode
118a, 118b, 218c, 218a, 218b, 118c, 618a, 618b, 618c: gate wirings
118a, 218a, 318a, 418a, 518a: word line
119: the mask layer of silicon oxide layer etc.
120: silicon layer
121,121a, 121b, 221a, 221b, 621a, 621b: access transistor column silicon layer
122a, 122b, 222a, 222b, 622a, 622b: driver transistor column silicon layer
124,224,624:P+ injection zone
125,225,625:N+ injection zone
131: silicon oxide layer
132: the silicon nitride film sidewall
133: resist
134: silicon nitride film
Qa1, Qb1, Qa2, Qb2, Qa3, Qb3, Qa4, Qb4, Qa5, Qb5, Qa6, Qb6: memory node
Qp11, Qp21, Qp12, Qp22, Qp13, Qp23, Qp14, Qp24, Qp15, Qp25, Qp16, Qp26: access transistor
Qn11, Qn21, Qn12, Qn22, Qn13, Qn23, Qn14, Qn24, Qn15, Qn25, Qn16, Qn26: driver transistor
BL1, BL3, BL4, BL5, BL6, BLB1, BLB3, BLB4, BLB5, BLB6: bit line
Vss1, Vss2, Vss3, Vss4, Vss5, Vss6: earthing potential line
Na1, Nb1, Na2, Nb2, Na4, Nb4, Nb6, Nb6 node connect distribution
Embodiment
[embodiment 1]
Fig. 1 shows the equivalent circuit diagram of the memory cell of the non-loaded 4T-SRAM used in the present invention.In Fig. 1, BL1 and BLB1 show bit line, WL1 shows the word line, Vss1 shows earthing potential, Qp11 and Qp21 show to possess to have and for access memory, memory node are charged as to the access transistor of the function of " H ", Qn11 and Qn21 demonstration drive the driver transistor of memory node for the data of read memory unit, Qa1 and Qb1 show in order to store the memory node of data.
Fig. 2 shows the layout of the SRAM memory cell in embodiments of the invention 1.In the SRAM memory cell array, repeated configuration has the unit cell UC shown in Fig. 2.Fig. 4 (a) is the profile construction of line of cut A-A ', B-B ', C-C ' and D-D ' that shows respectively the layout of Fig. 2 to Fig. 4 (d).
At first the layout of the present embodiment is described with reference to figure 2 and Fig. 4.Form the n trap of promising the 1st trap 101a in the sram cell array of substrate, and the element separating layer 102 that the diffusion layer on substrate forms by the dielectric film by oxide-film etc. and separating.By the diffusion layer on substrate and the 1st memory node Qa1 formed is by 1p+ diffusion layer 103a and 1n+ diffusion layer 104a and form, and connect by the 1st silicide layer 113a that is formed at substrate surface.Similarly, by the diffusion layer on substrate and the 2nd memory node Qb1 formed is by 2p+ diffusion layer 103b and 2n+ diffusion layer 104b and form, and connect by the 2nd silicide layer 113b that is formed at substrate surface.For suppress from have be the n+ diffusion layer of n trap same conductivity of the 1st trap 101a towards the leakage of substrate, the 1st and the bottom of 2n+ diffusion layer and the top of the 1st trap 101a form the 2nd Leakage prevention diffusion layer 101b and the 3rd Leakage prevention diffusion layer 101c had from the different conductivity types of the 1st trap.The the 1st and the 2nd Leakage prevention diffusion layer is to separate according to the diffusion layer on each substrate by element separating layer 102.
Qp11 and Qp21 are the access transistor in order to access memory unit that belongs to PMOS, Qn11 and Qn21 be belong to NMOS in order to drive the driver transistor of memory cell.
In the present embodiment, 1 unit cell UC possesses the transistor that is arranged in 2 row 2 row on substrate is arranged.At the 1st row, upper in the 1st memory node Qa1, be arranged with respectively access transistor Qp11 and driver transistor Qn11 from the upside of figure.In addition, at the 2nd row, upper in the 2nd memory node Qb1, be arranged with respectively access transistor Qp21 and driver transistor Qn21 from the upside of figure.The sram cell array of the present embodiment is to have 4 transistorized unit cell UC continuous arrangements always to form at the upper and lower of figure by this kind possessed.
The contact 110a be formed on the 1st memory node Qa1 connects distribution Na1 and is connected with the contact 111b being formed on the gate wirings of extending from the gate electrode of driver transistor Qn21 by node.In addition, being formed at the contact 110b on the 2nd memory node Qb1, is connect distribution Nb1 and be connected with the contact 111a being formed on the gate wirings of extending from the gate electrode of driver transistor Qn11 by node.The contact 106a that is formed at access transistor Qp11 top is connected in bit line BL1, and the contact 106b that is formed at access transistor Qp21 top is connected in bit line BLB1.The gate wirings 118a extended from the gate electrode of access transistor Qp11 and Qp21 is connected in a plurality of memory cells in the transverse direction adjacency as the word line.The contact (108a, 108b) that is formed at driver transistor (Qn11, Qn21) top is connected in the wiring layer Vss1 into earthing potential.
In addition, the distribution of bit line and the distribution of earthing potential, for the distribution with other memory cell is shared, preferably, connect the more upper layer of distribution at the node than being the distribution in each memory cell and connect.
In addition, an example as the formation of above-mentioned hierarchy type distribution, can realize that node connects distribution (Na1), node connects distribution (Nb1), reaches the formation of the distribution Vss1 of earthing potential at the layer distribution more the next than bit line (BL1, BLB1), so that each distribution can not contact with the contact that should not contact.
Fig. 2 shows n+ injection zone 125 and p+ injection zone 124.In the sram cell array region of the present embodiment, the pattern that forms n+ injection zone 125 and p+ injection zone 124 is to form by simple line and space.Therefore, the impact of size offset or contraposition skew is less, and near the nargin (margin) of the size boundary of n+ injection zone and p+ injection zone can be suppressed to minimum, with on graphic, the length (length of the closure of each sram cell) that can effectively dwindle the longitudinal direction of sram cell.
In Fig. 3, (a) shows the plane graph of the part of the SRAM memory cell array consisted of a plurality of SRAM memory cells.In Cell array Area (cell array region) in the drawings, dispose a plurality of memory cells at transverse direction, and commonization (share) there is word line 118a in being disposed at a plurality of memory cells of transverse direction.The word line is connected in the distribution on upper strata by the contact 107 that is formed at Contact Area (joining zone), and optionally with wiring layer, carrys out substrate.Therefore, different with the sram cell of patent documentation 2, because need not form the contact for the word line at unit, therefore can dwindle the sram cell area.
By connecting a plurality of unit in word line 118a, distance word line contact 107 than the unit in distally in, likely because of the delay of the signal of word line, cause reading or the problem of write latency.Therefore, be connected in the element number of word line, can determine in the scope of the problem of the delay of not reading or writing.
In Fig. 3, (b) shows the plane graph of the part of the sram cell array consisted of a plurality of sram cells in other situation.Cell array region in the drawings also disposes a plurality of memory cells in transverse direction equally, and, in being disposed at the memory cell of transverse direction, commonization has word line 118a.Yet, in Fig. 3 (b), even in joining zone, also with cell array region, similarly dispose pillar.So by also pillar being configured with the pattern identical with memory cell area (pattern) at joining zone, even joining zone also can keep with cell array in the systematicness of same struts configuration, therefore the pillar that is adjacent to joining zone can be reduced with the difference of the size of an intercolumniation that is not adjacent to joining zone, and the characteristic that is adjacent to the SGT of joining zone can be suppressed in Min. with the error of the characteristic of the SGT that is not adjacent to joining zone.
During in Fig. 3, (a) reaches (b), narrated the formation of word line and word line contact as an example though used the layout of embodiment 1, but in fact be not limited to the layout of embodiment 1, in the layout of other embodiment, also applicable identical word line and the formation of word line contact.
In the present invention, each the transistorized source electrode and the drain electrode that form SRAM are defined as follows.About driver transistor (Qn11, Qn21), the diffusion layer that is formed on the top of the columnar semiconductor layers that is connected in earthing potential is defined as to the source diffusion layer, and the diffusion layer that will be formed at the bottom of columnar semiconductor layers is defined as drain diffusion layer.About access transistor (Qn11, Qp21), though according to the operate condition difference, be formed at the diffusion layer on top of columnar semiconductor layers and the diffusion layer that is formed at bottom and all can become source electrode or drain electrode, but for convenience's sake, the diffusion layer that is formed at the top of columnar semiconductor layers is defined as to the source diffusion layer, and the diffusion layer that will be formed at the bottom of columnar semiconductor layers is defined as drain diffusion layer.
Next the structure of SRAM of the present invention is described with reference to the profile construction of Fig. 4.As shown in Fig. 4 (a), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap 101a, and the diffusion layer on substrate is by the formed element separating layer 102 of dielectric film by oxide-film etc. and separate.In the 1st memory node Qa6 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 1p+ drain diffusion layer 103a, and in the 2nd memory node Qb1 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 2p+ drain diffusion layer 103b.In addition, the 1st, 2p+ drain diffusion layer (103a, 103b) is upper, is formed with respectively the 1st, the 2nd silicide layer (113a, 113b).Be formed with the column silicon layer 121a that forms access transistor Qp11 on p+ drain diffusion layer 103a, and be formed with the column silicon layer 121b that forms access transistor Qp21 on p+ drain diffusion layer 103b.
Be formed with gate insulating film 117 and gate electrode 118 around each column silicon layer.On column silicon layer top, be formed with p+ source diffusion layer 116 by implanted dopant etc., be formed with silicide layer 115 on source diffusion layer surface.The contact 106a be formed on access transistor Qp11 is connected in bit line BL1, and the contact 106b be formed on access transistor Qp21 is connected in bit line BLB1.The gate wirings 118a extended from the gate electrode of access transistor Qp11 and Qp21 is to be connected in as the word line a plurality of memory cells that are adjacent to transverse direction.
As shown in Fig. 4 (b), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap 101a, and the diffusion layer on substrate is by the formed element separating layer 102 of dielectric film by oxide-film etc. and separate.In the 1st memory node Qa1 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 1n+ drain diffusion layer 104a, and in the 2nd memory node Qb1 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 2n+ drain diffusion layer 104b.In addition, the 1st, on the 2n+ drain diffusion layer, be formed with respectively the 1st, the 2nd silicide layer (113a, 113b).The contact 111a be formed on the 1st drain diffusion layer 104a is formed near the going up in boundary of 1p+ drain diffusion layer 103a and 1n+ drain diffusion layer 104a, and connects distribution Na1 and be connected in the contact 111a gate wirings 118b that is formed at extended from the gate electrode of driver transistor Qn11 via memory node.
In order to suppress from thering is the leakage towards substrate with the 1n+ diffusion layer 104a of the 1st trap same conductivity, in the bottom of 1n+ diffusion layer and be that the 1st Leakage prevention diffusion layer 101b with conductivity type different from the 1st trap is formed at the top of the 1st trap, and in order to suppress from thering is the leakage towards substrate with the 2n+ diffusion layer 104b of the 1st trap same conductivity, in the bottom of 2n+ diffusion layer and be that the 2nd Leakage prevention diffusion layer 101c with conductivity type different from the 1st trap is formed at the top of the 1st trap.The 1st and the bottom of the 2nd Leakage prevention diffusion layer be formed also shallowly than the bottom of element separating layer, and the 1st and the 2nd Leakage prevention diffusion layer is by the element separation layer.
As shown in Fig. 4 (c), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap, and by the diffusion layer on element separating layer 102 separate substrate.In the 1st memory node Qa1 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 1n+ drain diffusion layer 104a, and in the 2nd memory node Qb1 formed at the diffusion layer on substrate, by implanted dopant etc. and be formed with 2n+ drain diffusion layer 104b.In addition, the 1st, 2n+ drain diffusion layer (104a, 104b) surface, be formed with respectively the 1st, the 2nd silicide layer (113a, 113b).In order to suppress from thering is the leakage towards substrate with the 1n+ diffusion layer 104a of the 1st trap same conductivity, in the bottom of 1n+ diffusion layer and be that the 1st Leakage prevention diffusion layer 101b with conductivity type different from the 1st trap is formed at the top of the 1st trap, and in order to suppress from thering is the leakage towards substrate with the 2n+ diffusion layer 104b of the 1st trap same conductivity, in the bottom of 2n+ diffusion layer and be that the 2nd Leakage prevention diffusion layer 101c with conductivity type different from the 1st trap is formed at the top of the 1st trap.The 1st and the bottom of the 2nd Leakage prevention diffusion layer be formed also shallowly than the bottom of element separating layer, and the 1st and the 2nd Leakage prevention diffusion layer is by the element separation layer.
Form in order to form the column silicon layer 122a of driver transistor Qn11 at 1n+ drain diffusion layer 104a, and form in order to form the column silicon layer 122b of driver transistor Qn21 at 2n+ drain diffusion layer 104b.Be formed with gate insulating film 117 and gate electrode 118 around each column silicon layer.On column silicon layer top, be formed with n+ source diffusion layer 114 by implanted dopant etc., be formed with silicide layer 115 on source diffusion layer surface.The contact (108a, 108b) be formed on driver transistor (Qn11, Qn21) all is connected in earthing potential Vss1 via wiring layer.
As shown in Fig. 4 (d), at substrate, being formed with common in the sram cell array is the n trap of the 1st trap, and by the diffusion layer on element separating layer 102 separate substrate.In the 2nd memory node Qb1 that the diffusion layer on substrate forms, be formed with 2p+ drain diffusion layer 103b and 2n+ drain diffusion layer 104b by implanted dopant etc.Be formed with the 2nd silicide layer 113b on drain diffusion layer, and 2p+ drain diffusion layer 103b directly is connected by the 2nd silicide layer 113b with 2n+ drain diffusion layer 104b.In order to suppress from thering is the leakage towards substrate with the 2n+ diffusion layer 104b of the 1st trap same conductivity, in the bottom of 2n+ diffusion layer and be that the 2nd Leakage prevention diffusion layer 101c with conductivity type different from the 1st trap 101a is formed at the top of the 1st trap.In the present embodiment, though be to connect N+ source diffusion layer and P+ source diffusion layer by silicide, when the contact resistance of N+ source diffusion layer and P+ source diffusion interlayer is minimum, do not need to form silicide.In addition, also can, by being connected with P+ source diffusion layer substrate at N+ source diffusion layer with contact, connect N+ source diffusion layer and P+ source diffusion layer to replace with silicide, or connect N+ source diffusion layer and P+ source diffusion layer with other method.
Fig. 4 (e) shows the profile construction of the E-E ' of (a) in Fig. 3.Be formed with the unit in left side and the P+ source diffusion layer 103 unit, that formed by silicon layer on right side on substrate.Be formed with silicide layer 113 on each source diffusion layer.Be formed with to form the column silicon layer 121 of access transistor on each P+ source diffusion layer 103, be the column silicon layer 121 that is formed with to form access transistor on P+ source diffusion layer 103.Be formed with gate insulating film 117 and gate electrode 118 around each column silicon layer.By implanted dopant etc. and be formed with P+ drain diffusion layer region 116, in the drain diffusion layer region surface, be formed with silicide layer 115 on column silicon layer top.The contact 106 be formed on each access transistor is connected in bit line, and the contact 107 be formed on word line 118a is connected in the more low-resistance word line formed by the wiring layer on upper strata.
Form the column silicon layer 122b that forms access transistor Qp21 on 2p+ drain diffusion layer 103b, and form the column silicon layer 122b that forms driver transistor Qn21 on 2n+ drain diffusion layer 104b.Form gate insulating film 117 and gate electrode 118 around each column silicon layer, and form the source diffusion layer on each column silicon layer top by implanted dopant etc., and be formed with silicide layer 115 on source diffusion layer surface.The contact 106b be formed on access transistor Qp21 is connected in bit line BLB1, and the contact 108b be formed on driver transistor Qn21 is connected in power supply potential distribution Vss1.
The gate wirings 118c extended at the gate electrode from driver transistor Qn21 is formed with contact 111b, and contact 111b connects distribution Na1 and is connected in the contact 110a be formed on the 1st drain diffusion layer via memory node.Be formed with contact 110b on 2n+ drain diffusion layer 104b or on 2p+ drain diffusion layer 103b, and connect distribution Nb1 and be connected in the contact 111a be formed at the gate wirings 118b extended from the gate electrode of driver transistor Qn11 via memory node.
As Fig. 5 (a) to as shown in Fig. 5 (d), in the structure that is p trap and the n type diffused layer that forms the 1st Leakage prevention diffusion layer 201b and the 2nd Leakage prevention diffusion layer 201c between p+ diffusion layer and the 1st trap at the 1st trap 201a, also can form sram cell equally.Now, by the bottom at p+ drain diffusion layer 203a and be that the 1st Leakage prevention diffusion layer 201b is formed at the top of the 1st trap, in the bottom of p+ drain diffusion layer 203b and be that the 2nd Leakage prevention diffusion layer 201c is formed at the top of the 1st trap, can suppress the leakage from diffusion layer towards the 1st trap.
One example of the manufacture method in order to form semiconductor device of the present invention is described referring to Fig. 6 to Figure 14.In each figure, (a) display plane figure, (b) show the profile between D-D '.
As shown in Figure 6, by by film forming such as silicon nitride films on substrate, relend the pattern that is formed column silicon layer (121a, 122a, 121b, 122b) by photoetching (lithography), and carry out etching, form whereby silicon nitride film mask (mask) 119 and column silicon layer (121a, 122a, 121b, 122b).Next, by implanted dopant etc., form the n trap of the 1st trap 101a in the sram cell array.
The forming element separating layer 102 as shown in Figure 7.The element separating layer is by first the ditch pattern being carried out to etching, and by CVD (Chemical Vapor Deposition, chemical vapour deposition (CVD)) etc. the dielectric film of oxide-film etc. is imbedded in the ditch pattern, the method that oxide-film unnecessary on substrate is removed in modes such as dry ecthing or wet etchings etc. forms.Whereby, become the pattern of the diffusion layer of the 1st memory node Qa1 and the 2nd memory node Qb1 on substrate.
As shown in Figure 8, by Implantation etc., impurity is directed in to p+ injection zone 124 and n+ injection zone 125 respectively, and forms the drain diffusion layer (103a, 103b, 104a, 104b) of column silicon layer bottom on substrate.For suppress from have be the n+ diffusion layer 104b of n trap same conductivity of the 1st trap 101a towards the leakage of substrate, form the 2nd Leakage prevention diffusion layer 101c.The 2nd Leakage prevention diffusion layer 101c can carry out by the mask with n+ injection zone 125 Impurity injection etc. and form.
As shown in Figure 9, make gate insulating film 117 and grid conducting film 118 film forming.Gate insulating film 117 is by oxide-film or high-k (High-k) film and form.In addition, the grid conducting film is to form by polysilicon (polysilicon) or metal film or these stromatolithic structure.
As shown in figure 10, use resist (resist) etc. 133, form the gate wirings pattern by photoetching.
As shown in figure 11, take resist 133 as mask, by grid conducting film 117 and gate insulating film 118 in addition etching removed.Form whereby gate wirings (118a to 118c).Afterwards, the mask 19 on pillar is removed.
As shown in figure 12, be to be made as after the dielectric film film forming by silicon nitride film etc. to be eat-back (etchback), and the structure sidewall of the sidewall of column silicon layer and gate electrode covered with the dielectric film 134 of silicon nitride film etc.
As shown in figure 13, by Implantation etc., impurity is directed in to p+ injection zone 124 and n+ injection zone 125 respectively, and forms the source diffusion layer (114,116) on column silicon layer top.Next, the metal of Ni etc. given to sputter and heat-treats, forming whereby the silicide layer 115 on the source diffusion layer on silicide layer (113a, 113b) on drain diffusion layer and column silicon layer top.
At this, the dielectric film 134 by the silicon nitride film that covers column silicon layer and the sidewall of gate electrode etc., can suppress because reach the short circuit between source electrode-grid between the caused drain electrode-grid of silicide layer.
As shown in figure 14, after forming the silicon oxide layer of interlayer film, form contact (106a, 106b, 108a, 108b, 110a, 110b, 111a, 111b).
(embodiment 2)
Figure 15 shows the SRAM layout of embodiment 2.The point different from embodiment 1 in the present embodiment is the different point of shape and the size of the column silicon layer that forms driver transistor of the column silicon layer that forms access transistor.In non-loaded 4T-SRAM of the present invention, the leakage current of access transistor need be set as also large than the leakage current of driver transistor.The means as the leakage current that increases access transistor, can be set as increasing more greatly leakage current by the column silicon layer that will form access transistor as shown in figure 15.The shape of column silicon layer need not be circular, also can be elliptical shape.
On the other hand, when wish is improved read margin, can form the electric current that increases more greatly driver transistor by the column silicon layer by driver transistor and improve read margin.
In the present embodiment, though be to use the layout of the pillar identical with embodiment 1 as an example, in fact be not limited to the layout of embodiment 1, also same applicable the present embodiment in the layout of other embodiment.
Point in addition, because the formation with shown in embodiment 1 is identical, therefore explanation is omitted.
(embodiment 3)
Figure 16 shows the sram cell layout of embodiment 3.Different at following point and embodiment 1 in the present embodiment.The Qa3 of the memory node formed by the 1st diffusion layer on substrate, the gate wirings of extending with gate electrode from driver transistor Qn23 are to be connected by the common contact 310a formed across both, the Qb3 of the memory node that the 2nd diffusion layer on substrate forms, with the gate wirings of gate electrode extension from driver transistor Qn13, are to be connected by the common contact 310b formed across both.By contact but not wiring layer directly connects grid and memory node, can reduce the quantity of the contact in sram cell as mentioned above, therefore can dwindle cellar area by the configuration of adjusting column silicon layer or contact.
As an example of the formation of the distribution of hierarchy type, can realize that distribution with lower floor forms Vss3 and forms the formation of bit line (BL3, BLB3) with the distribution on upper strata.In addition, in the present embodiment, node connects distribution Na3, node connects distribution Nb3 and forms by contact.
In the present embodiment, though be to use the layout of the pillar identical with embodiment 1 as an example, in fact be not limited to this layout, at also same applicable the present embodiment of other layout.
Point in addition, because the formation with shown in embodiment 1 is identical, therefore explanation is omitted.
(embodiment 4)
Figure 17 shows the sram cell layout of embodiment 4.In the present embodiment, be different at following point and embodiment 1.In embodiment 1, in memory node Qa1, though contact 110a only with driver transistor Qn11 in abutting connection with configuration, on memory node Qb1, contact 110b is on the diffusion layer be disposed between driver transistor Qn21 and access transistor Qp21.Due to the asymmetry of this kind of layout, can produce asymmetry in the characteristic of sram cell, and the possibility that operation margin is had narrow down.In the present embodiment, because the layout of the access transistor Qp24 on the access transistor Qp14 on the 1st memory node Qa4, contact (410a, 411a) and driver transistor Qn14 and the 2nd memory node Qb4, contact (410b, 411b) and driver transistor Qn24 is symmetrical, therefore do not have the deteriorated of the as above because caused operation margin of asymmetry, and can reach the sram cell with wider operation margin.
In addition, the distribution of bit line and the distribution of earthing potential, share for the distribution with other memory cell, preferably is configured in than the node of the distribution in each memory cell and connects the more upper layer of distribution.In the present embodiment, node connection distribution forms by contact.
As an example of the formation of hierarchy type distribution, can realize that the distribution with lower floor forms Vss4, form the formation of bit line (BL4, BLB4) with the distribution on upper strata.
(embodiment 5)
Figure 18 shows the sram cell layout of embodiment 5.Similarly to Example 4, layout is symmetrical to the present embodiment, therefore can reach the sram cell with wider operation margin.In addition, identical with embodiment 2, the Qa5 of the memory node formed by the 1st diffusion layer on substrate, the gate wirings of extending with gate electrode from driver transistor Qn25 are by being connected across both common contact 510a, and the Qb5 of the memory node that the 2nd diffusion layer on substrate forms, with the gate wirings of gate electrode extension from driver transistor Qn15, are by being connected across both common contact 510b.
In addition, the distribution of bit line and the distribution of earthing potential, share for the distribution with other memory cell, preferably is configured in than the node of the distribution in each memory cell and connects the more upper layer of distribution.In the present embodiment, node connection distribution forms by contact.
As an example of the formation of hierarchy type distribution, can realize that distribution with lower floor forms Vss5 and forms the formation of bit line (BL5, BLB5) with the distribution on upper strata.In addition, in the present embodiment, node connects distribution Na5, node connects distribution Nb5 and forms by contact.
In Figure 19, (a) shows the plane graph of the part of the SRAM memory cell array consisted of a plurality of SRAM memory cells.In cell array region in the drawings, in transverse direction, dispose a plurality of memory cells, and commonization there is word line 518a in a plurality of memory cells of transverse direction configuration.The word line is connected in the distribution on upper strata by the contact 507 that is formed at joining zone, and optionally with the wiring layer substrate.Therefore, different with the sram cell of patent documentation 2, owing to need not forming the contact for the word line at unit, therefore can dwindle the sram cell area.
By connecting a plurality of unit in word line 518a, distance word line contact 507 than the unit in distally in, likely because of the delay of the signal of word line, cause reading or the problem of write latency.Therefore, be connected in the element number of word line, can determine in the scope of the problem of the delay of not reading or writing.
In Figure 19, (b) shows the plane graph of the part of the sram cell array consisted of a plurality of sram cells in other situation.Cell array region in the drawings also disposes a plurality of memory cells in transverse direction equally, and commonization has word line 518a in being disposed at the memory cell of transverse direction.Yet, in (b) in Figure 19, even in joining zone, also with cell array region, dispose equally pillar.So, by joining zone, also configuring pillar, the characteristic that can will be adjacent to the SGT of joining zone suppresses in Min. with the error of the characteristic of the SGT that is not adjacent to joining zone.
In sum, according to the present invention, in the static type memory cell that uses 4 MOS transistor to form, aforementioned MOS transistor is for being disposed at drain electrode, grid, source electrode the SGT of vertical direction, and be adjacent to commonization of a plurality of unit of transverse direction by the grid using access transistor as the word line, and will form 1 according to a plurality of unit, the non-loaded 4T-SRAM of CMOS type that can realize having minimum memory unit area for the contact of word line.

Claims (6)

1. a semiconductor storage unit, possess a plurality of static type memory cells that are arranged with 4 MOS transistor on substrate, it is characterized in that,
Each person performance of aforementioned 4 MOS transistor as the 1st and the access transistor of 2PMOS, with the 1st and the function of the driver transistor of 2NMOS, the 1st and the access transistor of 2PMOS in order to keep memory cell data in order to supply with electric charge and access memory, and the 1st and the driver transistor of 2NMOS for the data of read memory unit in order to drive memory node;
The aforementioned the 1st and the access transistor of 2PMOS in,
P type the 1st diffusion layer, the 1st columnar semiconductor layers and P type the 2nd diffusion layer vertically are configured on substrate to stratum, and aforementioned the 1st columnar semiconductor layers be configured in the bottom that is formed at aforementioned the 1st columnar semiconductor layers aforementioned the 1st diffusion layer, and be formed between aforementioned the 2nd diffusion layer on top of aforementioned the 1st columnar semiconductor layers, be formed with the 1st grid in the sidewall of aforementioned the 1st columnar semiconductor layers;
The aforementioned the 1st and the driver transistor of 2NMOS in,
N-type the 3rd diffusion layer, the 2nd columnar semiconductor layers and N-type the 4th diffusion layer vertically are configured on substrate to stratum, and aforementioned the 2nd columnar semiconductor layers be configured in the bottom that is formed at aforementioned the 2nd columnar semiconductor layers aforementioned the 3rd diffusion layer, and be formed between aforementioned the 4th diffusion layer on top of aforementioned the 1st columnar semiconductor layers, be formed with the 2nd grid in the sidewall of aforementioned the 2nd columnar semiconductor layers;
The arrangement that is adjacent to each other of the access transistor of aforementioned 1PMOS and the driver transistor of aforementioned 1NMOS;
The arrangement that is adjacent to each other of the access transistor of aforementioned 2PMOS and the driver transistor of aforementioned 2NMOS;
Be formed with to give in a plurality of memory cells common 1st trap of current potential to this substrate in aforesaid substrate;
Being formed at aforementioned P type the 1st diffusion layer of bottom of access transistor of aforementioned 1PMOS and aforementioned N-type the 3rd diffusion layer of bottom that is formed at the driver transistor of aforementioned 1NMOS is connected to each other;
Aforementioned aforementioned P type the 1st diffusion layer connected to one another and N-type the 3rd diffusion layer performance are as the function of the 1st memory node of the data that are stored in memory cell in order to maintenance;
In order to prevent the leakage between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap, between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap with bottom than the element separating layer also shallow mode form the 1st Leakage prevention diffusion layer had with aforementioned the 1st trap opposite conductivity type;
Aforementioned the 1st Leakage prevention diffusion layer directly is connected with aforementioned P type the 1st diffusion layer or N-type the 3rd diffusion layer;
Being formed at aforementioned P type the 1st diffusion layer of bottom of access transistor of aforementioned 2PMOS and aforementioned N-type the 3rd diffusion layer of bottom that is formed at the driver transistor of aforementioned 2NMOS is connected to each other;
Aforementioned aforementioned P type the 1st diffusion layer connected to one another and N-type the 3rd diffusion layer performance are as the function of the 2nd memory node of the data that are stored in memory cell in order to maintenance;
In order to prevent the leakage between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap, between aforementioned N-type the 3rd diffusion layer or P type the 1st diffusion layer and aforementioned the 1st trap with bottom than the element separating layer also shallow mode form the 2nd Leakage prevention diffusion layer had with aforementioned the 1st trap opposite conductivity type;
Aforementioned the 2nd Leakage prevention diffusion layer directly is connected with aforementioned P type the 1st diffusion layer or N-type the 3rd diffusion layer;
The aforementioned the 1st and each person's of the driver transistor of aforementioned 2PMOS grid by the 1st gate wirings, be connected to each other, aforementioned the 1st gate wirings is connected to each other and forms the word line by each person's of the access transistor of the aforementioned the 1st and aforementioned 2PMOS in a plurality of memory cells more than 2 with adjacency grid;
Respectively at a plurality of memory cells of adjacency, form the 1st contact on aforementioned the 1st gate wirings that is the word line.
2. semiconductor storage unit according to claim 1, is characterized in that, in being formed with the zone of aforementioned the 1st contact on aforementioned the 1st gate wirings of aforementioned word line, with memory cell area, similarly disposes pillar.
3. semiconductor storage unit according to claim 1, is characterized in that, the 2nd gate wirings of extending from the grid of the driver transistor of aforementioned 1NMOS is connected with the diffusion layer of bringing into play as the function of aforementioned the 2nd memory node by the 2nd common contact;
The 3rd gate wirings of extending from the grid of the driver transistor of aforementioned 2NMOS is connected with the diffusion layer of bringing into play as the function of aforementioned the 1st memory node by the 3rd common contact.
4. semiconductor storage unit according to claim 1, it is characterized in that, form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the driver transistor of 2NMOS around length have be equal to or greater than form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the access transistor of 2PMOS around the value of length; Perhaps
Perhaps form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the driver transistor of 2NMOS around length have be equal to or less than form the aforementioned the 1st and the sidewall of the columnar semiconductor layers of the access transistor of 2PMOS around the value of length.
5. semiconductor storage unit according to claim 1, is characterized in that, aforementioned 4 MOS transistor are arranged in 2 row 2 row on described dielectric film;
The access transistor of aforementioned 1PMOS is arranged in the 1st row the 1st row;
The driver transistor of aforementioned 1NMOS is arranged in the 2nd row the 1st row;
The access transistor of aforementioned 2PMOS is arranged in the 1st row the 2nd row;
The driver transistor of aforementioned 2NMOS is arranged in the 2nd row the 2nd row.
6. semiconductor storage unit according to claim 1, is characterized in that, aforementioned 4 MOS transistor are
The access transistor of aforementioned 1PMOS and the access transistor of aforementioned 2PMOS are in abutting connection with arrangement;
In the side's in abutting connection with the direction quadrature of the access transistor of the access transistor with aforementioned 1PMOS and aforementioned 2PMOS direction, the driver transistor of aforementioned 1NMOS and the access transistor of aforementioned 1PMOS are in abutting connection with arrangement;
In the opposing party's in abutting connection with the direction quadrature of the access transistor of the access transistor with aforementioned 1PMOS and aforementioned 2PMOS direction, the driver transistor of aforementioned 2NMOS and the access transistor of aforementioned 2PMOS are in abutting connection with arrangement.
CN2012800091090A 2012-02-15 2012-02-15 Semiconductor storage device Pending CN103460373A (en)

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CN111899775A (en) * 2020-07-24 2020-11-06 安徽大学 SRAM memory cell circuit capable of realizing multiple logic functions and BCAM operation

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111899775A (en) * 2020-07-24 2020-11-06 安徽大学 SRAM memory cell circuit capable of realizing multiple logic functions and BCAM operation

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