JP3167036B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a large number of memory cells for storing bit data, and a peripheral circuit used for writing or reading bit data of the memory cells. The present invention relates to a semiconductor memory device whose degree of improvement can be improved.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor memory devices formed on the same substrate has been improved with the improvement of fine processing technology.

In order to shorten the access time of the semiconductor memory device and reduce the power consumption, a large number of memory cells for storing bit data inside the semiconductor memory device are divided into several blocks (basic units). ).

[0004] This is because only the block to which the memory cell to which the bit data is to be written or read in the semiconductor memory device belongs performs the operation of writing or reading the bit data, thereby driving the wiring portion to be driven. It is intended to reduce the length of the device and the number of operating logic gates to shorten the access time and the power consumption.

Conventionally, various methods have been tried for dividing a memory cell into blocks in a semiconductor memory device.

[0006]

However, as described above, the improvement of the integration degree of the conventional semiconductor memory device has been performed only in accordance with the improvement of the fine processing technology.

As described above, if the number of divided memory cells in a semiconductor memory device is further increased in order to reduce access time and power consumption, peripheral circuits and the like are provided for each divided block. Therefore, there is a problem that the number of elements that must be formed on the substrate is increased, and the degree of integration of the entire semiconductor memory device is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has a large number of memory cells for storing bit data and a peripheral circuit used for writing or reading bit data of the memory cells. It is an object of the present invention to provide a semiconductor memory device in which the degree of integration can be further improved with limited fine processing technology.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor memory device having a large number of memory cells for storing bit data and a peripheral circuit used for writing or reading bit data of the memory cells. has a lower portion to which the peripheral circuit is fabricated on a substrate, which is formed on the lower layer portion on the insulating film, a laminated structure of an upper portion of the memory cell is built, and the peripheral circuit ,Common
Write or read by selection by the peripheral circuit
The plurality of peripheral circuits having substantially the same area as the peripheral circuit.
A plurality of blocks, each including a memory cell as one block unit.
The object has been achieved by being constituted by a lock .

The peripheral circuit includes a sense amplifier and a decoder.
And a write amplifier, wherein the memory cell is a thin film
By forming the transistor, the above-mentioned object is also achieved.

[0011]

According to the present invention, in order to improve the degree of integration of a semiconductor memory device, the structure of the semiconductor memory device formed on a semiconductor substrate is made to be a laminated structure.

As a technique for manufacturing a semiconductor integrated circuit having a laminated structure, a predetermined circuit composed of a transistor or the like is formed as a lower layer portion, an oxide film is formed thereon, and the amorphous or multi-layered structure is formed. There is a technique in which a crystalline silicon deposited film is heated to be single-crystallized or single-crystallized by irradiation with an energy beam, and another circuit including a transistor or the like as an upper layer portion is formed on the single-crystallized film. This is generally SOI
(Silicon ON Insulator) technology.

However, it is an extremely difficult technique to make the amorphous or polycrystalline silicon provided above the lower layer portion into a single crystal uniformly over a large area.

According to the present invention, in order to solve such a problem, when a semiconductor memory device has a laminated structure, a thin film transistor (hereinafter, referred to as a TFT) is provided in an upper layer portion.
) Is formed.

A memory cell composed of such a TFT can be formed relatively easily in the upper layer of a semiconductor memory device having a laminated structure as compared with the above-mentioned SOI technology.

Further, for example, when the semiconductor memory device has a laminated structure and the memory cell inside the semiconductor memory device is divided into a larger number of blocks, the memory cell constituted by the TFTs is The target to be driven is limited, and the degree of dependence on the characteristics of the transistor is reduced.

According to the present invention, the area of the memory cell group formed in the upper layer portion is set to be substantially the same as the area of the peripheral circuit of the memory cell group, and the memory cell group and the peripheral circuit are formed as one basic circuit. As a unit, the semiconductor memory device may be constituted by a plurality of the basic units.

By doing so, the area of the peripheral circuit of each basic unit falls in the lower layer of the range of the area of the memory cell group of each basic unit, and the number of divisions of the semiconductor memory device into basic units is increased. The problem that the area of the peripheral circuit increases and the degree of integration of the entire semiconductor memory device decreases can be solved.

In this regard, FIG. 10 and FIG.
1 will be described later.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of one memory cell block according to the embodiment of the present invention.

The semiconductor memory device of the present embodiment has a plurality of FIG.
The memory cell block 40 shown in FIG.

When writing or reading bit data, only the memory cell block 40 containing the bit data to be written or read is selected.

In FIG. 1, memory cell block 4
0 is composed of the memory cell section 20 and the peripheral circuit 10.

The memory cell section 20 is composed of a large number of memory cells 22 for storing bit data.

The peripheral circuit 10 includes a sense amplifier and a column decoder 12 (hereinafter simply referred to as a column decoder 12).
) And the row decoder 14.

Each of the memory cells 22 storing the bit data of the memory cell section 20 is selected by the row decoder 14 for one of the word lines WL1, WL2 to WLn when writing or reading the bit data. At the time of writing or reading, the column decoder 12 sets the bit lines BL1a, BL2a to BLna
A corresponding bit line pair is selected from the respective bit line pairs of the bit line BL1b and BL2b to BLnb to write or read bit data of a desired memory cell 22.

FIG. 2 is a circuit diagram of a memory cell used in the above embodiment.

FIG. 2 shows the circuit of the memory cell 22 in the i-th row and the j-th column among the many memory cells 22 in the memory cell section 20 of FIG.

In FIG. 2, a memory cell 22 has P
Channel MOSTFT1 and N-channel MOSTFT
3 and one P-channel MO
This is a flip-flop configured to store bit data and configured by an inverter configured by STFT2 and N-channel MOSTFT4.

When writing or reading bit data to or from this memory cell, the corresponding word line WL
i is set to the H state, and the corresponding N-channel MOSTFT transistors T5 and T6 are both turned on. afterwards,
The bit lines BLja and BL
Data is read and written by selecting a bit line pair consisting of jb.

FIG. 3 is a circuit diagram of an example of a column decoder used in this embodiment.

The column decoder shown in FIG. 3 uses pre-decode signals CA0-C by multi-input NAND gate 32.
After decoding An (for the column address), the column selection signal CLj is output via the inverter gate 34.

The column selection signal CLj shown in FIG.
Are used to select a corresponding bit line pair.

FIG. 4 is a circuit diagram of an example of a row decoder used in this embodiment.

In FIG. 4, a multi-input NAND gate 36 decodes predecode signals RA0 to RAn (for a row address) and drives a word line WLi via an inverter gate 34.

The word line WLi in FIG. 4 is the same as the word line WLi in FIG.

FIG. 5 is a circuit diagram of a sense amplifier used in this embodiment.

In FIG. 5, symbols BLja, BLjb,
VCC and VSS are the same as those having the same reference numerals in FIG. 5 is the same as that of FIG.
Are the same as those having the same reference numerals.

In FIG. 5, input / output lines I / Oa and I / Oa
/ Ob is a pair of input / output line pairs, and is a wiring for inputting / outputting bit data to be written or read from the outside of the semiconductor memory device when writing or reading bit data.

The read signals φSEa and φSEb are
When one set is a read signal line pair and the access to the semiconductor memory device is a read operation, the read signal line φSEa goes high, and the read signal line φSEb
Attains an L state, and N-channel MOS transistor T17
And P-channel MOS transistor T18 are both turned on.

If the access is a write,
The read signal line φSEa goes low, the read signal line φSEb goes high, and both the N-channel MOS transistor T17 and the P-channel MOS transistor T18 are turned off. Thereafter, information according to an external input is written via a pair of I / O lines by a write amplifier (not shown).

The input / output lines I / Oa and I / Ob
And read signal lines φSEa and φSEb are respectively
Shared with sense amplifiers in other columns.

The main part of the sense amplifier of FIG. 5 includes two P-channel MOS transistors T11 and T12,
This is a latch circuit composed of two N-channel MOS transistors T13 and T14. That is, the sense amplifier shown in FIG. 5 is a so-called latch type sense amplifier.

This sense amplifier is an example of the sense amplifier used in the present invention, and the present invention is not necessarily limited to this.

In the latch type sense amplifier shown in FIG. 5, when the read signal line φSEa goes high and the read signal line φSEb goes low, the bit data is read from the memory cell.

At this time, when the column selection signal CLj is set to the H state and the j-th column is selected, both the N-channel MOS transistors T15 and T16 are turned on, and this sense amplifier is supplied from the memory cell. Amplify the bit data.

The read bit data amplified by the sense amplifier is output through input / output lines I / Oa and I / Ob.

FIG. 6 is a layout diagram of a part of the upper layer of this embodiment.

In FIG. 6, reference characters BL1a, BL1
b, BL2a, BL2b are the same as the bit lines of the same reference numerals in FIG. 1 described above, and BL3a, BL3a,
BL3b is a similar bit line. The symbols VCC, VSS, T1 to T6 in FIG. 6 correspond to the same symbols in FIG.

FIG. 7 is a layout diagram of a part of the lower layer of this embodiment.

In FIG. 7, symbols VCC, VSS,
T11 to T16 correspond to the same reference numerals in FIG. 5 described above.

FIG. 8 is a sectional view of this embodiment.

FIG. 8 is a cross-sectional view including both the upper layer portion and the lower layer portion, which is indicated by the ab section in FIG. 6 described above or is indicated by the ab section in FIG. 7 described above.

In FIGS. 6 to 8, reference characters AL1,
AL2 is an aluminum wiring layer. Symbols M1 to M3
Is a metal wiring layer. Symbols PL1 to PL3 are polysincon layers.

In FIG. 6, although aluminum wiring layers AL1 and AL2 are partially omitted from illustration, they are wired in the uppermost layer of the upper layer shown in FIG. Similarly, in FIG. 7, a part of the metal wiring layer M2 is not shown, but is wired in the uppermost layer of the lower layer part shown in FIG. Although only the wiring of some memory cells is shown in the metal wiring layer M3 (dashed line) in FIG. 6 and the metal wiring layer M1 (dashed line) in FIG. 7, other memory cells are similarly wired. .

6 to 8 described above are made on the same scale, and the ab cross section is the same. The upper layer of FIG. 6 and the lower layer of FIG. 7 are overlapped by matching the ab cross section, the size of one bit of the memory cell, and the like, and the positional relationship of each part follows this.

FIG. 9 is a diagram showing contact symbols used in the above-described layout diagrams of FIGS. 6 and 7, and shows what kind of connection each contact symbol represents. Have been.

The memory cell block 40 of the semiconductor memory device of the present embodiment described above with reference to FIGS.
As shown in FIG. 11, for each memory cell block 40 (for each basic unit), the peripheral circuit 10 is formed as a lower layer on a semiconductor substrate, and the memory cell section 20 is formed as an upper layer.
The peripheral circuit 10 is formed on an insulating film formed on a lower layer portion where the peripheral circuit 10 is formed.

Therefore, with such a laminated structure of the present embodiment, the chip area of the memory cell block 40 can include the layout of the peripheral circuit, not only the area of the memory cell section 20.

According to the present invention, when an attempt is made to divide a semiconductor memory device into blocks for the purpose of shortening access time or reducing power consumption, it is possible to reduce the degree of integration of the entire semiconductor memory device. , The unit of block division can be reduced.

For example, the memory cell unit 20 (memory cell group) for one memory cell block shown by oblique lines in FIG.
Can be reduced until it becomes the same as the area of the peripheral circuit 10 for one memory cell block indicated by oblique lines in FIG. 11, and the adverse effect on the integration degree of the entire semiconductor memory device is small.

In the present embodiment, a predetermined circuit is formed in the lower layer portion, and then the memory cell portion 20 is formed in the upper layer portion.
Since it is configured using T and N channel MOS TFTs,
It can be formed relatively easily without using SOI technology.

[0064]

As described above, according to the present invention,
In a semiconductor memory device having a large number of memory cells for storing bit data and a peripheral circuit used when writing or reading the bit data of the memory cells,
It is possible to obtain an excellent effect that the degree of integration can be further improved by the limited fine processing technology.

[Brief description of the drawings]

FIG. 1 is a block diagram of one memory cell block according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell used in the embodiment.

FIG. 3 is a logic circuit diagram of a column decoder used in the embodiment.

FIG. 4 is a logic circuit diagram of a row decoder used in the embodiment.

FIG. 5 is a circuit diagram of a sense amplifier used in the embodiment.

FIG. 6 is an integrated circuit pattern diagram of a part of an upper layer portion of the embodiment.

FIG. 7 is an integrated circuit pattern diagram of a part of a lower layer portion of the embodiment.

FIG. 8 is a sectional view of the integrated circuit pattern of the embodiment.

FIG. 9 is a diagram showing contact symbols used in the integrated circuit pattern diagram of FIG. 6 and the integrated circuit pattern diagram of FIG. 7;

FIG. 10 is a layout diagram of a memory cell block (an upper layer memory cell section) of the embodiment on a semiconductor memory device.

FIG. 11 is a layout diagram of a memory cell block (lower peripheral circuit) of the embodiment on a semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Peripheral circuit (lower part), 12 ... Sense amplifier and column decoder, 14 ... Row decoder, 20 ... Memory cell part (upper part), 22 ... Memory cell, 32, 36 ... Multi-input NAND gate, 34 ... Inverter gate , 40 ... memory cell block, AL1, AL2 ... aluminum wiring layer, BL1a, BL2a, BLja, BLna, BL1b, BL
2b, BLjb, BLnb... Bit lines, CAφ to CAn, RAφ to RAn... Predecode signals, CLj... Column select signals, I / Oa, I / Ob. ... Polysilicon layer, T1, T2 ... P-channel MOS TFT, T3 to T6 ... N-channel MOS TFT, T11, T12, T18 ... P-channel MOS transistor, T13 to T17 ... N-channel MOS transistor, WL1, WL2, WLi, WLn ... word Lines, φSEa, φSEb ... readout signal lines.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8224 H01L 27/11 H01L 27/10 471

Claims (2)

(57) [Claims] 1. A semiconductor memory device comprising: a plurality of memory cells for storing bit data; and a peripheral circuit used for writing or reading the bit data of the memory cell , wherein the peripheral circuit is formed on a semiconductor substrate. and filled-in lower part, which is formed on the lower layer portion on the insulating film has a laminated structure of an upper portion of the memory cell is built, selection by the peripheral circuit, the common of said peripheral circuit Written by
Write or read, almost the same as the peripheral circuit
A plurality of memory cells having an area and one block
It must be composed of a plurality of such blocks as a unit.
The semiconductor memory device according to claim and. 2. The device according to claim 1, wherein said peripheral circuit comprises a sense amplifier, a decoder, and a write amplifier.
It consists, semiconductor memory device, wherein the memory cell is formed by a thin film transistor.