JPH056979A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enhance the degree of integration by means of a limited fine processing technology. CONSTITUTION:A semiconductor memory device consists of a plurality of memory cell blocks 40. The memory cell blocks 40 comprise a memory cell section 20 and a peripheral circuit 10. The peripheral circuit 10 is built in a semiconductor board as its lower layer while the memory cell section 20 is built in an insulation film formed on the lower layer as its upper part. The degree of integration is enhanced by the lamination structure as described above. In addition, it is possible to form easily a memory cell transistor on the upper layer without any sophisticated SOI technology by using a thin film transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a large number of memory cells for storing bit data and a peripheral circuit used when writing or reading bit data of the memory cells, and more particularly to an integrated memory device. The present invention relates to a semiconductor memory device capable of improving the degree.

[0002]

2. Description of the Related Art In recent years, with the improvement of fine processing technology, the degree of integration of semiconductor memory devices formed on the same substrate has been improved.

Further, in order to shorten the access time of the semiconductor memory device and to reduce the power consumption, a large number of memory cells for storing bit data inside the semiconductor memory device are divided into some blocks (basic units). ) Is done.

This is a wiring portion driven by the operation of writing or reading bit data only in the block to which the memory cell to be written or read of bit data in the semiconductor memory device belongs. The number of active logic gates and the number of active logic gates are reduced to shorten access time and power consumption.

Various methods have heretofore been attempted for dividing a memory cell into blocks in such a semiconductor memory device.

[0006]

However, as described above, the improvement in the degree of integration of the conventional semiconductor memory device has been made only in accordance with the improvement in the fine processing technology.

Further, as described above, if the number of block divisions of the memory cells inside the semiconductor memory device is further improved in order to shorten the access time and reduce the power consumption, the peripheral circuits etc. for each divided block will be improved. Therefore, there is a problem in that the number of elements that must be formed on the substrate is increased and the integration degree of the entire semiconductor memory device is reduced.

The present invention has been made to solve the above-mentioned conventional problems, and comprises a large number of memory cells for storing bit data, and a peripheral circuit used when writing or reading bit data of the memory cells. Another object of the present invention is to provide a semiconductor memory device capable of further improving the degree of integration with a limited fine processing technique.

[0009]

The present invention provides a semiconductor memory device comprising a large number of memory cells for storing bit data, and a peripheral circuit used when writing or reading bit data of the memory cells. By having a laminated structure of a lower layer portion in which the peripheral circuit is formed on a substrate and an upper layer portion in which the memory cell is formed on an insulating film formed on the lower layer portion, the above problems can be solved. Has been achieved.

Further, the lower layer portion is formed on the substrate by a conventional CMO.
A lower layer portion including peripheral circuits such as a sense amplifier, a decoder, and a write amplifier formed by S process, and the upper layer portion is
The memory cell group, which is an upper layer portion in which a memory cell formed of a thin film transistor is formed on an insulating film formed on the lower layer portion, and has the same area as the peripheral circuit, and the peripheral circuit are regarded as one basic unit. The above-mentioned problems are also achieved by being constituted by a plurality of the basic units.

[0011]

According to the present invention, in order to improve the degree of integration of the semiconductor memory device, the structure of the semiconductor memory device formed on the semiconductor substrate is a laminated structure.

As a technique for manufacturing a semiconductor integrated circuit having a laminated structure, a predetermined circuit such as a transistor is formed as a lower layer portion than before, and an oxide film is formed on the predetermined circuit. There is a technique in which a crystalline silicon deposition film is heated to be single-crystallized or to be single-crystallized by irradiation with an energy beam, and another circuit including a transistor or the like as an upper layer portion is formed in this. This is generally SOI
It is called (Silicon ON Insulator) technology.

However, it is a very difficult technique to uniformly form the amorphous or polycrystalline silicon provided above the lower layer portion into a single crystal over a large area.

In order to solve such a problem, the present invention has a thin film transistor (hereinafter, referred to as TFT) as an upper layer when a semiconductor memory device has a laminated structure.
Called)).

A memory cell composed of such a TFT can be formed relatively easily in the upper layer portion of the semiconductor memory device having a laminated structure, as compared with the SOI technique described above.

Further, for example, when the semiconductor memory device has a laminated structure and the block division of the memory cell inside the semiconductor memory device is divided into more blocks, the memory cell constituted by the TFT is The target to be driven is limited, and the degree of dependence on the characteristics of the transistor becomes smaller.

According to the present invention, the area of the memory cell group formed in the upper layer portion is set to be substantially the same as the area of the peripheral circuit of this memory cell group, and the memory cell group and the peripheral circuit are formed into one basic unit. Alternatively, the semiconductor memory device may be composed of a plurality of basic units.

By doing so, the area of the peripheral circuit of each basic unit is contained in the lower layer portion of the range of the area of the memory cell group of each basic unit, and when the number of divisions of the semiconductor memory device into basic units is increased. It is possible to solve the problem that the area of the peripheral circuit increases and the integration degree of the entire semiconductor memory device decreases.

Regarding this point, FIG. 10 and FIG.
It will be described later using 1.

[0020]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one memory cell block according to the embodiment of the present invention.

The semiconductor memory device of this embodiment has a plurality of components shown in FIG.
The memory cell block 40 shown in FIG.

When writing or reading bit data, only the memory cell block 40 containing the bit data to be written or read is selected.

In FIG. 1, the memory cell block 4
Reference numeral 0 is composed of the memory cell section 20 and the peripheral circuit 10.

The memory cell section 20 is composed of a large number of memory cells 22 for storing bit data.

Further, the peripheral circuit 10 includes a sense amplifier and a column decoder 12 (hereinafter, simply the column decoder 12).
Is called) and the row decoder 14.

Each of the memory cells 22 for storing the bit data of the memory cell section 20 is selected by the row decoder 14 for one row of the word lines WL1, WL2 to WLn when writing or reading the bit data. Further, at the time of this writing or reading, the column decoder 12 causes the bit lines BL1a, BL2a to BLna.
Of the bit lines BL1b and BL2b to BLnb, the corresponding bit line pair is selected to write or read the bit data of the desired memory cell 22.

FIG. 2 is a circuit diagram of a memory cell used in the above embodiment.

FIG. 2 shows a circuit of the memory cell 22 in the i-th row and the j-th column among the large number of memory cells 22 in the memory cell section 20 shown in FIG.

In FIG. 2, the memory cell 22 has a P
Channel MOST TFT1 and N channel MOST TFT
1 inverter composed of 3 and P channel MO
It is a flip-flop for storing bit data, which is composed of an inverter composed of STFT2 and N-channel MOSTFT4.

When writing or reading bit data to or from this memory cell, the corresponding word line WL
i is set to the H state, and the corresponding N-channel MOSTFT transistors T5 and T6 are both turned on. afterwards,
By the column decoder, bit line BLja and bit line BL
Data is read and written by selecting the bit line pair consisting of jb and jb.

FIG. 3 is a circuit diagram of an example of the column decoder used in this embodiment.

The column decoder shown in FIG. 3 has predecode signals CA0-C in multi-input NAND gate 32.
After decoding An (for column address), the column selection signal CLj is output via the inverter gate 34.

The column selection signal CLj shown in FIG.
Are used to select the corresponding bit line pair.

FIG. 4 is a circuit diagram of an example of the row decoder used in this embodiment.

In FIG. 4, multi-input NAND gate 36 decodes predecode signals RA0 to RAn (for row address) and drives word line WLi via inverter gate 34.

The word line WLi shown in FIG. 4 is the same as the word line WLi shown in FIG.

FIG. 5 is a circuit diagram of a sense amplifier used in this embodiment.

In FIG. 5, reference numerals BLja, BLjb,
VCC and VSS are the same as those having the same reference numerals in FIG. Further, the reference symbol CLj in FIG. 5 is the same as that in FIG.
Is the same as the one with the same sign.

In FIG. 5, input / output lines I / Oa, I
/ Ob is a pair of I / O line pairs, and is a wiring for inputting / outputting bit data to be written or read to / from the outside of the semiconductor memory device when writing or reading bit data.

Further, the read signals φSEa and φSEb are
When a pair of read signal lines is formed and the access to the semiconductor memory device is read, the read signal line φSEa becomes H state and the read signal line φSEb.
Becomes the L state, and the N-channel MOS transistor T17
Both the P-channel MOS transistor T18 and the P-channel MOS transistor T18 are turned on.

If the access is writing,
The read signal line φSEa goes into the L state, the read signal line φSEb goes into the H state, and the N-channel MOS transistor T17 and the P-channel MOS transistor T18 are both turned off. Then, a write amplifier (not shown) writes information according to the external input through the I / O line pair.

These input / output lines I / Oa and I / Ob
And the read signal lines φSEa and φSEb are respectively
It is shared with the sense amplifiers of other columns.

The main part of the sense amplifier of FIG. 5 is composed of two P-channel MOS transistors T11, T12 and 2
The latch circuit is composed of two N-channel MOS transistors T13 and T14. That is, the sense amplifier shown in FIG. 5 is a so-called latch type sense amplifier.

This sense amplifier is an example of the sense amplifier used in the present invention, and the present invention is not necessarily limited to this.

In the latch type sense amplifier shown in FIG. 5, when the read signal line φSEa is in the H state and the read signal line φSEb is in the L state, the bit data is read from the memory cell.

At this time, when the column selection signal CLj is in the H state and the j-th column is selected, both N-channel MOS transistors T15 and T16 are turned on, and this sense amplifier outputs from the memory cell. Amplify bit data.

The read bit data amplified by the sense amplifier is output through the input / output lines I / Oa and I / Ob.

FIG. 6 is a layout diagram of a part of the upper layer portion of this embodiment.

In FIG. 6, reference symbols BL1a and BL1
b, BL2a, and BL2b are the same as the bit lines with the same reference numerals in FIG. 1, and BL3a, BL3a with the reference numerals in FIG.
BL3b is a similar bit line. Reference numerals VCC, VSS, T1 to T6 in FIG. 6 correspond to the same reference numerals in FIG.

FIG. 7 is a layout diagram of a part of the lower layer portion of this embodiment.

In FIG. 7, reference numerals VCC, VSS,
T11 to T16 correspond to the same reference numerals in FIG. 5 described above.

FIG. 8 is a sectional view of this embodiment.

FIG. 8 is a sectional view including both the upper layer portion and the lower layer portion, which is shown in the ab section of FIG. 6 described above or the ab section of FIG. 7 described above.

In these FIGS. 6 to 8, reference characters AL1,
AL2 is an aluminum wiring layer. Reference symbols M1 to M3
Is a metal wiring layer. Reference symbols PL1 to PL3 are polysinccon layers.

Although the aluminum wiring layers AL1 and AL2 are partially omitted in FIG. 6, they are wired in the uppermost layer of the upper layer portion shown in FIG. Similarly, in FIG. 7, the metal wiring layer M2 is partially not shown, but is wired in the uppermost layer of the lower layer portion shown in FIG. Further, in the metal wiring layer M3 (broken line) in FIG. 6 and the metal wiring layer M1 (broken line) in FIG. 7, only the wirings of some memory cells are shown, but other memory cells are similarly wired. .

6 to 8 described above are made to the same scale, and the ab cross section is the same. Further, the upper layer portion in FIG. 6 and the lower layer portion in FIG. 7 are overlapped with each other by matching the ab cross section and the size of one bit of the memory cell, etc., and the positional relationship of each portion follows this.

FIG. 9 is a diagram showing the contact symbols used in the layout diagrams of FIGS. 6 and 7, and shows what connection each contact symbol makes. Has been done.

The memory cell block 40 of the semiconductor memory device of this embodiment described with reference to FIGS.
As shown in FIG. 11, for each memory cell block 40 (each basic unit), the peripheral circuit 10 is formed as a lower layer portion on the semiconductor substrate, and the memory cell portion 20 is an upper layer portion.
The peripheral circuit 10 is formed on the insulating film formed on the lower layer part.

Therefore, with such a laminated structure of the present embodiment, the chip area of the memory cell block 40 is not limited to the area of the memory cell portion 20, and the layout of the peripheral circuits can be included.

When the semiconductor memory device is divided into blocks for the purpose of shortening the access time or reducing the power consumption, according to the present invention, the degree of integration of the entire semiconductor memory device is not reduced. , The unit of block division can be reduced.

For example, the memory cell section 20 (memory cell group) for one memory cell block indicated by the diagonal lines in FIG.
11 can be reduced to the same area as the area of the peripheral circuit 10 for one memory cell block indicated by the diagonal lines in FIG. 11, and the adverse effect on the integration degree of the entire semiconductor memory device is small.

In this embodiment, a predetermined circuit is formed in the lower layer and then the memory cell section 20 is formed in the upper layer. The memory cell section 20 is formed by the P-channel MOSTF.
Since it is configured using T and N channel MOSTFT,
It can be formed relatively easily without using SOI technology.

[0064]

As described above, according to the present invention,
In a semiconductor memory device comprising a large number of memory cells for storing bit data and a peripheral circuit used when writing or reading bit data of the memory cells,
The excellent effect that the degree of integration can be further improved by the limited fine processing technology can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of one memory cell block according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell used in the above embodiment.

FIG. 3 is a logic circuit diagram of a column decoder used in the above embodiment.

FIG. 4 is a logic circuit diagram of a row decoder used in the above embodiment.

FIG. 5 is a circuit diagram of a sense amplifier used in the embodiment.

FIG. 6 is a partial integrated circuit pattern diagram of the upper layer portion of the embodiment.

FIG. 7 is a partial integrated circuit pattern diagram of a lower layer portion of the embodiment.

FIG. 8 is a cross-sectional view of an integrated circuit pattern of the above embodiment.

FIG. 9 is a diagram showing contact symbols used in the integrated circuit pattern diagram of FIG. 6 and the integrated circuit pattern diagram of FIG. 7.

FIG. 10 is a layout diagram of the memory cell block (upper layer memory cell portion) of the above-described embodiment on the semiconductor memory device.

FIG. 11 is a layout diagram on the semiconductor memory device of the memory cell block (peripheral circuit of the lower layer portion) of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Peripheral circuit (lower layer part), 12 ... Sense amplifier and column decoder, 14 ... Row decoder, 20 ... Memory cell part (upper layer part), 22 ... Memory cell, 32, 36 ... Multi-input NAND gate, 34 ... Inverter gate , 40 ... Memory cell block, AL1, AL2 ... Aluminum wiring layer, BL1a, BL2a, BLja, BLna, BL1b, BL
2b, BLjb, BLnb ... Bit line, CAφ to CAn, RAφ to RAn ... Predecode signal, CLj ... Column selection signal, I / Oa, I / Ob ... Input / output line, M1 to M3 ... Metal wiring layer, PL1 to PL3 ... polysilicon layer, T1, T2 ... P-channel MOSTFT, T3-T6 ... N-channel MOSTFT, T11, T12, T18 ... P-channel MOS transistor, T13-T17 ... N-channel MOS transistor, WL1, WL2, WLi, WLn ... Word Line, φSEa, φSEb ... Read signal line.

Claims (2)

[Claims] 1. A semiconductor memory device comprising a large number of memory cells for storing bit data and a peripheral circuit used when writing or reading bit data of the memory cells, wherein the peripheral circuit on a semiconductor substrate is On the built-in lower layer portion and the insulating film formed on the lower layer portion,
A semiconductor memory device having a laminated structure with an upper layer portion in which the memory cell is formed. 2. The lower layer section according to claim 1, wherein the lower layer section is composed of peripheral circuits such as a sense amplifier, a decoder and a write amplifier which are formed by a conventional CMOS process on a substrate,
The upper layer portion is an upper layer portion in which a memory cell formed of a thin film transistor is formed on an insulating film formed on the lower layer portion, and the memory cell group having substantially the same area as the peripheral circuit and the peripheral circuit are provided. A semiconductor memory device comprising one basic unit and a plurality of the basic units.