JP2018045753A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device allowing data to be searched at a high speed.SOLUTION: The semiconductor device comprises: a first cell (MDC0) capable of holding information of one bit; a second cell (DC0) adjacent to the first cell; first and second match lines (MLA0 and MLB0) extending along a first direction; a pair of first search lines (SLA0 and /SLA0) extending in a second direction orthogonal to the first direction to transmit first data; a pair of second search lines (SLB0 and /SLB0) extending in the second direction to transmit second data; a first logical operation cell (LCA0) which is connected to the pair of search lines and the first match line and drives the first match line on the basis of a result of comparison between information held in the first and second cells and the first data transmitted to the pair of first search lines; and a second logical operation cell (LCB0) which is connected to the pair of second search lines and the second match line and drives the second match line on the basis of a result of comparison between information held in the first and second cells and the second data transmitted to the pair of second search lines.SELECTED DRAWING: Figure 11

Description

  The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a search function.

  In recent years, with the spread of the Internet, the demand for content addressable memory (CAM) has increased. The CAM has a comparison function for detecting coincidence between data inputted from the outside and data held inside, in addition to the original storage function of the memory that holds data. Used for conversion tables and the like.

  The search device disclosed in Japanese Patent Application Laid-Open No. 2-191998 (Patent Document 1) uses a memory cell (CAM cell) having a built-in comparison function for detecting a match for each 1-bit storage circuit holding data. Without reading out the data held in the storage circuit, the detection of coincidence between the data input from the outside and the data held in the storage circuit is executed.

Japanese Patent Laid-Open No. 2-192098

  In recent years, in addition to the address search function, the CAM searches for a similar pattern (minimum distance search) that searches for the most similar pattern from an input pattern and a reference pattern stored in a database in fields such as image recognition processing. It is used to realize functions. As the number of addresses to be searched and the number of patterns to be processed increase, the number of arithmetic processes in the CAM increases. Therefore, particularly when real-time processing is required, improvement in processing speed in CAM is required. In addition, the memory capacity of the CAM has increased in recent years, and high integration of the CAM is also required.

  The present disclosure has been made to solve the above-described problem, and in one aspect, provides a semiconductor device capable of high-speed data search.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a first cell configured to hold 1-bit information, a second cell adjacent to the first cell, configured to hold 1-bit information, and a first direction. A first match line extending along the second direction, a first search line pair extending along a second direction orthogonal to the first direction and transmitting the first data during the first data search, and a second The second search line pair that extends along the direction and transmits the second data at the time of the second data search, is connected to the first search line pair and the first match line, and is held by the first and second cells. A first logic operation cell for driving the first match line based on a comparison result between the information and the first data transmitted to the first search line pair, the second search line pair and the second match line; The information held in the first and second cells and the second data transmitted to the second search line pair And a second logic operation cells for driving the second match line based on the compare results.

  A semiconductor device according to an embodiment can realize high-speed data search while suppressing an increase in size of the device.

It is a block diagram explaining the example of a structure of the semiconductor device according to a certain embodiment. It is a circuit diagram explaining the example of a structure of the memory cell according to a certain embodiment. FIG. 3 is a plan view showing an arrangement of memory cell wells, diffusion regions, polysilicon, contact holes, and first layer metal wirings arranged in a semiconductor device. FIG. 3 is a plan view showing an arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell arranged in a semiconductor device. FIG. 6 is a plan view showing an arrangement of vias 2, second metal wiring layers and third metal wiring layers of memory cells arranged in a semiconductor device. It is a circuit diagram explaining the structural example of the memory cell according to other embodiment. It is a block diagram explaining the structural example of the semiconductor device according to other embodiment. FIG. 10 is a plan view showing an arrangement of a well, a diffusion region, polysilicon, a contact hole, and a first layer metal wiring of a memory cell according to another embodiment. FIG. 10 is a plan view showing the arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell according to another embodiment. It is a block diagram explaining the example of a structure of the semiconductor device according to a certain embodiment. 3 is a circuit diagram illustrating a configuration example of a memory cell arranged in a semiconductor device. FIG. It is a figure which shows the correspondence of the data which the data cell of FIG. 11 and a mask data cell hold | maintain, and the data of a memory cell in a table format. FIG. 3 is a plan view showing an arrangement of memory cell wells, diffusion regions, polysilicon, contact holes, and first layer metal wirings arranged in a semiconductor device. FIG. 3 is a plan view showing an arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell arranged in a semiconductor device. FIG. 6 is a plan view showing an arrangement of vias 2, second metal wiring layers and third metal wiring layers of memory cells arranged in a semiconductor device. It is a figure explaining the metal wiring pattern in the memory cell according to a certain embodiment. It is a circuit diagram explaining the structural example of the memory cell as a TCAM cell according to other embodiment. It is a figure which shows the correspondence of the data which the data cell and mask data cell of FIG. 17 hold | maintain, and the data of a memory cell in a table format. It is a block diagram explaining the structural example of the semiconductor device according to other embodiment. It is the top view which showed arrangement | positioning of the well of a memory cell as a TCAM cell according to other embodiment, a diffusion region, a polysilicon, a contact hole, and 1st layer metal wiring. It is a block diagram explaining the example of a structure of the semiconductor device according to a certain embodiment. FIG. 11 is a circuit diagram illustrating a configuration example of a memory cell of a semiconductor device. FIG. 3 is a plan view showing an arrangement of memory cell wells, diffusion regions, polysilicon, contact holes, and first layer metal wirings arranged in a semiconductor device. FIG. 3 is a plan view showing an arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell arranged in a semiconductor device. FIG. 6 is a plan view showing an arrangement of vias 2, second metal wiring layers and third metal wiring layers of memory cells arranged in a semiconductor device. FIG. 10 is a circuit diagram illustrating a configuration example of a memory cell according to a modification of the third embodiment. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device according to a modification of the third embodiment. FIG. 10 is a plan view showing an arrangement of a well, a diffusion region, polysilicon, a contact hole, and a first layer metal wiring of a memory cell according to a modification of the third embodiment. FIG. 3 is a plan view showing an arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell arranged in a semiconductor device. FIG. 6 is a plan view showing an arrangement of vias 2, second metal wiring layers and third metal wiring layers of memory cells arranged in a semiconductor device. It is a figure showing the structure of a transistor. FIG. 10 is a plan view showing an arrangement of a well, a diffusion region, polysilicon, and local wiring of a memory cell according to a fourth embodiment. FIG. 10 is a plan view showing an arrangement of vias 0, local wirings, and first level metal wiring layers of a memory cell according to a fourth embodiment. FIG. 10 is a plan view showing an arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell according to a fourth embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a memory cell of a semiconductor device according to a fifth embodiment. FIG. 10 is a diagram for explaining a metal wiring pattern in each memory cell constituting a semiconductor device according to a fifth embodiment. FIG. 10 is a plan view showing an arrangement of a well, a diffusion region, polysilicon, and local wiring of a memory cell according to a fifth embodiment. FIG. 10 is a plan view showing an arrangement of vias 0, local wirings, and first level metal wiring layers of a memory cell according to a fifth embodiment. FIG. 10 is a plan view showing an arrangement of vias 1, first-layer metal wiring layers, and second-layer metal wiring layers of a memory cell according to a fifth embodiment. FIG. 10 is a plan view showing an arrangement of vias 2, second layer metal wirings and third layer metal wirings of a memory cell according to a fifth embodiment. FIG. 10 is a plan view showing an arrangement of vias 3, third layer metal wirings, and fourth layer metal wirings of a memory cell according to a fifth embodiment.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

[Embodiment 1]
(Configuration example of semiconductor device)
FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device 100 according to an embodiment. Referring to FIG. 1, semiconductor device 100 includes a row decoder 102, search drivers 104A, 104B, 106A, 106B, read / write circuits 108, 110, precharge & encode circuits 112A, 112B, and a memory array. Memory cells MC0 # 0 to MC1 # 1 are provided. Here, # 0 to # 1 are address addresses called entries. For example, # 0 indicates an address at address 0, and two BCAM cells, memory cells MC0 # 0 and MC1 # 0, are simultaneously accessed during data read and write operations.

  Note that the configuration of the memory array shown in FIG. 1 is arranged in two columns and two rows for simplicity of explanation, but the configuration of the memory cell to which the technique disclosed in this specification is applied is limited to this configuration. It is not a thing.

  The row decoder 102 activates one of the word lines WL0 and WL1 according to an input address signal (not shown).

  Search driver 104A drives search line SLA0 to a level corresponding to A port search data signal S0 (A), and drives search line / SLA0 to its inverted level. Search driver 104B drives search line SLB0 to a level corresponding to B port search data signal S0 (B), and drives search line / SLB0 to its inverted level. Search driver 106A drives search line SLA1 to a level corresponding to A port search data signal S1 (A), and drives search line / SLA1 to its inverted level. Search driver 106B drives search line SLB1 to a level corresponding to search data signal S1 (B) for the B port, and drives search line / SLB1 to its inverted level.

  In one aspect, read / write circuit 108 amplifies and reads data (potential) read to bit line pair BL0, / BL0 by a sense amplifier (not shown). Thereby, read / write circuit 108 reads data from each memory cell connected to bit line pair BL0, / BL0. In another aspect, read / write circuit 108 drives bit line pair BL0, / BL0 according to input data DIO0 by a write driver (not shown). Thus, read / write circuit 108 writes data to each memory cell connected to bit line pair BL0, / BL0 and whose word line is activated. Similarly to read / write circuit 108, read / write circuit 110 amplifies and reads data read to bit line pair BL1, / BL1 by a sense amplifier (not shown) in one aspect, and in another aspect. The bit line pair BL1, / BL1 is driven according to the input data DIO1 by a write driver (not shown).

  The precharge & encode circuit 112A precharges the match lines MLA0 and MLA1 for the A port and encodes the search results output to the match lines MLA0 and MLA1. The precharge & encode circuit 112B precharges the match lines MLB0 and MLB1 for the B port and encodes the search results output to the match lines MLB0 and MLB1. In one aspect, precharge & encode circuits 112A and 112B precharge the connected match line to “H” level.

  Memory cells MC0 # 0 to MC1 # 1 are each configured to hold 1-bit storage data. The stored data is data to be compared with the search data.

  Each memory cell is connected to one word line, one set of bit line pairs, two sets of search line pairs, and two match lines. For example, memory cell MC0 # 0 is connected to word line WL0, bit line pair BL0 / BL0, search line pairs SLA0, / SLA0 and SLB0, / SLB0, and match lines MLA0 and MLB0.

  Bit line pair BL0, / BL0, search line pair SLA0, / SLA0, and SLB0, / SLB0 are commonly connected to memory cells MC0 # 0 and MC0 # 1 in the first column. Bit line pair BL1, / BL1, search line pair SLA1, / SLA1, and SLB1, / SLB1 are commonly connected to memory cells MC1 # 0 and MC1 # 1 in the second column.

  Word line WL0 and match lines MLA0 and MLB0 are commonly connected to memory cells MC0 # 0 and MC1 # 0 corresponding to the first row (address # 0). Word line WL1 and match lines MLA1 and MLB1 are commonly connected to memory cells MC0 # 1 and MC1 # 1 corresponding to the second row (address # 1).

(Memory cell circuit configuration)
FIG. 2 is a circuit diagram illustrating a configuration example of the memory cell MC0 # 0 according to an embodiment.

  Referring to FIG. 2, memory cell MC0 # 0 includes NMOS (Metal Oxide Semiconductor) transistors NA0 and NA1, which are access transistors, NMOS transistors ND0 and ND1 which are driver transistors, and PMOS transistors P0 and P1. Data cell DC0 capable of holding 1-bit information. In one aspect, the semiconductor device 100 can function as a BCAM (Binary Content Addressable Memory).

  Memory cell MC0 # 0 extends along the row direction perpendicular to the bit line pair BL0, / BL0 extending along the column direction (vertical direction in FIG. 2) and the bit line pair extending. A search line pair SLA0, / SLA0 that extends along the column direction and transmits search data for the A port, and a search line pair SLB0, / SLB0 that transmits search data for the B port. In addition.

  Memory cell MC0 # 0 matches the match lines MLA0 and MLB0 extending in the row direction (the horizontal direction in FIG. 2), the information according to the information held in the data cell and the search data for the A port, as a match line. It includes a logical operation cell LCA0 that outputs to MLA0 and a logical operation cell LCB0 that outputs a result corresponding to the information held in the data cell and the search data for the B port to match line MLB0.

  The NMOS transistor NA0 is connected between the storage node A0 and the bit line BL0, and the word line WL0 is connected to the gate. The NMOS transistor NA1 is connected between the storage node A1 and the bit line / BL0, and the word line WL0 is connected to the gate. The PMOS transistor P0 is connected between the power supply line VDD, which is the power supply potential, and the storage node A0, and the gate is connected to the storage node A1. The NMOS transistor ND0 is connected between the storage node A0 and the power supply line VSS which is the ground potential, and has a gate connected to the storage node A1. The PMOS transistor P1 is connected between the power supply line VDD and the storage node A1, and has a gate connected to the storage node A0. The NMOS transistor ND1 is connected between the storage node A1 and the power supply line VSS, and has a gate connected to the storage node A0.

  The NMOS transistor ND0 and the PMOS transistor P0 constitute an inverter. The NMOS transistor ND1 and the PMOS transistor P1 also constitute an inverter. The output of one inverter is connected to the input of the other inverter. Therefore, the flip-flop formed by NMOS transistors ND0 and ND1 and PMOS transistors P0 and P1 holds 1-bit information.

  Logic operation cell LCA0 includes NMOS transistors NS0, NS1, NS2 and NS3. The logic operation cell LCB0 includes NMOS transistors NS4, NS5, NS6, NS7.

  The NMOS transistors NS0 and NS1 are connected in series between the match line MLA0 and the power supply line VSS at the ground potential, and the search line SLA0 and the storage node A0 are connected to the gates, respectively. NMOS transistors NS2 and NS3 are connected in series between match line MLA0 and power supply line VSS, and search line / SLA0 and storage node A1 are connected to the gates, respectively.

  The NMOS transistors NS4 and NS5 are connected in series between the match line MLB0 and the power supply line VSS, and the search line SLB0 and the storage node A0 are connected to the gates, respectively. NMOS transistors NS6 and NS7 are connected in series between match line MLB0 and power supply line VSS, and search line / SLB0 and storage node A1 are connected to the gates, respectively.

  1 other than the memory cell MC0 # 0 in FIG. 1 are different from the above example in the connected word line, match line, bit line pair and search line pair, but the internal circuit configuration is the memory cell MC0. Since it is the same as # 0, the description will not be repeated.

(Write operation)
Next, the operation for the memory cell at address # 0 will be described with reference to FIGS.

  Row decoder 102 activates word line WL 0 to “H” level and deactivates other word lines (ie, word line WL 1) to “L” level when data is written to address # 0. Read / write circuit 108 drives bit line BL0 to a level corresponding to input data DIO0, and drives bit line / BL0 to its inverted level. Read / write circuit 110 drives bit line BL1 to a level corresponding to input data DIO1, and drives bit line / BL1 to its inverted level. At this time, all search line pairs are set to the “L” level. Each match line does not need to have a specific level, but is preferably set to a precharged “H” level.

  In the example shown in FIG. 2, it is assumed that data (level) held in the storage node A1 is data held in the memory cell MC0 # 0. More specifically, when storage node A1 is “1” (“H” level) and storage node A0 is “0” (“L” level), memory cell MC0 # 0 has data “1”. ”. On the other hand, when the storage node A1 is “0” and the storage node A0 is “1”, the memory cell MC0 # 0 holds the data “0”.

  As an example, when data “1” is written to the memory cell MC0 # 0, the row decoder 102 first activates the word line WL0 to “H” level. Subsequently, read / write circuit 108 activates bit line / BL0 to “H” level and deactivates bit line BL0 to “L” level.

  Semiconductor device 100 can write input data into the memory cell at address # 0 by performing these operations. At the time of reading, the potential difference between the bit lines is amplified by a sense amplifier (not shown), and the data held in each memory cell is read out.

(Search operation)
Next, the operation during data search will be described. At the time of data search, the search data input to each search line pair and the entry data at a plurality of addresses # 0 to # 1 are compared at a time, and whether each entry data and the search data match or not. Are output in one cycle. At this time, all of word lines WL0 and WL1 are set to the “L” level. Bit lines BL0 and BL1 are preferably set to "H" level.

  According to the configuration of the memory cell MC0 # 0 described above, the search data for the A port is “1” (that is, the search line SLA0 is “1” and the search line / SLA0 is “0”). When the data of MC0 # 0 is “0” (storage node A1 is “0” and storage node A0 is “1”), the NMOS transistors NS0 and NS1 are turned on, and the match line MLA0 The potential becomes the ground potential. The search data for the A port is “0” (that is, the search line SLA0 is “0” and the search line / SLA0 is “1”), and the data in the memory cell MC0 # 0 is “1” (storage node A1 Is “1” and the storage node A0 is “0”), the NMOS transistors NS2 and NS3 are turned on, and the potential of the match line MLA0 becomes the ground potential. That is, when the search data for the A port and the data of the memory cell MC0 # 0 do not match, the potential of the match line MLA0 becomes the ground potential.

  On the other hand, when the search data for the A port is “1” and the data of the memory cell MC0 # 0 is “1”, or the search data for the A port is “0” and the memory cell When the data of MC0 # 0 is “0” (that is, when both match), the potential of the precharged match line MLA0 is maintained.

  As described above, unless the data of all the memory cells (memory cells MC0 # 0 and MC1 # 0) connected to the match line MLA0 match the search data for the corresponding A port, the data is stored in the match line MLA0. The charged charge is extracted.

  According to the above, the logic operation cell LCA0 has the first logic unit constituted by the NMOS transistors NS0 and NS1, and the second logic unit constituted by the NMOS transistors NS2 and NS3. The first logic unit drives the match line MLA0 according to the comparison result between the information held in the mask data cell MDC0 and the information transmitted to the search line SLA0. The second logic unit drives the match line MLA0 according to the comparison result between the information held in the data cell DC0 and the information transmitted to the search line / SLA0.

  Since the behavior of match line MLB0 is the same as that of match line MLA0 described above, the description thereof will not be repeated.

  According to the above, the semiconductor device 100 according to an embodiment includes a search line pair for A port, a match line, and a logical operation cell, and a search line pair for B port independent of these, a match line, and A logic operation cell. Thereby, the semiconductor device 100 can simultaneously search the search data for the A port and the search data for the B port during one cycle. Therefore, when there are a plurality of search targets, the semiconductor device 100 can realize a search speed twice as high as that of a single-port search device (BCAM device).

  In addition, the semiconductor device 100 searches for search data for the A port and search data for the B port using a common memory array. Therefore, the semiconductor device 100 can suppress an increase in size of the device.

  The retrieval device generally performs retrieval at a timing according to a clock signal generated by a clock generation circuit (not shown). In this regard, since the conventional search apparatus has only one search port, it is necessary to generate a clock signal twice in order to search two search data. On the other hand, the semiconductor memory device 100 may generate a clock signal once when searching for two search data. Therefore, this semiconductor memory device 100 can suppress power consumption in the clock generation circuit as compared with the conventional case.

(Memory cell layout)
Next, the layout configuration of the memory cell MC0 # 0 will be described by dividing it in the stacking direction as an example with reference to FIGS.

  FIG. 3 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, contact hole CT, and first layer metal wiring of memory cell MC0 # 0 arranged in semiconductor device 100. FIG. In FIG. 3, one of polysilicon PO and diffusion region DF is represented by a reference symbol. In the example shown in FIG. 3, the gate of the transistor is made of polysilicon, but the material of the gate is not limited to polysilicon. In another aspect, a metal may be used as the gate material. At this time, a high-k material (for example, hafnium oxide) having a high dielectric constant (relative dielectric constant) is preferably used for the gate insulating film disposed under the metal gate (metal gate). These conditions are the same in the drawings described below.

  As shown in FIG. 3, polysilicon (PO) constituting the gate of each transistor extends along the row direction, and each of the plurality of wells constituting the memory cell extends along the column direction. . Therefore, the gate and the well extend in directions orthogonal to each other. Each well is formed to be continuous with a corresponding well of a memory cell (memory cell MC0 # 1) adjacent in the column direction.

  In the memory cell MC0 # 0, a P-type conductivity type P well PW0, an N-type conductivity type N well NW0, and a P well PW1 are sequentially formed in a direction (row direction) in which the word line WL0 extends. In the region where the P well PW0 and the N well NW0 are provided, the transistors constituting the data cell DC0 are arranged. More specifically, PMOS transistors P0 and P1 are arranged in N well NW0, and NMOS transistors NA0, NA1, ND0, and ND1 are arranged in P well PW0.

  NMOS transistors NS0 to NS7 for data search are arranged in P well PW1. More specifically, two N-type diffusion layers DF are formed in the P well PW1. Transistors NS0 to NS3 constituting the logic operation cell LCA0 are arranged in one diffusion layer DF, and transistors NS4 to NS7 constituting the logic operation cell LCB0 are arranged in the other diffusion layer DF.

  NMOS transistor NA0 has a source and a drain formed by a pair of N-type diffusion regions FL302 and FL304, and a polysilicon gate arranged therebetween. This gate is electrically connected to the word line WL0 formed in the upper metal wiring layer through the contact hole CT2. N-type diffusion region FL302 is electrically connected to bit line BL0 formed in the upper metal wiring layer through contact hole CT6.

  NMOS transistor ND0 has a source and a drain formed by a pair of N-type diffusion regions FL304 and FL306, and a polysilicon gate disposed therebetween. N-type diffusion region FL306 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT8.

  NMOS transistor ND1 has a source and a drain formed by a pair of N-type diffusion regions FL306 and FL308, and a polysilicon gate disposed therebetween. N-type diffusion region FL306 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT8.

  NMOS transistor NA1 has a source and a drain formed by a pair of N-type diffusion regions FL308 and FL310, and a polysilicon gate arranged therebetween. This gate is electrically connected to a word line WL0 formed in the upper metal wiring layer through a contact hole CT4. N-type diffusion region FL310 is electrically connected to bit line / BL0 formed in the upper metal wiring layer through contact hole CT12.

  PMOS transistor P0 has a source and a drain formed by a pair of P-type diffusion regions FL312 and FL314, and a gate formed of polysilicon arranged therebetween. N-type diffusion region FL304, the gate of NMOS transistor ND1, and P-type diffusion region FL312 are connected to a common first layer metal wiring via contact holes CT8, CT16, and CT18, respectively. They are therefore electrically connected to each other. P-type diffusion region FL314 is electrically connected to power supply line VDD formed in the upper metal wiring layer via contact hole CT20.

  PMOS transistor P1 has a source and a drain formed by a pair of P-type diffusion regions FL314, FL316, and a gate formed of polysilicon arranged therebetween. N-type diffusion region FL308, the gate of NMOS transistor ND0, and P-type diffusion region FL316 are connected to a common first-layer metal wiring through contact holes CT10, CT14, and CT22, respectively. They are therefore electrically connected to each other.

  NMOS transistor NS2 has a source and a drain formed by a pair of N-type diffusion regions FL318 and FL320, and a polysilicon gate arranged therebetween. This gate is electrically connected to search line / SLA0 formed in the upper metal wiring layer through contact hole CT24. N-type diffusion region FL318 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT28.

  NMOS transistor NS3 has a source and a drain formed by a pair of N-type diffusion regions FL320 and FL322, and a polysilicon gate arranged therebetween. N-type diffusion region FL322 is electrically connected to match line MLA0 formed in the upper metal wiring layer through contact hole CT30.

  NMOS transistor NS1 has a source and a drain formed by a pair of N-type diffusion regions FL322 and FL324, and a polysilicon gate disposed therebetween.

  NMOS transistor NS0 has a source and a drain formed by a pair of N-type diffusion regions FL324 and FL326, and a polysilicon gate arranged therebetween. This gate is electrically connected to search line SLA0 formed in the upper metal wiring layer through contact hole CT26. N-type diffusion region FL326 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT32.

  NMOS transistor NS6 has a source and a drain formed by a pair of N-type diffusion regions FL328 and FL330, and a polysilicon gate arranged therebetween. This gate is electrically connected to search line / SLB0 formed in the upper metal wiring layer through contact hole CT40. N-type diffusion region FL328 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT34.

  NMOS transistor NS7 has a source and a drain formed by a pair of N-type diffusion regions FL330 and FL332, and a polysilicon gate arranged therebetween. N-type diffusion region FL332 is electrically connected to match line MLB0 formed in the upper metal wiring layer through contact hole CT36.

  NMOS transistor NS5 has a source and a drain formed by a pair of N-type diffusion regions FL332 and FL334, and a polysilicon gate arranged therebetween.

  NMOS transistor NS4 has a source and a drain formed by a pair of N-type diffusion regions FL334 and FL336, and a polysilicon gate arranged therebetween. This gate is electrically connected to search line SLB0 formed in the upper metal wiring layer through contact hole CT42. N-type diffusion region FL336 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT38.

  The gate of the NMOS transistor ND0, the gate of the PMOS transistor P0, the gate of the NMOS transistor NS3, and the gate of the NMOS transistor NS7 are formed of common polysilicon.

  The gate of the NMOS transistor ND1, the gate of the PMOS transistor P1, the gate of the NMOS transistor NS1, and the gate of the NMOS transistor NS5 are formed of common polysilicon.

  NMOS transistors NA0, ND0, ND1, and NA1 are arranged in a common N-type diffusion layer. PMOS transistors P0 and P1 are arranged in a common P-type diffusion layer.

  Each N-type diffusion region is formed by implanting N-type impurities into the active regions of P wells PW0 and PW1. Each P-type diffusion region is formed by implanting a P-type impurity into the active region of N well NW0.

  As described above, the memory cell configuring the semiconductor device 100 employs a configuration in which the NMOS transistors NS0 to NS7 for data search are arranged in the two N-type diffusion layers DF. Generally, BCAM employs a configuration in which a transistor for data search is arranged in one diffusion layer DF. Therefore, in the memory array constituting the semiconductor device 100, the physical distance between memory cells adjacent in the row direction is slightly longer than that of a general BCAM. Thereby, the semiconductor device 100 can reduce the probability that a multi-bit error will occur. Multi-bit error refers to a phenomenon in which data held in a plurality of cells arranged in the row direction is inverted by cosmic rays such as α rays and neutron rays.

  FIG. 4 is a plan view showing the arrangement of the via 1, the first metal wiring layer, and the second metal wiring layer of the memory cell MC0 # 0 arranged in the semiconductor device 100. FIG. The via 1 connects the first layer metal wiring and the second layer metal wiring. In FIG. 4, second-layer metal wirings M202 to M224 are arranged along the column direction.

  The gate of the NMOS transistor NA0 and the gate of the NMOS transistor NA1 are connected to different first layer metal wirings through contact holes CT2 and CT4, respectively. These first layer metal wirings are connected to a common second layer metal wiring M202 that forms the word line WL0 through vias 1V102 and V104, respectively.

  N-type diffusion region FL306 forming the sources of NMOS transistors ND0 and ND1 is connected to the first layer metal wiring through contact hole CT8. This first layer metal wiring is connected to a second layer metal wiring M204 that forms a power supply line VSS through a via 1V106.

  N-type diffusion region FL302 forming the source of NMOS transistor NA0 is connected to the first layer metal wiring through contact hole CT6. This first layer metal wiring is connected to second layer metal wiring M206 forming bit line BL0 through via 1V108.

  N-type diffusion region FL310 forming the source of NMOS transistor NA1 is connected to the first layer metal wiring through contact hole CT10. This first layer metal interconnection is connected to second layer metal interconnection M208 forming bit line / BL0 through via 1V110.

  P-type diffusion region FL314 forming the sources of PMOS transistors P0 and P1 is connected to the first layer metal wiring through contact hole CT20. This first-layer metal wiring is connected to a second-layer metal wiring M210 that forms a power supply line VDD through a via 1V112.

  The gate of the NMOS transistor NS0 is connected to the first layer metal wiring through the contact hole CT26. This first layer metal interconnection is connected to second layer metal interconnection M212 forming search line SLA0 through via 1V114.

  N-type diffusion region FL322 forming the sources of NMOS transistors NS1 and NS3 is connected to the first layer metal wiring through contact hole CT30. This first layer metal interconnection is connected to second layer metal interconnection M214 forming match line MLA0 through via 1V116.

  The gate of the NMOS transistor NS2 is connected to the first layer metal wiring through the contact hole CT24. This first layer metal interconnection is connected to second layer metal interconnection M216 forming search line / SLA0 through via 1V118.

  N-type diffusion regions FL318 and FL328 forming the sources of NMOS transistors NS2 and NS6, respectively, are connected to a common first layer metal interconnection via contact holes CT28 and CT34, respectively. The first layer metal wiring is connected to the second layer metal wiring M218 forming the power supply line VSS through the via 1V120.

  The N-type diffusion region FL326 that forms the source of the NMOS transistor NS0 and the N-type diffusion region FL336 that forms the source of the NMOS transistor NS4 are connected to a common first-layer metal wiring via contact holes CT32 and CT38, respectively. Is done. This first layer metal wiring is connected to second layer metal wiring M218 via via 1V122.

  The gate of the NMOS transistor NS4 is connected to the first layer metal wiring through the contact hole CT42. This first layer metal interconnection is connected to second layer metal interconnection M220 forming search line SLB0 through via 1V124.

  N-type diffusion region FL332 forming the sources of NMOS transistors NS5 and NS7 is connected to the first layer metal wiring through contact hole CT36. This first layer metal wiring is connected to second layer metal wiring M222 forming match line MLB0 through via 1V1126.

  The gate of the NMOS transistor NS6 is connected to the first layer metal wiring through the contact hole CT40. This first layer metal interconnection is connected to second layer metal interconnection M224 forming search line / SLB0 through via 1V128.

  FIG. 5 is a plan view showing the arrangement of via 2, second metal wiring layer, and third metal wiring layer of memory cell MC0 # 0 arranged in semiconductor device 100. FIG. The via 2 connects the second layer metal wiring and the third layer metal wiring. In FIG. 5, third layer metal interconnections M310-M350 are arranged along the row direction.

  Second-layer metal interconnection M204 is connected to third-layer metal interconnections M310 and M350 forming power supply line VSS via via 2V220 and via 2V230. Second layer metal interconnection 218 is connected to third layer metal interconnections M310 and M350 through via 2V250 and via 2V260.

  Second-layer metal interconnection M222 is connected to third-layer metal interconnection M320 forming match line MLB0 through via 2V270.

  Second layer metal interconnection M202 is connected to third layer metal interconnection M330 forming word line WL0 through via 2V210.

  Second-layer metal interconnection M214 is connected to third-layer metal interconnection M340 forming match line MLA0 through via 2V240.

  Note that the wiring pattern of the metal wiring inside the memory cell MC0 # 1 adjacent to the memory cell MC0 # 0 in the column direction is the same as the wiring pattern in which the wiring pattern of the memory cell MC0 # 0 is targeted in the row direction. The description will not be repeated. Note that the wiring pattern of the metal wiring inside the memory cell MC1 # 0 adjacent to the memory cell MC0 # 0 in the row direction is the same as the wiring pattern in which the wiring pattern of the memory cell MC0 # 0 is targeted in the column direction. Alternatively, the wiring pattern of the memory cell MC0 # 0 may be the same.

  By configuring the layout as described above, a highly integrated CAM memory array can be realized up to the third metal wiring layer. If the number of wiring layers can be reduced, manufacturing costs can be reduced.

(Modification)
In the above embodiment, the transistors for data search are NMOS transistors (NS01 to NS07). In another aspect, the semiconductor device may include a PMOS transistor as a data search transistor.

  FIG. 6 is a circuit diagram illustrating a configuration example of the memory cell MC0 # 0 according to another embodiment. Note that the portions denoted by the same reference numerals as those in FIG. 2 are the same, and therefore the description thereof will not be repeated.

  A logic operation cell LCA0 according to another embodiment includes PMOS transistors PS0, PS1, PS2, and PS3 in place of the NMOS transistors NS0, NS1, NS2, and NS3. A logic operation cell LCB0 according to another embodiment includes PMOS transistors PS4, PS5, PS6 and PS7 in place of the NMOS transistors NS4, NS5, NS6 and NS7.

  The PMOS transistors PS0 and PS1 are connected in series between the match line MLA0 and the power supply line VDD, and the search line SLA0 and the storage node A0 are connected to the gates, respectively. PMOS transistors PS2 and PS3 are connected in series between match line MLA0 and power supply line VDD, and search line / SLA0 and storage node A1 are connected to the gates, respectively.

  PMOS transistors PS4 and PS5 are connected in series between match line MLB0 and power supply line VDD, and search line SLB0 and storage node A0 are connected to the gates, respectively. PMOS transistors PS6 and PS7 are connected in series between match line MLB0 and power supply line VDD, and search line / SLB0 and storage node A1 are connected to the gates, respectively.

  The data of the memory cell MC0 # 0 shown in FIG. 2 holds data “0” when the storage node A1 is at “L” level, and holds data “1” when the storage node A1 is at “H” level. It was the composition to do. In one aspect, data in memory cell MC0 # 0 shown in FIG. 6 holds data “0” when storage node A0 is at “L” level and data “0” when storage node A0 is at “H” level. Hold 1 ″.

  FIG. 7 is a block diagram illustrating a configuration example of a semiconductor device 700 according to another embodiment. Note that the same reference numerals as those in FIG. 1 denote the same parts, and therefore the description thereof will not be repeated.

  As shown in FIG. 6, the memory cells MC0 # 0 to MC1 # 1 arranged in the semiconductor device 700 have PMOS transistors as data search transistors.

  An inverter Inv is provided at each output terminal of the search drivers 104A, 104B, 106A, 106B included in the semiconductor device 700. Thereby, the level of each search line becomes the inversion level of the signal output by the connected search driver.

  Further, an inverter Inv is provided at input terminals of the precharge & encode circuits 112A and 112B included in the semiconductor device 700. As a result, the precharge & encode circuits 112A and 112B accept input of signals at the inversion level of the connected match lines. These inverters Inv invert the output levels of the precharge & encode circuits 112A and 112B to precharge the match lines. In one aspect, each match line is precharged to “L” level.

  A search operation of the semiconductor device 700 will be described with reference to FIGS. 6 and 7. When the data of memory cell MC0 # 0 (the level of storage node A0) matches the search data, the level of the match line is maintained at the precharged “L” level. On the other hand, when the data of memory cell MC0 # 0 and the search data do not match, the level of the match line becomes “H” level.

  As an example, a case where the search data signal S0 (A) is “1” will be described. In this case, the level of the search line SLA0 becomes the “L” level inverted by the inverter Inv. Therefore, the PMOS transistor PS0 connected to the search line SLA0 is turned on. In the above case, when the data of the memory cell MC0 # 0 is “0”, that is, when the data of the memory cell MC0 # 0 and the search data do not match, the PMOS transistor PS1 is turned on and the match line MLA0 is set to “H”. Level. On the other hand, when the data in the memory cell MC0 # 0 is “1”, that is, when the data in the memory cell MC0 # 0 matches the search data, the PMOS transistor PS1 is turned off and the match line MLA0 is precharged. Maintained at “L” level.

  According to the above, the match line MLA0 for the A port maintains the “L” level when the data held in the memory cell corresponding to the address # 0 matches all the search data for the A port. If there is even one that does not match, it becomes “H” level. Precharge & encode circuit 112A accepts an input of “H” level when the data held in the memory cell corresponding to address # 0 matches all the search data for the A port by the action of inverter Inv. If there is even one that does not match, an “L” level input is accepted. The same applies to the precharge & encode circuit 112A included in the semiconductor device 100 described above. Similarly, the behavior of the precharge & encode circuit 112B included in the semiconductor device 700 and the behavior of the precharge & encode circuit 112B included in the semiconductor device 100 are the same.

  Therefore, the semiconductor device 700 can use a memory cell having a PMOS transistor as a transistor for data search only by providing an inverter at each output terminal of the search driver and each input terminal of the precharge & encode circuit.

  In one aspect, a silicon germanium layer can be formed in the source and drain regions of the PMOS transistors PS0 to PS7. Thereby, stress is applied to the silicon of the adjacent channel portion, and the lattice constant of the silicon can be increased. As a result, the speed of the current flowing through the channel portion is increased, and the switching speed of the PMOS transistors PS0 to PS7 can be improved. In another aspect, the layers formed in the source and drain regions of the PMOS transistors PS0 to PS7 are not limited to the silicon germanium layer, and may be any layer that applies stress to the silicon in the channel portion.

  FIG. 8 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, contact hole CT, and first layer metal wiring of memory cell MC0 # 0 according to another embodiment. In addition, since it is the same about the part which attached | subjected the code | symbol same as the code | symbol of FIG. 3, description about the part is not repeated.

  As shown in FIG. 8, the well configuration of memory cell MC0 # 0 according to another embodiment is different from the well configuration of memory cell MC0 # 0 described in FIG. 3 in that it does not have P well PW1.

  The PMOS transistors PS0 to PS7 for data search are arranged in the N well NW0. More specifically, three diffusion layers DF extending in the column direction are formed in the N well NW0. In a certain diffusion layer DF, PMOS transistors P0 and P1 constituting the data cell DC0 are arranged. In a certain diffusion layer DF, PMOS transistors PS0 to PS3 constituting the logic operation cell LCA0 are arranged. In a certain diffusion layer DF, PMOS transistors PS4 to PS7 constituting the logic operation cell LCB0 are arranged.

  PMOS transistor PS2 has a source and a drain formed by a pair of P-type diffusion regions FL340 and 342, and a polysilicon gate disposed therebetween. This gate is connected to first layer metal wiring forming search line / SLA0 through contact hole CT44. P-type diffusion region FL340 is connected to first layer metal wiring forming power supply line VDD through contact hole CT48.

  PMOS transistor PS3 has a source and a drain formed by a pair of P-type diffusion regions FL342 and 344, and a polysilicon gate disposed therebetween. P type diffusion region FL344 is connected to a first layer metal interconnection forming match line MLA0 through contact hole CT50.

  PMOS transistor PS1 has a source and a drain formed by a pair of P-type diffusion regions FL344 and 346, and a polysilicon gate arranged therebetween.

  PMOS transistor PS0 has a source and a drain formed by a pair of P-type diffusion regions FL346 and 348, and a polysilicon gate arranged therebetween. This gate is connected to a first layer metal wiring forming search line SLA0 through contact hole CT46. P-type diffusion region FL348 is connected to a first layer metal wiring forming power supply line VDD through contact hole CT52.

  PMOS transistor PS6 has a source and a drain formed by a pair of P-type diffusion regions FL350 and 352, and a polysilicon gate arranged therebetween. This gate is connected to first layer metal wiring forming search line / SLB0 through contact hole CT60. P type diffusion region FL350 is connected to first layer metal wiring forming power supply line VDD through contact hole CT54.

  PMOS transistor PS7 has a source and a drain formed by a pair of P-type diffusion regions FL352 and 354, and a polysilicon gate arranged therebetween. P type diffusion region FL354 is connected to first layer metal wiring forming first layer metal wiring forming match line MLB0 through contact hole CT56.

  PMOS transistor PS5 has a source and a drain formed by a pair of P-type diffusion regions FL354 and 356, and a polysilicon gate arranged therebetween.

  PMOS transistor PS4 has a source and a drain formed by a pair of P-type diffusion regions FL356, 358, and a polysilicon gate disposed therebetween. This gate is connected to the first layer metal wiring forming search line SLB0 through contact hole CT62. P type diffusion region FL358 is connected to first layer metal wiring forming power supply line VDD through contact hole CT58.

  The gate of the NMOS transistor ND0, the gate of the PMOS transistor P0, the gate of the PMOS transistor PS3, and the gate of the PMOS transistor PS7 are formed of common polysilicon.

  The gate of the NMOS transistor ND1, the gate of the PMOS transistor P1, the gate of the PMOS transistor PS1, and the gate of the PMOS transistor PS5 are formed of common polysilicon.

  Since the memory cell constituting the semiconductor device 700 does not have the P well PW1, the number of wells is one less than that of the memory cell constituting the semiconductor device 100. Therefore, the memory cell included in the semiconductor device 700 can be made smaller than the memory cell included in the semiconductor device 100.

  FIG. 9 is a plan view showing the arrangement of via 1, first metal wiring layer, and second metal wiring layer of memory cell MC0 # 0 according to another embodiment. Note that the portions denoted by the same reference numerals as those in FIG. 4 are the same, and therefore description thereof will not be repeated.

  The metal wiring pattern in the second layer of memory cell MC0 # 0 according to another embodiment is different from the metal wiring pattern shown in FIG. 4 in that it has second-layer metal wiring M910 instead of second-layer metal wiring M218. .

  The P-type diffusion region FL340 that forms the source of the PMOS transistor PS2 and the P-type diffusion region FL350 that forms the source of the PMOS transistor PS6 are connected to a common first layer metal wiring via contact holes CT48 and CT54, respectively. The This first layer metal wiring is connected to a second layer metal wiring M910 that forms a power supply line VDD through a via 1V121.

  The P-type diffusion region FL348 forming the source of the PMOS transistor PS2 and the P-type diffusion region FL358 forming the source of the PMOS transistor PS6 are connected to the common first layer metal wiring via the contact holes CT52 and CT58, respectively. The This first-layer metal wiring is connected to a second-layer metal wiring M910 that forms a power supply line VDD through a via 1V123.

[Embodiment 2]
The semiconductor device shown in the above embodiment can function as a 2-port BCAM device. More specifically, the semiconductor device shown in the above embodiment has a configuration in which a search line pair, a match line, and a logic operation cell are arranged for each port in a BCAM cell that holds binary data. . A semiconductor device that can function as a 2-port TCAM (Ternary Content Addressable Memory) device will be described below.

(Configuration example of semiconductor device)
FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device 1000 according to an embodiment. Note that the same reference numerals as those in FIG. 1 denote the same parts, and therefore the description thereof will not be repeated.

  Referring to FIG. 10, semiconductor device 1000 is different from semiconductor device 100 described in FIG. 1 in that there are two pairs of bit lines connected to each memory cell.

  More specifically, memory cells MC0 # 0 and MC0 # 1 arranged in the column direction are connected to a common bit line pair BL0, / BL0 and BL1, / BL1. Memory cells MC1 # 0 and MC1 # 1 are connected to a common bit line pair BL2, / BL2 and BL3, / BL3.

(Memory cell circuit configuration)
FIG. 11 is a circuit diagram illustrating a configuration example of the memory cell MC0 # 0 arranged in the semiconductor device 1000.

  Referring to FIG. 11, memory cell MC0 # 0 arranged in semiconductor device 1000 has a data cell DC0 configured to hold 1-bit stored data and 1-bit information held by data cell DC0. And a mask data cell MDC0 configured to be able to hold other independent 1-bit data. Data cell DC0 and mask data cell MDC0 are adjacent to each other in the row direction.

  Memory cell MC0 # 0 further includes a pair of bit lines BL0, / BL0 extending along the column direction, and BLA1, / BL1.

  The mask data cell MDC0 is configured by NMOS transistors NA0, NA1, ND0, ND1 and PMOS transistors P0, P1.

  The NMOS transistor NA0 is connected between the storage node m1 and the bit line BL0, and the word line WL0 is connected to the gate. The NMOS transistor NA1 is connected between the storage node / m1 and the bit line / BL0, and the word line WL0 is connected to the gate. PMOS transistor P0 is connected between power supply line VDD and storage node m1, and has its gate connected to storage node / m1. The NMOS transistor ND0 is connected between the storage node m1 and the power supply line VSS, and has a gate connected to the storage node / m1. PMOS transistor P1 is connected between power supply line VDD and storage node / m1, and has its gate connected to storage node m1. The NMOS transistor ND1 is connected between the storage node / m1 and the power supply line VSS, and has a gate connected to the storage node m1.

  The NMOS transistor ND0 and the PMOS transistor P0 constitute an inverter. The NMOS transistor ND1 and the PMOS transistor P1 also constitute an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed of NMOS transistors ND0 and ND1 and PMOS transistors P0 and P1 holds 1-bit information.

  The data cell DC0 includes NMOS transistors NA2 and NA3 that are access transistors, NMOS transistors ND2 and ND3 that are driver transistors, and PMOS transistors P2 and P3.

  The NMOS transistor NA2 is connected between the storage node m0 and the bit line BL1, and the word line WL0 is connected to the gate. The NMOS transistor NA3 is connected between the storage node / m0 and the bit line / BL1, and the gate is connected to the word line WL0. PMOS transistor P2 is connected between power supply line VDD and storage node m0, and has its gate connected to storage node / m0. NMOS transistor ND2 is connected between storage node m0 and power supply line VSS, and has its gate connected to storage node / m0. PMOS transistor P3 is connected between power supply line VDD and storage node / m0, and has its gate connected to storage node m0. NMOS transistor ND3 is connected between storage node / m0 and power supply line VSS, and has its gate connected to storage node m0.

  The NMOS transistor ND2 and the PMOS transistor P2 constitute an inverter. The NMOS transistor ND3 and the PMOS transistor P3 also constitute an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop constituted by NMOS transistors ND2 and ND3 and PMOS transistors P2 and P3 holds 1-bit information (stored data).

  Memory cell MC0 # 0 is arranged adjacent to both data cell DC0 and mask data cell MDC0 in the column direction, and adjacent to logical operation cell LCB0 in the column direction. A logic operation cell LCA0.

  The logical operation cell LCA0 outputs a result corresponding to the data held in the data cell DC0 and the mask data cell MDC0 and the search data for the A port to the match line MLA0. More specifically, the logical operation cell LCA0 determines whether or not the data in the data cell DC (level of the storage node m1) matches the search data for the A port, and the data in the mask data cell MDC (storage node m0). The match line MLA0 is driven according to whether or not the inversion level of the search data for the A port matches. The logical operation cell LCB0 outputs a result corresponding to the data held in the data cell DC0 and the mask data cell MDC0 and the search data for the B port to the match line MLA0. More specifically, the logical operation cell LCB0 determines whether or not the data in the data cell DC matches the search data for the B port, and the inversion level of the data in the mask data cell MDC and the search data for the B port. The match line MLB0 is driven according to whether or not the two match.

  The logical operation cell LCA0 includes NMOS transistors NS0 to NS3. The logical operation cell LCB0 includes NMOS transistors NS4 to NS7.

  The NMOS transistors NS0 and NS1 are connected in series between the match line MLA0 and the power supply line VSS, and the search line SLA0 and the storage node m1 are connected to the gates, respectively. NMOS transistors NS2 and NS3 are connected in series between match line MLA0 and power supply line VSS, and search line / SLA0 and storage node m0 are connected to the gates, respectively.

  The NMOS transistors NS4 and NS5 are connected in series between the match line MLB0 and the power supply line VSS, and the search line SLB0 and the storage node m1 are connected to the gates, respectively. NMOS transistors NS6 and NS7 are connected in series between match line MLB0 and power supply line VSS, and search line / SLB0 and storage node m0 are connected to the gates, respectively.

  Note that other memory cells other than the memory cell MC0 # 0 in FIG. 10 are different from the above example in the connected word line, match line, bit line pair and search line pair, but the internal circuit configuration is the memory cell MC0. Since it is the same as # 0, the description will not be repeated.

(Memory cell data)
FIG. 12 is a diagram showing the correspondence relationship between the data held in data cell DC0 and mask data cell MDC0 in FIG. 11 and the data in memory cell MC0 # 0 in a tabular form.

  Referring to FIGS. 11 and 12, memory cell MC0 # 0 uses 2-bit SRAM cells (data cell DC and mask data cell MDC), and is “0”, “1”, “*” (don't care: Don't care) can be stored. Don't care “*” indicates that either “0” or “1” may be used.

  Specifically, when “0” (“L” level) is stored in the storage node m0 of the data cell DC0 and “1” (“H” level) is stored in the storage node m1 of the mask data cell MDC0, It is assumed that “0” is stored in the memory cell MC0 # 0. When “1” is stored in the storage node m0 of the data cell DC0 and “0” is stored in the storage node m1 of the mask data cell MDC0, “1” is stored in the memory cell MC0 # 0. To do. When “0” is stored in the storage node m0 of the data cell DC0 and “0” is stored in the storage node m1 of the mask data cell MDC0, “*” (don't care) is stored in the memory cell MC0 # 0. Suppose that This is not used when “1” is stored in the storage node m0 of the data cell DC0 and “1” is stored in the storage node m1 of the mask data cell MDC0.

(Write operation)
Referring to FIG. 11 again, the write operation for memory cell MC0 # 0 will be described. Row decoder 102 activates word line WL0 to “H” level and deactivates other word lines (ie, word line WL1) to “L” level during data writing to memory cell MC0 # 0. . Read / write circuit 108 drives bit lines BL0 and BL1 to a level corresponding to input data DIO0, and drives bit lines / BL0 and / BL1 to their inversion levels. At this time, all search line pairs are set to the “L” level. Each match line does not need to have a specific level, but is preferably set to a precharged “H” level.

  As an example, when the input data DIO0 is “1”, the read / write circuit 108 sets the bit line BL1 to “H” level, the bit line / BL1 to “L” level, and the bit line BL0 to “L”. The bit line / BL0 is driven to the “H” level.

  The semiconductor device 1000 can write input data to each memory cell by performing these operations. At the time of reading, the potential difference between the bit lines is amplified by a sense amplifier (not shown), and the data held in each memory cell is read out.

  In a memory cell arranged in the semiconductor device 1000, a bit line pair to which a data cell is connected is different from a bit line pair to which a mask data cell is connected. Therefore, in one aspect, the semiconductor device 1000 writes or reads data to or from a mask data cell that forms a memory cell while writing or reading data to or from the data cell that forms the memory cell. Reading can be performed.

(Search operation)
Next, the search operation will be described. According to the configuration of the memory cell MC0 # 0 described above, the search data for the A port is “1” (that is, the search line SLA0 is “1” and the search line / SLA0 is “0”). When the data of MC0 # 0 is “0” (the storage node m0 is “0” and the storage node m1 is “1”), the NMOS transistors NS0 and NS1 are turned on, and the match line MLA0 The potential becomes the ground potential. The search data for the A port is “0” (that is, the search line SLA0 is “0” and the search line / SLA0 is “1”), and the data in the memory cell MC0 # 0 is “1” (storage node m0). Is “1” and the storage node m1 is “0”), the NMOS transistors NS2 and NS3 are turned on, and the potential of the match line MLA0 becomes the ground potential. That is, when the search data for the A port and the data of the memory cell MC0 # 0 do not match, the potential of the match line MLA0 becomes the ground potential (“L” level).

  On the other hand, when the search data for the A port is “1” and the data of the memory cell MC0 # 0 is “1” or “*”, or the search data for the A port is “0”. In addition, when the data in the memory cell MC0 # 0 is “0” or “*” (that is, when both match), the potential (“H” level) of the precharged match line MLA0 is maintained.

  As described above, unless the data of all the memory cells (memory cells MC0 # 0 and MC1 # 0) connected to the match line MLA0 match the search data for the corresponding A port, the data is stored in the match line MLA0. The charged charge is extracted.

  Since the behavior of match line MLB0 is the same as that of match line MLA0 described above, the description thereof will not be repeated.

  Based on the above, the semiconductor device 1000 functioning as a TCAM device can simultaneously search the search data for the A port and the search data for the B port during one cycle. Therefore, when there are a plurality of search targets, the semiconductor device 1000 can realize a search speed twice as high as that of a single-port search device (TCAM device).

  In addition, the semiconductor device 1000 searches for search data for the A port and search data for the B port using a common memory array. Therefore, the semiconductor device 1000 can suppress an increase in size of the device.

  Further, the conventional TCAM device needs to generate a clock signal twice in order to search for two search data. On the other hand, the semiconductor device 1000 may generate a clock signal once when searching for two search data. Therefore, this semiconductor device 1000 can suppress power consumption as compared with the prior art.

(Memory cell layout)
Next, as an example, a layout configuration of the memory cell MC0 # 0 arranged in the semiconductor device 1000 will be described by dividing it in the stacking direction with reference to FIGS. In addition, since it is the same about the part which has attached | subjected the code | symbol same as the code | symbol of FIGS. 3-5, description about the part is not repeated.

  FIG. 13 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, contact hole CT, and first layer metal wiring of memory cell MC0 # 0 arranged in semiconductor device 1000. FIG.

  As shown in FIG. 13, polysilicon (PO) constituting the gate of each transistor extends along the row direction, and each of the plurality of wells constituting the memory cell extends along the column direction. . Therefore, the gate and the well extend in directions orthogonal to each other. Each well is formed to be continuous with a corresponding well of a memory cell (memory cell MC0 # 1) adjacent in the column direction.

  In memory cell MC0 # 0 according to an embodiment, P-type conductivity type P well PW0, N-type conductivity type N well NW0, P well PW1, and N well are arranged in the direction (row direction) in which word line WL0 extends. NW1 and P well PW2 are formed in order. In a region where the N well NW1 and the P well PW2 are provided, NMOS transistors NA2, NA3, ND2, ND3 and PMOS transistors P2, P3 constituting the data cell DC0 are arranged. More specifically, PMOS transistors P2 and P3 are arranged in N well NW1, and NMOS transistors NA2, NA3, ND2 and ND3 are arranged in P well PW2.

  PMOS transistor P3 has a source and a drain formed by a pair of P-type diffusion regions FLFL360 and FL362, and a polysilicon gate arranged therebetween. P type diffusion region FL362 is connected to power supply line VDD formed in the upper metal wiring layer through contact hole CT66.

  The PMOS transistor P2 has a source and a drain formed by a pair of P-type diffusion regions FL362 and FL364, and a polysilicon gate disposed therebetween.

  NMOS transistor NA3 has a source and a drain formed by a pair of N-type diffusion regions FL366 and FL368, and a polysilicon gate arranged therebetween. This gate is electrically connected to word line WL0 formed in the upper metal wiring layer through contact hole CT84. N-type diffusion region FL366 is electrically connected to bit line / BL1 formed in the upper metal wiring layer through contact hole CT74.

  NMOS transistor ND3 has a source and a drain formed by a pair of N-type diffusion regions FL368 and FL370, and a polysilicon gate arranged therebetween. N-type diffusion region FL370 is connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT78.

  NMOS transistor ND2 has a source and a drain formed by a pair of N-type diffusion regions FL370 and FL372, and a polysilicon gate arranged therebetween. P type diffusion region FL360, N type diffusion region FL368, and the gate of NMOS transistor ND2 are connected to a common first layer metal wiring through contact holes CT64, CT76, 72, respectively. They are therefore electrically connected to each other. P-type diffusion region FL364, the gate of PMOS transistor P3, and N-type diffusion region FL372 are connected to a common first-layer metal wiring via contact holes CT68, CT70, and 80, respectively. They are therefore electrically connected to each other.

  NMOS transistor NA2 has a source and a drain formed by a pair of N-type diffusion regions FL372 and FL374, and a polysilicon gate arranged therebetween. This gate is electrically connected to word line WL0 formed in the upper metal wiring layer through contact hole CT86. N-type diffusion region FL374 is electrically connected to bit line BL1 formed in the upper metal wiring layer through contact hole CT82.

  The gate of the NMOS transistor NS3, the gate of the NMOS transistor NS7, the gate of the PMOS transistor P3, and the gate of the NMOS transistor ND3 are formed of common polysilicon.

  The gate of the PMOS transistor P2 and the gate of the NMOS transistor ND2 are formed of common polysilicon.

  NMOS transistors NA0, ND0, ND1, and NA1 are arranged in a common N-type diffusion layer. PMOS transistors P0 and P1 are arranged in a common P-type diffusion layer. PMOS transistors P3 and P2 are arranged in a common P-type diffusion layer. NMOS transistors NA3, ND3, ND2, and NA2 are arranged in a common N-type diffusion layer.

  As shown in FIG. 13, the memory cell constituting the semiconductor device 1000 employs a configuration in which NMOS transistors NS0 to NS7 for data search are arranged in two N-type diffusion layers DF. Generally, a TCAM device employs a configuration in which transistors for data search are arranged in one diffusion layer DF. Therefore, in the memory array constituting the semiconductor device 1000, the physical distance between memory cells adjacent in the row direction is slightly longer than that of a general TCAM device. Thereby, the semiconductor device 1000 can reduce the probability that a multi-bit error will occur.

  FIG. 14 is a plan view showing the arrangement of the via 1, the first metal wiring layer, and the second metal wiring layer of the memory cell MC0 # 0 arranged in the semiconductor device 1000. FIG. In FIG. 14, second layer metal wirings M202 to M248 are arranged along the column direction.

  P-type diffusion region FL362 forming the sources of PMOS transistors P3 and P2 is connected to the first-layer metal wiring through contact hole CT66. This first layer metal wiring is connected to the second layer metal wiring M240 forming the power supply line VDD via the via 1V130.

  N-type diffusion region FL374 forming the source of NMOS transistor NA2 is connected to the first layer metal wiring through contact hole CT82. This first layer metal wiring is connected to a second layer metal wiring M242 forming bit line BL1 through via 1V132.

  The N type diffusion region FL366 that forms the source of the NMOS transistor NA3 is connected to the first layer metal wiring through the contact hole CT74. This first layer metal interconnection is connected to second layer metal interconnection M244 forming bit line / BL1 through via 1V134.

  N-type diffusion region FL370 forming the sources of NMOS transistors ND3 and ND2 is connected to the first layer metal interconnection through contact hole CT78. This first-layer metal wiring is connected to a second-layer metal wiring M246 that forms a power supply line VSS through a via 1V136.

  The gate of the NMOS transistor NA3 and the gate of the NMOS transistor NA2 are connected to different first layer metal wirings through contact holes CT84 and CT86, respectively. These first layer metal wirings are connected to a common second layer metal wiring M248 forming the word line WL0 through vias 1V138 and 1V140, respectively.

  FIG. 15 is a plan view showing the arrangement of the via 2, the second metal wiring layer, and the third metal wiring layer of the memory cell MC0 # 0 arranged in the semiconductor device 1000. FIG.

  Second layer metal interconnection M246 is connected to third layer metal interconnections M310 and M350 forming power supply line VSS via vias 2V275 and V280.

  Second-layer metal interconnection M248 is connected to third-layer metal interconnection M330 that forms word line WL0 through via 2V285.

  By configuring the layout as described above, a highly integrated TCAM memory array can be realized up to the third metal wiring layer. If the number of wiring layers can be reduced, manufacturing costs can be reduced.

  FIG. 16 is a diagram illustrating a metal wiring pattern in a memory cell according to an embodiment. In the figure, “F” represents the direction of the metal wiring pattern. As an example, the direction of the metal wiring pattern in the memory cell MC0 # 0 described with reference to FIGS.

  In this case, the metal wiring pattern of the memory cell MC0 # 1 adjacent to the memory cell MC0 # 0 in the column direction is a wiring pattern in which the wiring pattern of the memory cell MC0 # 0 is an axis target in the row direction.

  On the other hand, the metal wiring pattern of memory cell MC1 # 0 adjacent to memory cell MC0 # 0 in the row direction is the same wiring pattern as that of memory cell MC0 # 0 in the example shown in FIG. In another aspect, the metal wiring pattern of memory cell MC1 # 0 may be a wiring pattern in which the wiring pattern of memory cell MC0 # 0 is targeted in the column direction.

(Modification)
In the semiconductor device 1000 as the TCAM device described above, the transistors for data search are NMOS transistors (NS01 to NS07). Hereinafter, a TCAM device using a PMOS transistor as a transistor for data search will be described.

  FIG. 17 is a circuit diagram illustrating a configuration example of a memory cell MC0 # 0 as a TCAM cell according to another embodiment. In addition, since it is the same about the part which attached | subjected the code | symbol same as the code | symbol of FIG. 11, description about the part is not repeated.

  A logic operation cell LCA0 according to another embodiment includes PMOS transistors PS0, PS1, PS2, and PS3 in place of the NMOS transistors NS0, NS1, NS2, and NS3. A logic operation cell LCB0 according to another embodiment includes PMOS transistors PS4, PS5, PS6 and PS7 in place of the NMOS transistors NS4, NS5, NS6 and NS7.

  PMOS transistors PS0 and PS1 are connected in series between match line MLA0 and power supply line VDD, and search line SLA0 and storage node m1 are connected to the gates, respectively. PMOS transistors PS2 and PS3 are connected in series between match line MLA0 and power supply line VDD, and search line / SLA0 and storage node m0 are connected to the gates, respectively.

  PMOS transistors PS4 and PS5 are connected in series between match line MLB0 and power supply line VDD, and search line SLB0 and storage node m1 are connected to the gates, respectively. PMOS transistors PS6 and PS7 are connected in series between match line MLB0 and power supply line VDD, and search line / SLB0 and storage node m0 are connected to the gates, respectively.

  The relationship between the data in the memory cell MC0 # 0 arranged in the semiconductor device 1000 and the data held in the data cell DC0 and the mask data cell MDC0 is shown in FIG. In one aspect, the relationship between the data in memory cell MC0 # 0 shown in FIG. 17 and the data held in data cell DC0 and mask data cell MDC0 is different from the relationship shown in FIG.

  FIG. 18 is a table showing the correspondence between the data held in data cell DC0 and mask data cell MDC0 in FIG. 17 and the data in memory cell MC0 # 0 in tabular form.

  Referring to FIG. 18, when “1” is stored in storage node m0 of data cell DC0 and “0” is stored in storage node m1 of mask data cell MDC0, “0” is stored in memory cell MC0 # 0. "Is stored. When “0” is stored in the storage node m0 of the data cell DC0 and “1” is stored in the storage node m1 of the mask data cell MDC0, “1” is stored in the memory cell MC0 # 0. To do. When “1” is stored in the storage node m0 of the data cell DC0 and “1” is stored in the storage node m1 of the mask data cell MDC0, “*” (don't care) is stored in the memory cell MC0 # 0. Suppose that This is not used when “0” is stored in the storage node m0 of the data cell DC0 and “0” is stored in the storage node m1 of the mask data cell MDC0. As described above, a TCAM cell (memory cell MC0 # 0) that employs a PMOS transistor as a data search transistor holds data in a manner opposite to that of a TCAM cell that employs an NMOS transistor (FIG. 12). Can do.

  FIG. 19 is a block diagram illustrating a configuration example of a semiconductor device 1900 according to another embodiment. In addition, since it is the same about the part which attached | subjected the code | symbol same as the code | symbol of FIG. 10, description about the part is not repeated.

  As shown in FIG. 17, the memory cells MC0 # 0 to MC1 # 1 arranged in the semiconductor device 1900 have PMOS transistors as data search transistors.

  Similar to the semiconductor device 700 described with reference to FIG. 7, the semiconductor device 1900 includes inverters Inv at the output terminals of the search drivers 104A, 104B, 106A, and 106B and the input terminals of the precharge & encode circuits 112A and 112B. As a result, the level of each search line becomes the potential of the inverted level of the signal output by the connected search driver. Further, the precharge & encode circuits 112A and 112B accept input of inversion level signals of the connected match lines. Further, the action of the inverter Inv precharges each match line to the inverted level of the output signal of the connected precharge & encode circuit. In one aspect, each match line is precharged to “L” level.

  A search operation of the semiconductor device 1900 will be described with reference to FIGS. When the data in memory cell MC0 # 0 matches the search data, the level of the match line is maintained at the “L” level. On the other hand, when the data of memory cell MC0 # 0 and the search data do not match, the level of the match line becomes “H” level.

  As an example, a case where the search data signal S0 (A) is “1” will be described. In this case, the level of the search line SLA0 becomes the “L” level inverted by the inverter Inv. Therefore, the PMOS transistor PS0 connected to the search line SLA0 is turned on. In the above case, when the data of the memory cell MC0 # 0 is “0”, that is, when the data of the memory cell MC0 # 0 and the search data do not match, the PMOS transistor PS1 is turned on and the match line MLA0 is set to “H”. Level. On the other hand, when the data in the memory cell MC0 # 0 is “1”, that is, when the data in the memory cell MC0 # 0 matches the search data, the PMOS transistor PS1 is turned off and the match line MLA0 is precharged. Maintained at “L” level.

  According to the above, the precharge & encode circuit accepts an input of “H” level when the data held in each memory cell and the corresponding search data all match by the action of the inverter Inv. If there is even one that does not match, an “L” level input is accepted. The same applies to the precharge & encode circuit included in the semiconductor device 1000 described above.

  Therefore, the semiconductor device 1900 can use a memory cell having a PMOS transistor as a transistor for data search only by providing an inverter at each output terminal of the search driver and each input terminal of the precharge & encode circuit.

  FIG. 20 is a plan view showing an arrangement of a well, diffusion region DF, polysilicon PO, contact hole CT, and first layer metal wiring of memory cell MC0 # 0 as a TCAM cell according to another embodiment. Since the same reference numerals as those in FIGS. 8 and 13 are the same, the description of those parts will not be repeated.

  As shown in FIG. 20, the layout of MC0 # 0 according to another embodiment is the same as the layout of the BCAM cell shown in FIG. 8, but the layout of the TCAM cell shown in FIG. 13 is N well NW1, P well PW2. And a configuration in which the configurations arranged in these wells are added. Since the N well NW0 shown in FIG. 8 and the N well NW1 shown in FIG. 13 are adjacent to each other, they are expressed as one N well NW0 in FIG. A P well PW2 shown in FIG. 13 corresponds to the P well PW1 in FIG.

  Since the memory cell constituting the semiconductor device 1900 does not have the N well NW1 and the P well PW2, the number of wells is two smaller than that of the memory cell constituting the semiconductor device 1000. Therefore, the memory cell included in the semiconductor device 1900 can be smaller than the memory cell included in the semiconductor device 1000.

  Since the wiring patterns of the second layer metal wiring and the third layer metal wiring can be realized by the same wiring pattern as the example shown in FIGS. 14 and 15, the description thereof will not be repeated.

[Embodiment 3]
The data cells and mask data cells constituting the TCAM cell shown in the second embodiment are arranged adjacent to each other in the row direction, connected to a common word line, and connected to different bit line pairs. It was. In the third embodiment, another configuration of the TCAM cell will be described. More specifically, the data cells and mask data cells constituting the TCAM cell are arranged so as to be adjacent to each other in the column direction, are connected to a common bit line pair, and are connected to different word lines. The configuration will be specifically described below.

  FIG. 21 is a block diagram illustrating a configuration example of a semiconductor device 2100 according to an embodiment. In addition, since it is the same about the part which attached | subjected the code | symbol same as the code | symbol of FIG. 10, description about the part is not repeated.

  Each memory cell included in the semiconductor device 2100 is connected to two word lines, one bit line pair, two search line pairs, and two match lines. For example, memory cell MC0 # 0 is connected to word lines WL0 and WL1, bit line pair BL0 and / BL0, search line pairs SLA0 and / SLA0 and SLB0 and / SLB0, and match lines MLA0 and MLB0.

(Memory cell circuit configuration)
FIG. 22 is a circuit diagram illustrating a configuration example of the memory cell MC0 # 0 of the semiconductor device 2100. Referring to FIG. 22, memory cell MC0 # 0 includes a data cell DC0 configured to hold 1-bit data and a mask data cell MDC0. The data cell DC0 and the mask data cell MDC0 are adjacent to each other in the column direction.

  The mask data cell MDC0 is configured by NMOS transistors NA0, NA1, ND0, ND1 and PMOS transistors P0, P1.

  The NMOS transistor NA0 is connected between the storage node m1 and the bit line BL0, and the word line WL0 is connected to the gate. The NMOS transistor NA1 is connected between the storage node / m1 and the bit line / BL0, and the word line WL0 is connected to the gate. PMOS transistor P0 is connected between power supply line VDD and storage node m1, and has its gate connected to storage node / m1. The NMOS transistor ND0 is connected between the storage node m1 and the power supply line VSS, and has a gate connected to the storage node / m1. PMOS transistor P1 is connected between power supply line VDD and storage node / m1, and has its gate connected to storage node m1. The NMOS transistor ND1 is connected between the storage node / m1 and the power supply line VSS, and has a gate connected to the storage node m1.

  The NMOS transistor ND0 and the PMOS transistor P0 constitute an inverter. The NMOS transistor ND1 and the PMOS transistor P1 also constitute an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed of NMOS transistors ND0 and ND1 and PMOS transistors P0 and P1 holds 1-bit information.

  The data cell DC0 is composed of NMOS transistors NA2, NA3, ND2, ND3 and PMOS transistors P2, P3.

  The NMOS transistor NA2 is connected between the storage node m0 and the bit line BL0, and the word line WL1 is connected to the gate. The NMOS transistor NA3 is connected between the storage node / m0 and the bit line / BL0, and the word line WL1 is connected to the gate. PMOS transistor P2 is connected between power supply line VDD and storage node m0, and has its gate connected to storage node / m0. NMOS transistor ND2 is connected between storage node m0 and power supply line VSS, and has its gate connected to storage node / m0. PMOS transistor P3 is connected between power supply line VDD and storage node / m0, and has its gate connected to storage node m0. NMOS transistor ND3 is connected between storage node / m0 and power supply line VSS, and has its gate connected to storage node m0.

  The NMOS transistor ND2 and the PMOS transistor P2 constitute an inverter. The NMOS transistor ND3 and the PMOS transistor P3 also constitute an inverter. The output of one inverter is connected to the input of the other inverter. A flip-flop formed by NMOS transistors ND2 and ND3 and PMOS transistors P2 and P3 holds 1-bit information.

  As described above, data cell DC0 and mask data cell MDC0 are connected to a common bit line pair BL0, / BL0. The data cell DC0 and the mask data cell MDC0 are connected to different word lines WL0 and WL1, respectively.

  Memory cell MC0 # 0 includes logic operation cells LCA0 and LCB0 between data cell DC0 and mask data cell MDC0. The logic operation cells LCA0 and LCB0 are adjacent to each other in the row direction.

  The logical operation cell LCA0 outputs a result corresponding to the data held in the data cell DC0 and the mask data cell MDC0 and the search data for the A port to the match line MLA0. The logical operation cell LCB0 outputs a result corresponding to the data held in the data cell DC0 and the mask data cell MDC0 and the search data for the B port to the match line MLA0.

  The logical operation cell LCA0 includes NMOS transistors NS0 to NS3. The logical operation cell LCB0 includes NMOS transistors NS4 to NS7.

  The NMOS transistors NS0 and NS1 are connected in series between the match line MLA0 and the power supply line VSS, and the search line SLA0 and the storage node m0 are connected to the gates, respectively. NMOS transistors NS2 and NS3 are connected in series between match line MLA0 and power supply line VSS, and search line / SLA0 and storage node m1 are connected to the gates, respectively.

  The NMOS transistors NS4 and NS5 are connected in series between the match line MLB0 and the power supply line VSS, and the search line SLB0 and the storage node m0 are connected to the gates, respectively. NMOS transistors NS6 and NS7 are connected in series between match line MLB0 and power supply line VSS, and search line / SLB0 and storage node m1 are connected to the gates, respectively.

  It is assumed that the data in the memory cell MC0 # 0 shown in FIG. 22 is the same as that of the memory cell MC0 # 0 shown in FIG. That is, assume that “0” is stored in the memory cell MC0 # 0 when the storage node m0 of the data cell DC0 is “0” and the storage node m1 of the mask data cell MDC0 is “1”. Assume that “1” is stored in the memory cell MC0 # 0 when the storage node m0 of the data cell DC0 is “1” and the storage node m1 of the mask data cell MDC0 is “0”. Assume that “*” (don't care) is stored in the memory cell MC0 # 0 when the storage node m0 of the data cell DC0 is “0” and the storage node m1 of the mask data cell MDC0 is “0”. This is not used when the storage node m0 of the data cell DC0 is “1” and the storage node m1 of the mask data cell MDC0 is “1”.

(Write operation)
A write operation to memory cell MC0 # 0 shown in FIG. 22 will be described. Row decoder 102 first activates word line WL0 to “H” level and writes the other word lines (ie, word lines WL1 to WL4) to “L” level when writing data to memory cell MC0 # 0. Activate. Read / write circuit 108 drives bit line BL0 to a level corresponding to input data DIO00, and drives bit line / BL0 to its inverted level. Thereby, the semiconductor device 2100 writes data to the data cell DC0. Read / write circuit 108 sets the level of bit line pair BL0, / BL0 to "L" level when data writing to data cell DC0 is completed.

  Next, the row decoder 102 activates the word line WL1 to the “H” level and deactivates other word lines to the “L” level. Read / write circuit 108 drives bit line BL0 to a level corresponding to input data DIO01, and drives bit line / BL0 to its inverted level. Thereby, semiconductor device 2100 writes data to mask data cell MDC0. Read / write circuit 108 sets the level of bit line pair BL0, / BL0 to "L" level when data writing to data cell DC0 is completed. The semiconductor device 2100 performs these series of operations during two cycles. Note that in another aspect, the semiconductor device 2100 can perform data writing to the mask data cell MDC0 during the first cycle, and can perform data writing to the data cell DC0 during the next cycle.

(Search operation)
Next, the search operation will be described. According to the configuration of the memory cell MC0 # 0 described above, the search data for the A port is “1” (that is, the search line SLA0 is “1” and the search line / SLA0 is “0”). When the data of MC0 # 0 is “0” (the storage node m0 is “0” and the storage node m1 is “1”), the NMOS transistors NS0 and NS1 are turned on and thus precharged. The potential of the match line MLA0 is pulled out to the ground potential. The search data for the A port is “0” (that is, the search line SLA0 is “0” and the search line / SLA0 is “1”), and the data in the memory cell MC0 # 0 is “1” (storage node m0). Is “1” and the storage node m1 is “0”), the NMOS transistors NS2 and NS3 are turned on, so that the potential of the precharged match line MLA0 is pulled out to the ground potential. That is, when the search data for the A port and the data of the memory cell MC0 # 0 do not match, the potential of the match line MLA0 is at the “L” level (ground potential).

  On the other hand, when the search data for the A port is “1” and the data of the memory cell MC0 # 0 is “1” or “*”, or the search data for the A port is “0”. In addition, when the data in the memory cell MC0 # 0 is “0” or “*” (that is, when both match), the potential (“H” level) of the precharged match line MLA0 is maintained.

  As described above, unless the data of all the memory cells (memory cells MC0 # 0 and MC1 # 0) connected to the match line MLA0 match the search data for the A port, the charge stored in the match line MLA0 is Pulled out.

  Since the behavior of match line MLB0 is the same as that of match line MLA0 described above, the description thereof will not be repeated.

  Based on the above, the semiconductor device 2100 functioning as the TCAM device can simultaneously search the search data for the A port and the search data for the B port during one cycle, like the semiconductor device 1000 described above. Therefore, when there are a plurality of search targets, the semiconductor device 2100 can realize a search speed twice as high as that of a single-port search device (TCAM device).

  In addition, the semiconductor device 2100 searches for search data for the A port and search data for the B port using a common memory array. Therefore, the semiconductor device 2100 can suppress an increase in size of the device.

  Further, the conventional TCAM device needs to generate a clock signal twice in order to search for two search data. On the other hand, the semiconductor device 2100 may generate a clock signal once when searching for two search data. Therefore, this semiconductor device 2100 can suppress power consumption as compared with the conventional case.

(Memory cell layout)
Next, a layout configuration of the memory cell MC0 # 0 arranged in the semiconductor device 2100 will be described as an example by dividing it in the stacking direction with reference to FIGS. In addition, since it is the same about the part which has attached | subjected the code | symbol same as the code | symbol of FIGS. 13-15, the description about the part is not repeated.

  FIG. 23 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, contact hole CT, and first layer metal wiring of memory cell MC0 # 0 arranged in semiconductor device 2100. FIG.

  In memory cell MC0 # 0 according to an embodiment, P-type conductivity type P well PW0, N-type conductivity type N well NW0, and P well PW1 are formed in this order in the row direction. In the P well PW0, NMOS transistors NA2, NA3, ND2, ND3 constituting the data cell DC0 are arranged. In N well NW0, PMOS transistors P0 and P1 forming data cell DC0 and PMOS transistors P2 and P3 forming mask data cell MDC0 are arranged. In the P well PW1, NMOS transistors NA2, NA3, ND2, ND3 constituting the mask data cell MDC0 and NMOS transistors NS0 to NS7 for data search are arranged.

  NMOS transistor ND2 has a source and a drain formed by a pair of N-type diffusion regions FL502 and FL504, and a polysilicon gate arranged therebetween. N-type diffusion region FL502 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT406.

  NMOS transistor NA2 has a source and a drain formed by a pair of N-type diffusion regions FL504 and FL506, and a polysilicon gate arranged therebetween. This gate is electrically connected to the word line WL1 formed in the upper metal wiring layer through the contact hole CT402. N-type diffusion region FL506 is electrically connected to bit line BL0 formed in the upper metal wiring layer through contact hole CT410.

  NMOS transistor NA0 has a source and a drain formed by a pair of N-type diffusion regions FL506 and FL508, and a polysilicon gate arranged therebetween. This gate is electrically connected to word line WL0 formed in the upper metal wiring layer through contact hole CT404.

  NMOS transistor ND0 has a source and a drain formed by a pair of N-type diffusion regions FL508 and FL510, and a polysilicon gate arranged therebetween. N-type diffusion region FL510 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT414.

  NMOS transistors ND2, NA2, NA0, and ND0 are arranged in a common N-type diffusion layer DF.

  PMOS transistor P2 has a source and a drain formed by a pair of P-type diffusion regions FL512, FL514, and a polysilicon gate arranged therebetween. P-type diffusion region FL514 and N-type diffusion region FL504 are connected to a common first layer metal wiring via contact holes CT418 and CT408, respectively. The contact hole CT418 is also provided at the gate of a PMOS transistor P3 described later. Therefore, P type diffusion region FL514, N type diffusion region FL504, and the gate of PMOS transistor P3 are electrically connected to each other. P-type diffusion region FL512 is electrically connected to power supply line VDD formed in the upper metal wiring layer via contact hole CT416.

  PMOS transistor P0 has a source and a drain formed by a pair of P-type diffusion regions FL513, FL515, and a polysilicon gate arranged therebetween. P-type diffusion region FL513 and N-type diffusion region FL508 are connected to a common first layer metal wiring through contact holes CT420 and CT412, respectively. The contact hole CT420 is also provided at the gate of a PMOS transistor P1 described later. Therefore, P type diffusion region FL513, N type diffusion region FL508, and the gate of PMOS transistor P1 are electrically connected to each other. P-type diffusion region FL515 is electrically connected to power supply line VDD formed in the upper metal wiring layer through contact hole CT422.

  PMOS transistor P3 has a source and a drain formed by a pair of P-type diffusion regions FL516 and FL518, and a polysilicon gate disposed therebetween. P-type diffusion region FL516 and the gate of PMOS transistor P2 are electrically connected by a common contact hole CT424. P-type diffusion region FL516 and N-type diffusion region FL524 forming the drain of NMOS transistor NA3, which will be described later, are connected to a common first layer metal wiring via contact holes CT424 and CT432, respectively. Therefore, P type diffusion region FL516, the gate of PMOS transistor P2, and N type diffusion region FL524 are electrically connected to each other. P-type diffusion region FL518 is electrically connected to power supply line VDD formed in the upper metal wiring layer through contact hole CT426.

  The PMOS transistor P1 has a source and a drain formed by a pair of P-type diffusion regions FL518 and FL520, and a polysilicon gate disposed therebetween. P-type diffusion region FL520 and the gate of PMOS transistor P0 are electrically connected by a common contact hole CT428. P-type diffusion region FL520 and N-type diffusion region FL528 forming the drain of NMOS transistor NA1, which will be described later, are connected to a common first layer metal wiring via contact holes CT428 and CT436, respectively. Therefore, P type diffusion region FL520, the gate of PMOS transistor P0, and N type diffusion region FL528 are electrically connected to each other. PMOS transistors P3 and P1 are arranged in a common P-type diffusion layer DF.

  NMOS transistor NA3 has a source and a drain formed by a pair of N-type diffusion regions FL522, FL524, and a polysilicon gate disposed therebetween. This gate is electrically connected to word line WL1 formed in the upper metal wiring layer through contact hole CT440. N-type diffusion region FL522 is electrically connected to bit line / BL0 formed in the upper metal wiring layer through contact hole CT430.

  NMOS transistor ND3 has a source and a drain formed by a pair of N-type diffusion regions FL524 and FL526, and a polysilicon gate arranged therebetween. N-type diffusion region FL526 is electrically connected to power supply line VSS formed in the upper metal wiring layer through contact hole CT434.

  NMOS transistor ND1 has a source and a drain formed by a pair of N-type diffusion regions FL526 and FL528, and a polysilicon gate arranged therebetween.

  NMOS transistor NA1 has a source and a drain formed by a pair of N-type diffusion regions FL528 and FL530, and a polysilicon gate arranged therebetween. This gate is electrically connected to word line WL0 formed in the upper metal wiring layer through contact hole CT442. N-type diffusion region FL530 is electrically connected to bit line / BL0 formed in the upper metal wiring layer via contact hole CT438.

  As described above, since the memory cell constituting the semiconductor device 2100 does not have the N well NW1 and the P well PW2, the number of wells is larger than that of the memory cell constituting the semiconductor device 1000 described with reference to FIG. Two less. Therefore, the memory cell included in the semiconductor device 2100 can be further downsized than the memory cell included in the semiconductor device 1000.

  FIG. 24 is a plan view showing an arrangement of via 1, first metal wiring layer, and second metal wiring layer of memory cell MC0 # 0 arranged in semiconductor device 2100. FIG.

  The gate of the NMOS transistor NA2 is connected to the second layer metal wiring M260 forming the word line WL1 through the contact hole CT402, the first layer metal wiring, and the via 1V150.

  The gate of NMOS transistor NA0 is connected to second layer metal interconnection M262 forming word line WL0 through contact hole CT404, first layer metal interconnection, and via 1V152.

  The N-type diffusion region FL502 that forms the source of the NMOS transistor ND2 and the N-type diffusion region FL510 that forms the source of the NMOS transistor ND0 are connected to the common first layer metal wiring via the contact holes CT406 and CT414, respectively. . This first layer metal interconnection is connected to second layer metal interconnection M264 forming power supply line VSS via via 1V154 and via 1V156.

  N-type diffusion region FL506 forming the sources of NMOS transistors NA2 and NA0 is connected to second layer metal interconnection M266 forming bit line BL0 via contact hole CT410, first layer metal interconnection, and via V158.

  P-type diffusion region FL512 that forms the source of PMOS transistor P2 is connected to second layer metal wiring M268 that forms power supply line VDD via contact hole CT416, first layer metal wiring, and via 1V160. P type diffusion region FL518 forming the sources of PMOS transistors P3 and P1 is connected to second layer metal interconnection M268 via contact hole CT426, first layer metal interconnection, and via 1V161. P-type diffusion region FL515 forming the source of PMOS transistor P0 is connected to second layer metal interconnection M268 through contact hole CT422, first layer metal interconnection, and via 1V162.

  N-type diffusion region FL522 that forms the source of NMOS transistor NA3 and N-type diffusion region FL530 that forms the source of NMOS transistor NA1 are connected to a common first-layer metal interconnection via contact holes CT430 and CT428, respectively. This first layer metal interconnection is connected to second layer metal interconnection M270 forming bit line / BL0 via via 1V164 and via 1V166.

  N-type diffusion region FL526 forming the sources of NMOS transistors ND3 and ND1 is connected to second layer metal wiring M272 forming power supply line VSS via contact hole CT434, first layer metal wiring, and via 1V168. .

  The gate of the NMOS transistor NA3 is connected to the second layer metal wiring M274 forming the word line WL1 through the contact hole CT440, the first layer metal wiring, and the via 1V170.

  The gate of the NMOS transistor NA1 is connected to the second layer metal wiring M276 that forms the word line WL0 through the contact hole CT442, the first layer metal wiring, and the via 1V172.

  FIG. 25 is a plan view showing the arrangement of vias 2, second-layer metal wiring layers, and third-layer metal wiring layers of memory cell MC 0 # 0 arranged in semiconductor device 2100. In FIG. 25, third layer metal interconnections M360 to M380 are arranged along the row direction.

  Second layer metal interconnections M260 and M274 are connected to common third layer metal interconnection M360 forming word line WL1 through vias 2V215 and vias 2V255, respectively.

  Second-layer metal interconnection M222 is connected to third-layer metal interconnection M365 forming match line MLB0 through via 2V292.

  Second layer metal interconnections M264, M272, and M218 are connected to common third layer metal interconnection M370 that forms a power supply node via via 2V235, via 2V245, and via 2V282, respectively.

  Second layer metal interconnection M214 is connected to third layer metal interconnection M275 forming match line MLA0 through via 2V272.

  Second layer metal interconnections M262 and M276 are connected to common third layer metal interconnection M380 forming word line WL0 through via 2V225 and via 2V265, respectively.

  Note that the wiring pattern of the metal wiring inside the memory cell MC1 # 0 adjacent to the memory cell MC0 # 0 in the row direction is the same as the wiring pattern in which the wiring pattern of the memory cell MC0 # 0 is targeted in the column direction. The description will not be repeated. Note that the wiring pattern of the metal wiring inside the memory cell MC0 # 1 adjacent to the memory cell MC0 # 0 in the column direction is the same as the wiring pattern in which the wiring pattern of the memory cell MC0 # 0 is targeted in the row direction. Alternatively, the wiring pattern of the memory cell MC0 # 0 may be the same.

  By configuring the layout as described above, a highly integrated CAM memory array can be realized up to the third metal wiring layer. If the number of wiring layers can be reduced, manufacturing costs can be reduced.

(Modification)
In the above embodiment, the transistors for data search are NMOS transistors (NS01 to NS07). In another embodiment, the semiconductor device employs a PMOS transistor as a data search transistor.

  FIG. 26 is a circuit diagram illustrating a configuration example of the memory cell MC0 # 0 according to the modification of the third embodiment. Of the elements shown in FIG. 26, the elements described in FIG. Therefore, the description about the element is not repeated.

  The logic operation cell LCA0 according to the modification includes PMOS transistors PS0, PS1, PS2, and PS3 instead of the NMOS transistors NS0, NS1, NS2, and NS3. The logic operation cell LCB0 according to the modification includes PMOS transistors PS4, PS5, PS6, PS7 instead of the NMOS transistors NS4, NS5, NS6, NS7.

  The PMOS transistors PS0 and PS1 are connected in series between the match line MLA0 and the power supply line VDD. The gate of the PMOS transistor PS0 is connected to the search line SLA0. The gate of the PMOS transistor PS1 is connected to the storage node m1.

  The PMOS transistors PS2 and PS3 are connected in series between the match line MLA0 and the power supply line VDD. The gate of the PMOS transistor PS2 is connected to the search line / SLA0. The gate of the PMOS transistor PS3 is connected to the storage node m0.

  The PMOS transistors PS4 and PS5 are connected in series between the match line MLB0 and the power supply line VDD. The gate of the PMOS transistor PS4 is connected to the search line SLB0. The gate of the PMOS transistor PS5 is connected to the storage node m1.

  PMOS transistors PS6 and PS7 are connected in series between match line MLB0 and power supply line VDD. The gate of PMOS transistor PS6 is connected to search line / SLB0. The gate of the PMOS transistor PS7 is connected to the storage node m0.

  Assume that the data in memory cell MC0 # 0 according to the modification is the same as the data in memory cell MC0 # 0 shown in FIG.

  FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device 2700 according to a modification of the third embodiment. In addition, the same code | symbol is attached | subjected to the element demonstrated in FIG. 21 among the elements shown by FIG. Therefore, the description about the element is not repeated.

  As shown in FIG. 26, the memory cells MC0 # 0 to MC1 # 1 arranged in the semiconductor device 2700 have PMOS transistors as data search transistors.

  The semiconductor device 2700 has inverters Inv at the output terminals of the search drivers 104A, 104B, 106A, and 106B and the input terminals of the precharge & encode circuits 112A and 112B. As a result, the level of each search line becomes the potential of the inverted level of the signal output by the connected search driver. Further, the precharge & encode circuits 112A and 112B accept input of inversion level signals of the connected match lines. Further, the action of the inverter Inv precharges each match line to the inverted level of the output signal of the connected precharge & encode circuit. In one aspect, each match line is precharged to “L” level.

  A search operation of the semiconductor device 2700 will be described with reference to FIGS. When the data in memory cell MC0 # 0 matches the search data, the level of the match line is maintained at the “L” level. On the other hand, when the data of memory cell MC0 # 0 and the search data do not match, the level of the match line becomes “H” level.

  As an example, a case where the search data signal S0 (A) is “1” will be described. In this case, the level of the search line SLA0 becomes the “L” level inverted by the inverter Inv. Therefore, the PMOS transistor PS0 connected to the search line SLA0 is turned on. In the above case, when the data of the memory cell MC0 # 0 is “0”, that is, when the data of the memory cell MC0 # 0 and the search data do not match, the PMOS transistor PS1 is turned on and the match line MLA0 is set to “H”. Level. On the other hand, when the data in the memory cell MC0 # 0 is “1”, that is, when the data in the memory cell MC0 # 0 matches the search data, the PMOS transistor PS1 is turned off and the match line MLA0 is precharged. Maintained at “L” level.

  According to the above, the precharge & encode circuit accepts an input of “H” level when the data held in each memory cell and the corresponding search data all match by the action of the inverter Inv. If there is even one that does not match, an “L” level input is accepted.

  FIG. 28 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, contact hole CT, and first layer metal wiring of memory cell MC0 # 0 according to the modification of the third embodiment.

  The well configuration of memory cell MC0 # 0 shown in FIG. 28 is different from the well configuration of memory cell MC0 # 0 shown in FIG. 23 in that it further includes an N well NW1. The layout shown in FIG. 28 replaces the layout related to NMOS transistors NS0 to NS7 for data search in the layout shown in FIG. 23 with the layout related to PMOS transistors PS0 to PS7 for data search shown in FIG. It is a thing. Therefore, details of memory cell MC0 # 0 shown in FIG. 28 will not be repeated.

  FIG. 29 is a plan view showing the arrangement of via 1, first-layer metal interconnection layer, and second-layer metal interconnection layer of memory cell MC 0 # 0 arranged in semiconductor device 2700. The layout shown in FIG. 29 is substantially the same as the layout shown in FIG. Therefore, only different points will be described.

  The P-type diffusion region FL340 that forms the source of the PMOS transistor PS2 and the P-type diffusion region FL350 that forms the source of the PMOS transistor PS6 are connected to a common first layer metal wiring via contact holes CT48 and CT54, respectively. The This first layer metal wiring is connected to a second layer metal wiring M910 that forms a power supply line VDD through a via 1V121.

  The P-type diffusion region FL348 forming the source of the PMOS transistor PS2 and the P-type diffusion region FL358 forming the source of the PMOS transistor PS6 are connected to the common first layer metal wiring via the contact holes CT52 and CT58, respectively. The This first-layer metal wiring is connected to a second-layer metal wiring M910 that forms a power supply line VDD through a via 1V123.

  FIG. 30 is a plan view showing the arrangement of via 2, second metal wiring layer, and third metal wiring layer of memory cell MC0 # 0 arranged in semiconductor device 2700. The layout shown in FIG. 30 is the same as the layout shown in FIG. 25 except that via 2V282 is not provided in third layer metal interconnection M370.

  The semiconductor device 2700 that uses a PMOS transistor as a data search transistor can also simultaneously search for search data for the A port and search data for the B port.

[Embodiment 4]
In the above embodiment, each transistor is a planar (planar) transistor and has a structure having a single gate with respect to the channel. The semiconductor device according to the present embodiment employs a multi-gate transistor having a plurality of gates with respect to the channel.

(Transistor structure)
FIG. 31 illustrates a structure of a transistor. FIG. 31A illustrates an example of a structure of a planar field effect transistor (hereinafter also referred to as “planar FET”). FIG. 31B illustrates an example of a structure of a fin-type field effect transistor (hereinafter also referred to as “FinFET (Field effect transistor)”). FIG. 31C illustrates an example of the structure of a GAA (Gate All Around) field effect transistor (hereinafter also referred to as “GAAFET”).

  Referring to FIG. 31A, in a planar FET, a source, a channel, and a drain are formed on the same plane. Further, the gate of the planar FET is formed on the channel via a gate insulating film. That is, the gate is formed so as to cover one surface of the channel.

  The channel of the FinFET shown in FIG. 31B protrudes from the silicon substrate compared to the channel of the planar FET. The gate of the FinFET is formed so as to cover the side surface and the upper surface of the protruding channel.

  A nanowire obtained by crystal growth is used for the channel of the GAAFET shown in FIG. The gate of the GAAFET is configured to completely cover the channel (nanowire) axis.

  In the planar FET shown in FIG. 31A, since the channel is a plane, the gate faces the channel only from one direction. In this case, the depletion layer is formed only on one surface of the channel, and the leakage current increases.

  On the other hand, in the transistor illustrated in FIG. 31B or 31C, the gate faces the channel from a plurality of directions. This increases the current drive capability of the channel. Also, the channel is substantially depleted. As a result, these transistors can reduce leakage current. Therefore, the semiconductor device according to the fourth embodiment employs these multi-gate transistors. The schematic configuration of this semiconductor device is the same as the schematic configuration shown in FIG.

(Layout of dual port TCAM using FinFET)
Hereinafter, as an example, a case in which a FinFET is used as a transistor constituting the memory cell MC0 # 0 shown in FIG.

  FIG. 32 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, and local interconnection (LIC: Local Inter Connect) of memory cell MC0 # 0 according to the fourth embodiment. The layout of memory cell MC0 # 0 shown in FIG. 32 is that memory cell MC0 # 0 shown in FIG. 23 is provided in that a diffusion layer DF corresponding to a Fin of FinFET is provided and a local wiring is provided. The layout is different. Therefore, these points will be described.

  In memory cell MC0 # 0 according to the fourth embodiment, P-type conductivity type P well PW0, N-type conductivity type N well NW0, and P well PW1 are formed in this order in the row direction.

  In each well, a diffusion layer DF corresponding to a fin of FinFET is formed. More specifically, two diffusion layers DF corresponding to the sources and drains of the NMOS transistors NA2, NA3, ND2, and ND3 constituting the data cell DC0 are formed in the P well PW0.

  In N well NW0, one diffusion layer DF corresponding to PMOS transistors P0 and P1 constituting data cell DC0 and one diffusion layer DF corresponding to PMOS transistors P2 and P3 constituting mask data cell MDC0 are formed. ing.

  For example, the NMOS transistor ND2 has a source and a drain constituted by a pair of N-type diffusion regions FL702 and FL704, and a polysilicon gate arranged therebetween. Each N-type diffusion region FL702, FL704 is constituted by two common diffusion layers DF. That is, the source and drain of the NMOS transistor ND2 are constituted by the two diffusion layers DF.

  The P well PW1 includes a diffusion layer DF corresponding to the NMOS transistors NA2, NA3, ND2, ND3 constituting the mask data cell MDC0, a diffusion layer DF corresponding to the NMOS transistors NS0 to NS3 for data search, and an NMOS transistor. Two diffusion layers DF corresponding to NS4 to NS7 are formed.

  As the number of fins (diffusion layers) per transistor increases, the current drive capability of the transistor improves. In the example shown in FIG. 32, the number of fins corresponding to the PMOS transistors P0 to P3 is one, and the number of fins corresponding to the other NMOS transistors is two. However, the number of fins per transistor is limited to this. Absent. For example, the number of fins per transistor may be set to 3 or more.

  32 is a diffusion region (source, drain) and gate constituting each transistor shown in FIG. 32 except that the diffusion layer DF corresponds to a fin of FinFET, and the diffusion region constituting each transistor shown in FIG. And the gate relationship.

  Next, the arrangement of local wiring will be described. The local wiring is made of, for example, a single metal such as tungsten, and is arranged in ohmic contact with the source, drain, or gate of the transistor. That is, the local wiring functions as a source electrode, a drain electrode, or a gate electrode.

  The local wiring shown in FIG. 32 is arranged in place of each contact hole and first layer metal wiring shown in FIG. N-type diffusion region FL702 (two diffusion layers DF constituting), connected to each gate of FL706, FL710, FL712, FL718, FL722, FL740, FL750, and NMOS transistors NA0-NA3, NS0, NS2, NS4, NS6 The local wiring is arranged in place of one contact hole and one first layer metal wiring shown in FIG. In addition, local wirings are arranged independently in N-type diffusion regions FL736, FL744, FL746, and FL754, respectively. These local wirings are connected to the upper-layer first-layer metal wirings through vias 0, respectively. For example, the local wiring connected to the N-type diffusion region FL702 is connected to the first layer metal wiring in the upper layer through the via 0V006. In the N-type diffusion regions FL738, FL742, FL748, and FL752, local wirings for making two fins (diffusion layer DF) equipotential are arranged independently.

  The local wiring that connects the polysilicon constituting the gates of the PMOS transistor P3 and NMOS transistors ND3, NS3, NS7 and the N-type diffusion region FL704 is composed of two contact holes (CT408, CT418) and one first layer metal. Arranged instead of wiring. Similarly, a local wiring connecting the gate of the PMOS transistor P1 and the N-type diffusion region FL708, a local wiring connecting the gate of the PMOS transistor P2 and the N-type diffusion region FL728, and a gate and the N-type diffusion region of the PMOS transistor P0. The local wiring connecting FL 732 is also arranged in place of two contact holes and one first layer metal wiring. These local wirings are not connected to the upper-layer first-layer metal wiring, but are simply arranged to connect the drain of the NMOS transistor and the gate of the PMOS transistor.

  FIG. 33 is a plan view showing the arrangement of via 0, local wiring, and first-layer metal wiring layer of memory cell MC0 # 0 according to the fourth embodiment. The layout of the first layer metal wiring shown in FIG. 33 is substantially the same as the layout of the second layer metal wiring shown in FIG.

  Specifically, the first layer metal wirings M660, M662, M664, M666, M668, M670, M672, M674, M676, M612, M616, M618, M620, and M624 shown in FIG. 33 are the same as those shown in FIG. It corresponds to the two-layer metal wiring M260, M262, M264, M266, M268, M270, M272, M274, M276, M212, M216, M218, M220, and M224, respectively. The first layer metal wiring M618 functions as a dummy wiring. In another embodiment, the first layer metal wiring M618 may not be arranged.

  The N-type diffusion region FL736 that forms the source of the NMOS transistor NS2 is connected to the first metal wiring M682 that forms the power supply line VSS via the local wiring and the via 0V030.

  N-type diffusion region FL740 forming the sources of NMOS transistors NS3 and NS1 is connected to first metal wiring M684 forming match line MLA0 via local wiring and via 0V032.

  The N-type diffusion region FL744 forming the source of the NMOS transistor NS0 is connected to the first metal wiring M686 forming the power supply line VSS via the local wiring and the via 0V034.

  The N type diffusion region FL746 forming the source of the NMOS transistor NS6 is connected to the first metal wiring M688 forming the power supply line VSS via the local wiring and the via 0V040.

  N-type diffusion region FL750 forming the sources of NMOS transistors NS7 and NS5 is connected to first metal wiring M692 forming match line MLB0 via local wiring and via 0V042.

  The N type diffusion region FL754 that forms the source of the NMOS transistor NS4 is connected to the first metal wiring M694 that forms the power supply line VSS via the local wiring and the via 0V044.

  FIG. 34 is a plan view showing the arrangement of via 1, first metal wiring layer, and second metal wiring layer of memory cell MC 0 # 0 according to the fourth embodiment. In FIG. 34, second-layer metal interconnections M710 to M760 are arranged along the row direction.

  First layer metal interconnections M664, M672, M682, and M688 are connected to second layer metal interconnection M710 that forms power supply line VSS via vias 1V177, V179, V183, and V186, respectively.

  First layer metal interconnections M660 and M674 are connected to second layer metal interconnection M720 forming word line WL1 through vias 1V175 and V181, respectively.

  First layer metal interconnection M692 is connected to second layer metal interconnection M730 forming match line MLB0 through via 1V187.

  First layer metal interconnection M684 is connected to second layer metal interconnection M740 forming match line MLA0 through via 1V184.

  First layer metal interconnections M662 and M676 are connected to second layer metal interconnection M750 forming word line WL0 through vias 1V176 and V182, respectively.

  First-layer metal wirings M664, M672, M686, and M694 are connected to second-layer metal wiring M760 that forms power supply line VSS through vias 1V178, V180, V185, and V188, respectively.

  As described above, the semiconductor device according to the fourth embodiment can reduce the number of metal wiring layers by using local wiring. Specifically, this semiconductor device can omit a layer corresponding to the first layer metal wiring described in FIG. That is, the semiconductor device according to the fourth embodiment can be further downsized as compared with the semiconductor device 2100.

[Embodiment 5]
As shown in FIGS. 32 to 34, the memory cell MC0 # 0 according to the fourth embodiment includes the power supply line VSS connected to the NMOS transistor for data search, and the transistors constituting the data cell DC0 and the mask data cell MDC0. The power supply line VSS connected to is common. In such a case, there is a predetermined amount of leakage current of the NMOS transistor for data search both when searching (searching) data and not searching.

  The semiconductor device according to the fifth embodiment can solve the above problem. Hereinafter, a specific configuration of the semiconductor device according to the fifth embodiment will be described.

  FIG. 35 is a circuit diagram illustrating a configuration example of the memory cell MC0 # 0 of the semiconductor device according to the fifth embodiment. The configuration of memory cell MC0 # 0 shown in FIG. 35 is substantially the same as the configuration of memory cell MC0 # 0 shown in FIG. Therefore, only different parts will be described.

  The NMOS transistors NS0 and NS1 are connected in series between the match line MLA0 and the power supply line VSSA0, and the search line SLA0 and the storage node m0 are connected to the gates, respectively. NMOS transistors NS2 and NS3 are connected in series between match line MLA0 and power supply line VSSA0, and search line / SLA0 and storage node m1 are connected to the gates, respectively. That is, the power supply line VSSA0 is connected to the logic operation cell LCA0.

  The NMOS transistors NS4 and NS5 are connected in series between the match line MLB0 and the power supply line VSSB0, and the search line SLB0 and the storage node m0 are connected to the gates, respectively. NMOS transistors NS6 and NS7 are connected in series between match line MLB0 and power supply line VSSB0, and search line / SLB0 and storage node m1 are connected to the gates, respectively. That is, the power supply line VSSB0 is connected to the logic operation cell LCB0.

  As described above, the power supply lines VSSA0 and VSSB0 connected to the transistors for data search and the power supply line VSS connected to the transistors constituting the data cell DC0 and the mask data cell MDC0 are electrically independent from each other. Yes.

  The write operation of the memory cell MC0 # 0 shown in FIG. 35 is the same as the write operation of the memory cell MC0 # 0 described in FIG.

(Search operation)
FIG. 36 is a view for explaining a metal wiring pattern in each memory cell constituting semiconductor device 3600 according to the fifth embodiment. In the figure, “F” represents the direction of the metal wiring pattern. In the example shown in FIG. 36, the memory cells MC0 # 0, MC0 # 1, MC1 # 0, and MC1 # 1 are set to the same wiring pattern.

  Memory cell MC0 # 0 and memory cell MC0 # 1 share power supply lines VSS, VSSA0, and VSSB0, respectively. Further, a switch SWA0 that connects the power supply line VSS and the power supply line VSSA0 and a switch SWB0 that connects the power supply line VSS and the power supply line VSSB0 are respectively arranged.

  Memory cell MC1 # 0 and memory cell MC1 # 1 share power supply lines VSS, VSSA1, and VSSB1, respectively. In addition, a switch SWA1 that connects the power supply line VSS and the power supply line VSSA1 and a switch SWB1 that connects the power supply line VSS and the power supply line VSSB1 are arranged.

  The schematic configuration of the semiconductor device 3600 is the same as the schematic configuration shown in FIG. As an example, the switches SWA0 to SWB1 are connected to the search drivers 104A to 106B, respectively. In addition, the search drivers 104A to 106B output a control signal for controlling on / off of a switch connected to the search driver 104A to 106B. For example, the search driver 104A outputs a control signal PGA0 that controls on / off of the switch SWA0.

  The search driver 104A outputs a control signal PGA0 for turning on the switch SWA0 during the data search of the A port, that is, when the search data signal S0 (A) for the A port is input. On the other hand, the search driver 104A outputs a control signal PGA0 that turns off the switch SWA0 when the data search is completed (that is, when data is not searched). Similarly to the search driver 104A, the other search drivers 104B to 106B also set the corresponding switch to ON when searching for data and set the corresponding switch to OFF when not searching for data.

  Based on the above, the semiconductor device 3600 can electrically cut off the power supply line VSS connected to the data holding transistor and the power supply line connected to the data search transistor when data is not searched. As a result, the semiconductor device 3600 can suppress the leakage current in the data search transistor when data is not searched.

  In the above example, the semiconductor device 3600 is configured to arrange a switch for each column in the memory array. However, in another embodiment, the semiconductor device 3600 may be configured to arrange a switch for each memory array. . In this case, the A port power lines VSSA0 and VSSA1 arranged for each column are electrically connected. Further, the power lines VSSB0 and VSSB1 for the B port are also electrically connected. Thereby, the semiconductor device 3600 according to another embodiment can reduce the number of switch elements.

(Memory cell layout)
Next, the layout of the memory cell MC0 # 0 constituting the semiconductor device 3600 will be described in the stacking direction with reference to FIGS.

  FIG. 37 is a plan view showing the arrangement of the well, diffusion region DF, polysilicon PO, and local wiring of memory cell MC0 # 0 according to the fifth embodiment. The layout shown in FIG. 37 is the same as the layout shown in FIG. However, the local wiring connected to the data search transistor is connected to a power supply line arranged independently of the power supply line VSS.

  Specifically, the N-type diffusion region FL736 that forms the source of the NMOS transistor NS2 is connected to a local wiring that functions as the power supply line VSSA0. The N-type diffusion region FL744 that forms the source of the NMOS transistor N0 is connected to a local wiring that functions as the power supply line VSSA0. The N type diffusion region FL746 forming the source of the NMOS transistor N6 is connected to a local wiring functioning as the power supply line VSSB0. The N type diffusion region FL754 forming the source of the NMOS transistor N4 is connected to a local wiring functioning as the power supply line VSSB0.

  FIG. 38 is a plan view showing the arrangement of via 0, local wiring, and first metal wiring layer of memory cell MC0 # 0 according to the fifth embodiment. The layout shown in FIG. 38 is the same as the layout shown in FIG.

  However, the first layer metal wirings M682 and M686 function not as the power supply line VSS but as the power supply line VSSA0. The first-layer metal wirings M688 and M694 function not as the power supply line VSS but as the power supply line VSSB0.

  FIG. 39 is a plan view showing the arrangement of via 1, first layer metal wiring layer, and second layer metal wiring layer of memory cell MC0 # 0 according to the fifth embodiment. The layout shown in FIG. 39 is substantially the same as the layout shown in FIG. Therefore, only different points will be described.

  In place of second layer metal interconnection M710, second layer metal interconnections M715, M725, and M735 are arranged. Further, in place of the second layer metal wiring M760, second layer metal wirings M745, M755, and M765 are arranged.

  First layer metal interconnections M664 and M672 are connected to second layer metal interconnection M715 forming power supply line VSS via vias 1V177 and V179, respectively.

  First layer metal interconnection M682 is connected to second layer metal interconnection M725 forming power supply line VSSA0 through via 1V183.

  First layer metal interconnection M688 is connected to second layer metal interconnection M735 forming power supply line VSSB0 through via 1V186.

  First layer metal interconnections M664 and M672 are connected to second layer metal interconnection M745 forming power supply line VSS via vias 1V178 and V180, respectively.

  First layer metal interconnection M686 is connected to second layer metal interconnection M755 forming power supply line VSSA0 through via 1V185.

  First layer metal interconnection M694 is connected to second layer metal interconnection M765 forming power supply line VSSB0 through via 1V188.

  FIG. 40 is a plan view showing an arrangement of via 2, second layer metal interconnection, and third layer metal interconnection of memory cell MC0 # 0 according to the fifth embodiment. In FIG. 40, third-layer metal wirings M810 to M880 are arranged along the column direction.

  The third layer metal wirings M810, M820, M825, M830, M835, M845, M855, M865, and M875 function as dummy wirings. In other embodiments, these third layer metal wirings may not be arranged.

  Second layer metal interconnection M715 is connected to third layer metal interconnections M815 and M840 forming power supply line VSS through vias 2V212 and V216.

  Second layer metal interconnection M725 is connected to third layer metal interconnections M850 and M860 forming power supply line VSSA0 through vias 2V222 and V226.

  Second layer metal interconnection M735 is connected to third layer metal interconnections M870 and M880 forming power supply line VSSB0 via vias 2V232 and V236.

  Second layer metal interconnection M745 is connected to third layer metal interconnections M815 and M840 forming power supply line VSS through vias 2V214 and V218.

  Second layer metal interconnection M755 is connected to third layer metal interconnections M850 and M860 forming power supply line VSSA0 through vias 2V224 and V228.

  Second layer metal interconnection M765 is connected to third layer metal interconnections M870 and M880 forming power supply line VSSB0 through vias 2V234 and V238.

  FIG. 41 is a plan view showing the arrangement of vias 3, third layer metal interconnections and fourth layer metal interconnections of memory cell MC0 # 0 according to the fifth embodiment. In FIG. 40, fourth-layer metal interconnections M920 to M970 are arranged along the row direction.

  The fourth layer metal wirings M930 and M960 function as dummy wirings. In other embodiments, these fourth layer metal wirings may not be arranged.

  Third layer metal interconnection M815 is connected to fourth layer metal interconnections M920 and M970 forming power supply line VSS via vias 3V310 and V320.

  Third layer metal interconnection M840 is connected to fourth layer metal interconnections M920 and M970 forming power supply line VSS via vias 3V330 and V340.

  Third layer metal interconnection M850 is connected to fourth layer metal interconnection M940 forming power supply line VSSA0 through via 3V350.

  Third-layer metal interconnection M860 is connected to fourth-layer metal interconnection M940 forming power supply line VSSA0 through via 3V360.

  Third-layer metal interconnection M870 is connected to fourth-layer metal interconnection M950 forming power supply line VSSB0 through via 3V370.

  Third-layer metal interconnection M880 is connected to fourth-layer metal interconnection M950 forming power supply line VSSB0 through via 3V380.

  By configuring the layout as described above, the memory cell MC0 # 0 according to the fifth embodiment includes the power supply line VSS connected to the data holding transistor and the power supply line connected to the data search transistor. Can be cut off electrically. As a result, the data search transistor according to the fifth embodiment can suppress the leakage current when data is not searched.

(Other configurations)
In the above example, the circuit configuration and layout of the 2-port CAM have been described. In another aspect, the CAM may have three or more ports. In this case, the CAM cell has as many match lines, search line pairs, and logic operation cells as the number of ports. Thereby, the semiconductor device can further improve the search speed (processing speed).

  In yet another aspect, each of the transistors described above can employ an SOI (Silicon On Insulator) structure having a buried insulating film under a gate, a source, and a channel formed between the gate and the source. Thereby, each memory cell can minimize the occurrence of a depletion layer at the PN junction. As a result, each transistor can achieve low power consumption and improved switching speed by reducing leakage current.

[Appendix]
(Appendix 1)
The semiconductor device includes a first cell (MDC0) configured to hold 1-bit information, a second cell (DC0) adjacent to the first cell, configured to hold 1-bit information, The first and second match lines (MLA0, MLB0) extending along the direction and the first line that extends along the second direction orthogonal to the first direction and transmits the first data when searching for the first data A search line pair (SLA0, / SLA0), a second search line pair (SLB0, / SLB0) that extends along the second direction and transmits the second data during the second data search, and a first search line pair And a first logic that drives the first match line based on the comparison result between the information held in the first and second cells and the first data transmitted to the first search line pair. An arithmetic cell (LCA0), a second search line pair, a second match line, A second logic operation cell (LCB0) that drives the second match line based on a comparison result between the information held in the first and second cells and the second data transmitted to the second search line pair. Prepare.

  Thereby, the semiconductor device can thereby function as a TCAM device that can simultaneously search for two search data during one cycle. Therefore, this semiconductor device can improve the search speed as compared with the conventional case when there are a plurality of search targets. In addition, this semiconductor device searches for two search data using a common memory array. Therefore, this semiconductor device can suppress an increase in size of the device. In addition, since this semiconductor device can search for two search data based on one clock signal, it can suppress power consumption.

(Appendix 2)
In (Appendix 1), the second cell is adjacent to the first cell in the first direction. The semiconductor device extends along the second direction and is connected to the first bit line pair (BL1, / BL1) connected to the first cell, and extends along the second direction and connected to the second cell. A second bit line pair (BL0, / BL0) and a word line (WL0) extending in the first direction and connected to both the first and second cells.

  As a result, the semiconductor device can write or read data to or from the second cell while writing or reading data to or from the first cell.

(Appendix 3)
In (Supplementary Note 1), the second cell is adjacent to the first cell in the second direction. The semiconductor device extends along the second direction and extends along the first direction with the bit line pair (BL0, / BL0) connected to both the first and second cells. And a second word line (WL0) extending in the first direction and connected to the second cell.

  Thereby, this semiconductor device can suppress the enlargement of the device by sharing the bit line pair between the first cell and the second cell.

(Appendix 4)
In (Supplementary Note 1), the first logic operation cell is connected between the first match line and the power supply line, and the information (m1) held in the first cell and the first search line pair at the time of the first data search A first logic unit for driving the first match line according to a result of comparison with information transmitted to one of the search lines (SLA0), a first logic line connected between the first match line and the power line; During one data search, the first match line is driven according to the comparison result between the information (m0) held in the second cell and the information transmitted to the other search line (/ SLA0) of the first search line pair. And a second logical unit for. The second logic operation cell is connected between the second match line and the power supply line, and when the second data search is performed, the information held in the first cell and one search line (SLB0) of the second search line pair are connected. The third logic unit for driving the second match line according to the comparison result with the transmitted information is connected between the second match line and the power supply line. And a fourth logic unit for driving the second match line in accordance with a comparison result between the held information and the information transmitted to the other search line (/ SLB0) of the second search line pair.

(Appendix 5)
In (Appendix 4), the first logic unit includes first (NS1 / PS1) and second transistors (NS0 / PS0) connected in series between the power supply line (VSS / VDD) and the first match line. Including. The second logic unit includes a third (NS3 / PS3) and a fourth transistor (NS2 / PS2) connected in series between the power supply line (VSS / VDD) and the first match line. The third logic unit includes fifth (NS5 / PS5) and sixth transistors (NS4 / PS4) connected in series between the power supply line (VSS / VDD) and the second match line. The fourth logic unit includes seventh (NS7 / PS7) and eighth transistors (NS6 / PS6) connected in series between the power supply line (VSS / VDD) and the second match line. The gates of the first and fifth transistors are connected to a node (m1) where the first cell holds information. The gates of the third and seventh transistors are connected to a node (m0) where the second cell holds information. The gate of the second transistor is connected to one (SLA0) of the first search line pair. The gate of the fourth transistor is connected to the other (/ SLA0) of the first search line pair. The gate of the sixth transistor is connected to one (SLB0) of the second search line pair. The gate of the eighth transistor is connected to the other (/ SLB0) of the second search line pair.

(Appendix 6)
In (Appendix 5), the second cell is adjacent to the first cell in the first direction. The semiconductor device extends along the second direction and is connected to the first bit line pair (BL1, / BL1) connected to the first cell, and extends along the second direction and connected to the second cell. A second bit line pair (BL0, / BL0) and a word line (WL0) extending in the first direction and connected to both the first and second cells. The first cell has a first inverter whose input is connected to the first storage node (m1) connected to the gates of the first and fifth transistors, and whose output is connected to the second storage node (/ m1); A second inverter having an input connected to two storage nodes and an output connected to the first storage node; one end connected to the first storage node; the other end connected to one of the first bit line pairs; A first conductivity type ninth transistor (NA0) connected to the word line, one end connected to the second storage node, the other end connected to the other of the first bit line pair, and a gate connected to the word line And a tenth transistor (NA1) of the first conductivity type connected. The second cell has a third inverter whose input is connected to the third storage node (m0) connected to the gates of the third and seventh transistors, and whose output is connected to the fourth storage node (/ m0). A fourth inverter having an input connected to the four storage nodes and an output connected to the third storage node; one end connected to the third storage node; the other end connected to one of the second bit line pair; Is connected to the word line, the first conductivity type eleventh transistor (NA2), one end connected to the fourth storage node, the other end connected to the other of the second bit line pair, and the gate to the word line And a twelfth transistor (NA3) of the first conductivity type connected. In the direction in which the word line extends, the second conductivity type first region (PW0), the first conductivity type second region (NW0), the second conductivity type third region (PW1), and the first conductivity type The fourth region (NW1) and the second conductivity type fifth region (PW2) are sequentially formed. The first region includes the ninth and tenth transistors, the first conductivity type thirteenth transistor (ND0) constituting the first inverter, and the first conductivity type fourteenth transistor (ND1) constituting the second inverter. And are arranged. In the second region, a second conductivity type 15th transistor (P0) constituting the first inverter and a second conductivity type 16th transistor (P1) constituting the second inverter are arranged. First to eighth transistors (NS0 to NS7) of the first conductivity type are disposed in the third region. A 17th transistor (P2) of the 2nd conductivity type which constitutes the 3rd inverter, and an 18th transistor (P3) of the 2nd conductivity type which constitutes the 4th inverter are arranged in the 4th field. The fifth region includes eleventh and twelfth transistors, a first conductivity type 19th transistor (ND2) constituting a third inverter, and a first conductivity type 20th transistor (ND3) constituting a fourth inverter. And are arranged.

  Thus, a semiconductor device that can function as a TCAM device can simultaneously search a plurality of search data by using an NMOS transistor as a data search transistor. Further, since this semiconductor device has a larger number of transistors for data search than the conventional one, the well for arranging the transistor becomes wider than the conventional one. Thereby, this semiconductor device can reduce the probability that a multi-bit error will occur.

(Appendix 7)
In (Appendix 5), the second cell is adjacent to the first cell in the first direction. The semiconductor device extends along the second direction and is connected to the first bit line pair (BL1, / BL1) connected to the first cell, and extends along the second direction and connected to the second cell. A second bit line pair (BL0, / BL0) and a word line (WL0) extending in the first direction and connected to both the first and second cells. The first cell has a first inverter whose input is connected to the first storage node (m1) connected to the gates of the first and fifth transistors, and whose output is connected to the second storage node (/ m1); A second inverter having an input connected to two storage nodes and an output connected to the first storage node; one end connected to the first storage node; the other end connected to one of the first bit line pairs; A first conductivity type ninth transistor (NA0) connected to the word line, one end connected to the second storage node, the other end connected to the other of the first bit line pair, and a gate connected to the word line And a tenth transistor (NA1) of the first conductivity type connected. The second cell has a third inverter whose input is connected to the third storage node (m0) connected to the gates of the third and seventh transistors, and whose output is connected to the fourth storage node (/ m0). A fourth inverter having an input connected to the four storage nodes and an output connected to the third storage node; one end connected to the third storage node; the other end connected to one of the second bit line pair; Is connected to the word line, the first conductivity type eleventh transistor (NA2), one end connected to the fourth storage node, the other end connected to the other of the second bit line pair, and the gate to the word line And a twelfth transistor (NA3) of the first conductivity type connected. A first conductivity type first region (PW0), a first conductivity type second region (NW0), and a second conductivity type third region (PW1) are sequentially formed in the direction in which the word line extends. . The first region includes the ninth and tenth transistors, the first conductivity type thirteenth transistor (ND0) constituting the first inverter, and the first conductivity type fourteenth transistor (ND1) constituting the second inverter. And are arranged. The second region includes a second conductivity type 15th transistor (P0) constituting the first inverter, a second conductivity type 16th transistor (P1) constituting the second inverter, and a second conductivity type first transistor. 1st to 8th transistors (PS0 to PS7), a second conductivity type 17th transistor (P2) constituting the third inverter, and a second conductivity type 18th transistor (P3) constituting the fourth inverter. Be placed. The third region includes eleventh and twelfth transistors, a first conductivity type 19th transistor (ND2) constituting a third inverter, and a first conductivity type 20th transistor (ND3) constituting a fourth inverter. And are arranged.

  Thereby, a semiconductor device that can function as a TCAM device can simultaneously search a plurality of search data by using a PMOS transistor as a transistor for data search. In addition, since this semiconductor device has a small number of wells in which transistors are arranged, an increase in size of the device can be suppressed. Further, since this semiconductor device has a larger number of transistors for data search than the conventional one, the well for arranging the transistor becomes wider than the conventional one. Thereby, this semiconductor device can reduce the probability that a multi-bit error will occur. In another aspect, the semiconductor device can improve the search speed by adopting a material that stresses the silicon in the channel portion such as silicon germanium in the source and drain regions of the PMOS transistor for data search.

(Appendix 8)
In (Appendix 5), the second cell is adjacent to the first cell in the second direction. The semiconductor device extends along the second direction and extends along the first direction with the bit line pair (BL0, / BL0) connected to both the first and second cells. And a second word line (WL0) extending in the first direction and connected to the second cell. The first cell has a first inverter whose input is connected to the first storage node (m1) connected to the gates of the first and fifth transistors, and whose output is connected to the second storage node (/ m1); A second inverter having an input connected to the second storage node and an output connected to the first storage node; one end connected to the first storage node; the other end connected to one of the bit line pairs; A first conductivity type ninth transistor (NA0) connected to one word line, one end connected to the second storage node, the other end connected to the other of the bit line pair, and a gate connected to the first word line And a tenth transistor (NA1) of the first conductivity type connected. The second cell has a third inverter whose input is connected to the third storage node (m0) connected to the gates of the third and seventh transistors and whose output is connected to the fourth storage node, and a fourth storage node ( / M0), an input connected to the third storage node, an output connected to the third storage node, one end connected to the third storage node, the other end connected to one of the bit line pair, and the gate connected to the An eleventh transistor (NA2) of the first conductivity type connected to two word lines, one end connected to the fourth storage node, the other end connected to the other of the bit line pair, and a gate connected to the second word line And a twelfth transistor (NA3) of the first conductivity type connected. In the direction in which the first and second word lines extend, the second conductivity type first region (PW0), the first conductivity type second region (NW0), and the second conductivity type third region (PW1) Are formed in order. The first region includes ninth and eleventh transistors, a first conductivity type thirteenth transistor (ND0) constituting the first inverter, and a first conductivity type fourteenth transistor (ND1) constituting the second inverter. And are arranged. In the second region, a second conductivity type 15th transistor (P0) constituting the first inverter, a second conductivity type 16th transistor (P1) constituting the second inverter, and a third inverter are constituted. A 17th transistor (P2) of the 2nd conductivity type and an 18th transistor (P3) of the 2nd conductivity type which constitutes the 4th inverter are arranged. The third region includes first conductivity type first to eighth transistors (NS0 to NS7), tenth and twelfth transistors, and a first conductivity type nineteenth transistor (ND2) constituting a third inverter. The 20th transistor (ND3) of the 1st conductivity type which constitutes the 4th inverter is arranged.

  Thus, a semiconductor device that can function as a TCAM device can simultaneously search a plurality of search data by using an NMOS transistor as a data search transistor. In addition, since this semiconductor device has a small number of wells in which transistors are arranged, an increase in size of the device can be suppressed.

(Appendix 9)
In (Appendix 8), at least one of the first to twentieth transistors is a multi-gate transistor.

(Appendix 10)
(Supplementary Note 8) The semiconductor device includes a first local wiring that connects a diffusion layer (FL704) shared by the eleventh transistor (NA2) and the nineteenth transistor (ND2) and a gate of the eighteenth transistor (P3). The second local wiring connecting the diffusion layer (FL708) shared by the ninth transistor (NA0) and the thirteenth transistor (ND0) and the gate of the sixteenth transistor (P1), the twelfth transistor (NA3) and the second transistor Diffusion layer (FL728) shared by 20 transistors (ND3), third local wiring connecting the gate of the 17th transistor (P2), and diffusion shared by the 10th transistor (NA1) and the 14th transistor (ND1) The fourth node connecting the layer (FL732) and the gate of the fifteenth transistor (P0). Further comprising a local wiring.

(Appendix 11)
In (Supplementary Note 4), the semiconductor device includes a first power supply line (VSS) connected to the first cell and the second cell, and a second power supply line (VSSA0) connected to the first logic unit and the second logic unit. A third power supply line (VSSB0) connected to the third logic unit and the fourth logic unit, a first switch (SWA0) connecting the first power supply line and the second power supply line, and a first power supply line A second switch (SWB0) for connecting the third power supply line is further provided. The first switch is set to ON when searching for the first data, and is set to OFF when not searching for the first data. The second switch is set to ON when searching for the second data and set to OFF when not searching for the second data.

(Appendix 12)
The semiconductor device includes a data cell (DC0) configured to hold 1-bit information, first and second match lines (MLA0, MLB0) extending along the first direction, and orthogonal to the first direction. The first search line pair (SLA0, / SLA0) that extends along the second direction and transmits the first data at the time of the first data search, and extends along the second direction at the time of the second data search. Connected to the second search line pair (SLB0, / SLB0) for transmitting the second data, the first search line pair and the first match line, and transmitted to the information stored in the data cell and the first search line pair. Based on the comparison result with the first data, the first logic operation cell (LCA0) for driving the first match line, the second search line pair and the second match line, the information stored in the data cell and the first Comparison with second data transmitted to two search line pairs And a second logic operation cells (LCB0) for driving the second match line based on.

  Thereby, the semiconductor device can thereby function as a BCAM device that can simultaneously search for two search data during one cycle. Therefore, this semiconductor device can improve the search speed as compared with the conventional case when there are a plurality of search targets. In addition, this semiconductor device searches for two search data using a common memory array. Therefore, this semiconductor device can suppress an increase in size of the device. In addition, since this semiconductor device can search for two search data based on one clock signal, it can suppress power consumption.

(Appendix 13)
In (Supplementary Note 12), the semiconductor device extends along the first direction and extends along the first direction with the bit line pair (BL0, / BL0) connected to the data cell. And a word line (WL0) to be connected. The first logic operation cell is connected between the first match line and the power supply line (VSS), and the information stored in the first storage node (A0) of the data cell and the first search line during the first data search. A first logic unit for driving the first match line according to a comparison result with information transmitted to one search line (SLA0) of the pair is connected between the first match line and the power supply line. Depending on the comparison result between the information held in the second storage node (A1) of the data cell and the information transmitted to the other search line (/ SLA0) of the first search line pair during the first data search And a second logic unit for driving the first match line. The second logic operation cell is connected between the second match line and the power supply line, and information stored in the first storage node and one search line (SLB0) of the second search line pair during the second data search. ) Connected to the third logic unit for driving the second match line according to the comparison result with the information transmitted to the second match line and the power supply line. A fourth logic unit for driving the second match line according to the comparison result between the information held in the storage node and the information transmitted to the other search line (/ SLB0) of the second search line pair; Including. The first logic unit includes a first (NS0) and a second transistor (NS1) connected in series between the power supply line and the first match line. The second logic unit includes a third (NS3) and a fourth transistor (NS2) connected in series between the power supply line and the first match line. The third logic unit includes fifth (NS5) and sixth transistors (NS4) connected in series between the power supply line and the second match line. The fourth logic unit includes seventh (NS7) and eighth transistors (NS6) connected in series between the power supply line and the second match line. The gates of the first and fifth transistors are connected to the first storage node. The gates of the third and seventh transistors are connected to the second storage node. The gate of the second transistor is connected to one (SLA0) of the first search line pair. The gate of the fourth transistor is connected to the other (/ SLA0) of the first search line pair. The gate of the sixth transistor is connected to one (SLB0) of the second search line pair. The gate of the eighth transistor is connected to the other (/ SLB0) of the second search line pair. The data cell has a first inverter having an input connected to the first storage node and an output connected to the second storage node, an input connected to the second storage node, and an output connected to the first storage node. Two inverters, a first conductivity type ninth transistor (NA0) having one end connected to the first storage node, the other end connected to one of the bit line pair, and a gate connected to the word line; Is connected to the second storage node, the other end is connected to the other of the bit line pair, and the gate is connected to the word line, and the first conductivity type tenth transistor (NA1). A first conductivity type first region (PW0), a first conductivity type second region (NW0), and a second conductivity type third region (PW1) are sequentially formed in the direction in which the word line extends. . The first region includes the ninth and tenth transistors, the first conductivity type thirteenth transistor (ND0) constituting the first inverter, and the first conductivity type fourteenth transistor (ND1) constituting the second inverter. And are arranged. In the second region, a second conductivity type 15th transistor (P0) constituting the first inverter and a second conductivity type 16th transistor (P1) constituting the second inverter are arranged. First to eighth transistors (NS0 to NS7) of the first conductivity type are disposed in the third region.

  Thus, a semiconductor device that can function as a BCAM device can simultaneously search a plurality of search data by using an NMOS transistor as a data search transistor. Further, since this semiconductor device has a larger number of transistors for data search than the conventional one, the well for arranging the transistor becomes wider than the conventional one. Thereby, this semiconductor device can reduce the probability that a multi-bit error will occur.

(Appendix 14)
In (Supplementary Note 12), the semiconductor device extends along the first direction and extends along the first direction with the bit line pair (BL0, / BL0) connected to the data cell. And a word line (WL0) to be connected. The first logic operation cell is connected between the first match line and the power supply line (VDD), and the information stored in the first storage node (A0) of the data cell and the first search line during the first data search. A first logic unit for driving the first match line according to a comparison result with information transmitted to one search line (SLA0) of the pair is connected between the first match line and the power supply line. Depending on the comparison result between the information held in the second storage node (A1) of the data cell and the information transmitted to the other search line (/ SLA0) of the first search line pair during the first data search And a second logic unit for driving the first match line. The second logic operation cell is connected between the second match line and the power supply line, and information stored in the first storage node and one search line (SLB0) of the second search line pair during the second data search. ) Connected to the third logic unit for driving the second match line according to the comparison result with the information transmitted to the second match line and the power supply line. A fourth logic unit for driving the second match line according to the comparison result between the information held in the storage node and the information transmitted to the other search line (/ SLB0) of the second search line pair; Including. The first logic unit includes a first (PS0) and a second transistor (PS1) connected in series between the power supply line and the first match line. The second logic unit includes a third (PS3) and a fourth transistor (PS2) connected in series between the power supply line and the first match line. The third logic unit includes a fifth (PS5) and a sixth transistor (PS4) connected in series between the power supply line and the second match line. The fourth logic unit includes a seventh (PS7) and an eighth transistor (PS6) connected in series between the power supply line and the second match line. The gates of the first and fifth transistors are connected to the first storage node. The gates of the third and seventh transistors are connected to the second storage node. The gate of the second transistor is connected to one (SLA0) of the first search line pair. The gate of the fourth transistor is connected to the other (/ SLA0) of the first search line pair. The gate of the sixth transistor is connected to one (SLB0) of the second search line pair. The gate of the eighth transistor is connected to the other (/ SLB0) of the second search line pair. The data cell has a first inverter having an input connected to the first storage node and an output connected to the second storage node, an input connected to the second storage node, and an output connected to the first storage node. Two inverters, a first conductivity type ninth transistor (NA0) having one end connected to the first storage node, the other end connected to one of the bit line pair, and a gate connected to the word line; Is connected to the second storage node, the other end is connected to the other of the bit line pair, and the gate is connected to the word line, and the first conductivity type tenth transistor (NA1). A first conductivity type first region (PW0) and a first conductivity type second region (NW0) are formed in the extending direction of the word line. The first region includes the ninth and tenth transistors, the first conductivity type thirteenth transistor (ND0) constituting the first inverter, and the first conductivity type fourteenth transistor (ND1) constituting the second inverter. And are arranged. The second region includes a second conductivity type 15th transistor (P0) constituting the first inverter, a second conductivity type 16th transistor (P1) constituting the second inverter, and a second conductivity type first transistor. First to eighth transistors (PS0 to PS7) are arranged.

  Thus, a semiconductor device that can function as a BCAM device can simultaneously search a plurality of search data by using a PMOS transistor as a data search transistor. In addition, since this semiconductor device has a small number of wells in which transistors are arranged, an increase in size of the device can be suppressed. Further, since this semiconductor device has a larger number of transistors for data search than the conventional one, the well for arranging the transistor becomes wider than the conventional one. Thereby, this semiconductor device can reduce the probability that a multi-bit error will occur. In another aspect, the semiconductor device can improve the search speed by adopting a material that stresses the silicon in the channel portion such as silicon germanium in the source and drain regions of the PMOS transistor for data search.

The reference numerals in the above supplementary notes are examples, and the present invention is not limited to these.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the inventor is not limited to the above embodiment, and various modifications can be made without departing from the gist of the present invention. Needless to say.

  100, 700, 1000, 1900, 2100 Semiconductor device, 102 row decoder, 104A, 104B, 106A, 106B search driver, 108, 110 read / write circuit, 112A, 112B precharge & encode circuit, BL0, BL1 bit line, DC, DC0 data cell, DF diffusion region, LCA0, LCB0 logic operation cell, PO polysilicon, SLA0, SLA1, SLB0, SLB1 search line, SWA0, SWB0, SWA1, SWA1 switch, VDD, VSS power supply line, WL0, WL1 word line.

Claims (14)

A first cell configured to hold 1-bit information;
A second cell that is configured to hold 1-bit information and is adjacent to the first cell;
First and second match lines extending along a first direction;
A first search line pair extending along a second direction orthogonal to the first direction and transmitting the first data during the first data search;
A second search line pair extending along the second direction and transmitting second data during second data search;
The first search line pair and the first match line are connected to each other based on a comparison result between information held in the first and second cells and first data transmitted to the first search line pair. A first logical operation cell for driving the first match line;
Based on a comparison result between information stored in the first and second cells and second data transmitted to the second search line pair, connected to the second search line pair and the second match line. A semiconductor device comprising: a second logic operation cell that drives a second match line. The second cell is adjacent to the first cell in the first direction;
A first bit line pair extending along the second direction and connected to the first cell;
A second bit line pair extending along the second direction and connected to the second cell;
The semiconductor device according to claim 1, further comprising a word line extending along the first direction and connected to both the first and second cells. The second cell is adjacent to the first cell in the second direction;
A bit line pair extending along the second direction and connected to both the first and second cells;
A first word line extending along the first direction and connected to the first cell;
2. The semiconductor device according to claim 1, further comprising: a second word line extending along the first direction and connected to the second cell. The first logical operation cell is:
The first match line is connected between the power line and the information held in the first cell and the information transmitted to one search line of the first search line pair during the first data search. A first logic unit for driving the first match line according to a comparison result;
The first match line is connected between the power line and the information stored in the second cell and the information transmitted to the other search line of the first search line pair during the first data search. A second logic unit for driving the first match line according to a comparison result,
The second logical operation cell is:
The second match line is connected between the power line and the information stored in the first cell and information transmitted to one search line of the second search line pair during the second data search. A third logic unit for driving the second match line according to the comparison result;
The second match line is connected between the power line and the information stored in the second cell and information transmitted to the other search line of the second search line pair during the second data search. The semiconductor device according to claim 1, further comprising a fourth logic unit for driving the second match line according to a comparison result. The first logic unit includes first and second transistors connected in series between the power line and the first match line,
The second logic unit includes third and fourth transistors connected in series between the power line and the first match line,
The third logic unit includes fifth and sixth transistors connected in series between the power line and the second match line,
The fourth logic unit includes seventh and eighth transistors connected in series between the power line and the second match line,
Gates of the first and fifth transistors are connected to a node where the first cell holds information;
The gates of the third and seventh transistors are connected to a node where the second cell holds information;
A gate of the second transistor is connected to one of the first search line pair;
A gate of the fourth transistor is connected to the other of the first search line pair;
A gate of the sixth transistor is connected to one of the second search line pair;
The semiconductor device according to claim 4, wherein a gate of the eighth transistor is connected to the other of the second search line pair. The second cell is adjacent to the first cell in the first direction;
A first bit line pair extending along the second direction and connected to the first cell;
A second bit line pair extending along the second direction and connected to the second cell;
A word line extending along the first direction and connected to both the first and second cells;
The first cell is
A first inverter having an input connected to a first storage node connected to the gates of the first and fifth transistors and an output connected to a second storage node;
A second inverter having an input connected to the second storage node and an output connected to the first storage node;
A ninth transistor of the first conductivity type having one end connected to the first storage node, the other end connected to one of the first bit line pair, and a gate connected to the word line;
A tenth transistor of a first conductivity type having one end connected to the second storage node, the other end connected to the other of the first bit line pair, and a gate connected to the word line;
The second cell is
A third inverter having an input connected to a third storage node connected to the gates of the third and seventh transistors and an output connected to a fourth storage node;
A fourth inverter having an input connected to the fourth storage node and an output connected to the third storage node;
An eleventh transistor of the first conductivity type having one end connected to the third storage node, the other end connected to one of the second bit line pair, and a gate connected to the word line;
A first conductivity type twelfth transistor having one end connected to the fourth storage node, the other end connected to the other of the second bit line pair, and a gate connected to the word line;
In the direction in which the word line extends, a second conductivity type first region, the first conductivity type second region, the second conductivity type third region, and the first conductivity type fourth region, , The fifth region of the second conductivity type is formed in order,
The first region includes the ninth and tenth transistors, a first conductivity type thirteenth transistor constituting the first inverter, and a first conductivity type fourteenth transistor constituting the second inverter. Arranged,
In the second region, a second conductivity type 15th transistor constituting the first inverter and a second conductivity type 16th transistor constituting the second inverter are arranged,
In the third region, the first to eighth transistors of the first conductivity type are disposed,
In the fourth region, a second conductivity type 17th transistor constituting the third inverter and a second conductivity type 18th transistor constituting the fourth inverter are arranged,
The fifth region includes the eleventh and twelfth transistors, a first conductivity type 19th transistor constituting the third inverter, and a first conductivity type 20th transistor constituting the fourth inverter. The semiconductor device according to claim 5 arranged. The second cell is adjacent to the first cell in the first direction;
A first bit line pair extending along the second direction and connected to the first cell;
A second bit line pair extending along the second direction and connected to the second cell;
A word line extending along the first direction and connected to both the first and second cells;
The first cell is
A first inverter having an input connected to a first storage node connected to the gates of the first and fifth transistors and an output connected to a second storage node;
A second inverter having an input connected to the second storage node and an output connected to the first storage node;
A ninth transistor of the first conductivity type having one end connected to the first storage node, the other end connected to one of the first bit line pair, and a gate connected to the word line;
A tenth transistor of a first conductivity type having one end connected to the second storage node, the other end connected to the other of the first bit line pair, and a gate connected to the word line;
The second cell is
A third inverter having an input connected to a third storage node connected to the gates of the third and seventh transistors and an output connected to a fourth storage node;
A fourth inverter having an input connected to the fourth storage node and an output connected to the third storage node;
An eleventh transistor of the first conductivity type having one end connected to the third storage node, the other end connected to one of the second bit line pair, and a gate connected to the word line;
A first conductivity type twelfth transistor having one end connected to the fourth storage node, the other end connected to the other of the second bit line pair, and a gate connected to the word line;
A second conductivity type first region, the first conductivity type second region, and the second conductivity type third region are sequentially formed in a direction in which the word line extends,
The first region includes the ninth and tenth transistors, a first conductivity type thirteenth transistor constituting the first inverter, and a first conductivity type fourteenth transistor constituting the second inverter. Arranged,
The second region includes a second conductivity type 15th transistor constituting the first inverter, a second conductivity type 16th transistor constituting the second inverter, and the second conductivity type first to first transistors. An eighth transistor, a second conductivity type seventeenth transistor constituting the third inverter, and a second conductivity type eighteenth transistor constituting the fourth inverter;
The third region includes the eleventh and twelfth transistors, a first conductivity type 19th transistor constituting the third inverter, and a first conductivity type 20th transistor constituting the fourth inverter. The semiconductor device according to claim 5 arranged. The second cell is adjacent to the first cell in the second direction;
A bit line pair extending along the second direction and connected to both the first and second cells;
A first word line extending along the first direction and connected to the first cell;
A second word line extending along the first direction and connected to the second cell;
The first cell is
A first inverter having an input connected to a first storage node connected to the gates of the first and fifth transistors and an output connected to a second storage node;
A second inverter having an input connected to the second storage node and an output connected to the first storage node;
A ninth transistor of the first conductivity type having one end connected to the first storage node, the other end connected to one of the bit line pair, and a gate connected to the first word line;
A first conductivity type tenth transistor having one end connected to the second storage node, the other end connected to the other of the bit line pair, and a gate connected to the first word line;
The second cell is
A third inverter having an input connected to a third storage node connected to the gates of the third and seventh transistors and an output connected to a fourth storage node;
A fourth inverter having an input connected to the fourth storage node and an output connected to the third storage node;
An eleventh transistor of the first conductivity type having one end connected to the third storage node, the other end connected to one of the bit line pair, and a gate connected to the second word line;
A first conductivity type twelfth transistor having one end connected to the fourth storage node, the other end connected to the other of the bit line pair, and a gate connected to the second word line;
A first region of a second conductivity type, a second region of the first conductivity type, and a third region of the second conductivity type are sequentially formed in the extending direction of the first and second word lines,
The first region includes the ninth and eleventh transistors, a first conductivity type thirteenth transistor constituting the first inverter, and a first conductivity type fourteenth transistor constituting the second inverter. Arranged,
In the second region, the second conductivity type 15th transistor constituting the first inverter, the second conductivity type 16th transistor constituting the second inverter, and the second inverter constituting the third inverter. A conductive type 17th transistor and a second conductive type 18th transistor constituting the fourth inverter are disposed;
The third region includes the first conductivity type first to eighth transistors, the tenth and twelfth transistors, the first conductivity type 19th transistor constituting the third inverter, and the fourth conductivity type. The semiconductor device according to claim 5, wherein a twentieth transistor of a first conductivity type constituting an inverter is disposed.   The semiconductor device according to claim 8, wherein at least one of the first to twentieth transistors is configured by a multi-gate transistor. A first local wiring connecting a diffusion layer shared by the eleventh transistor and the nineteenth transistor and a gate of the eighteenth transistor;
A second local wiring connecting a diffusion layer shared by the ninth transistor and the thirteenth transistor and a gate of the sixteenth transistor;
A third local wiring connecting a diffusion layer shared by the twelfth transistor and the twentieth transistor and a gate of the seventeenth transistor;
The semiconductor device according to claim 8, further comprising a fourth local wiring that connects a diffusion layer shared by the tenth transistor and the fourteenth transistor and a gate of the fifteenth transistor. A first power line connected to the first cell and the second cell;
A second power line connected to the first logic unit and the second logic unit;
A third power line connected to the third logic unit and the fourth logic unit;
A first switch connecting the first power line and the second power line;
A second switch for connecting the first power line and the third power line;
The first switch is set to on when the first data is searched, and is turned off when the first data is not searched.
5. The semiconductor device according to claim 4, wherein the second switch is set to be on when the second data is searched and is turned off when the second data is not searched. 6. A data cell configured to hold 1-bit information;
First and second match lines extending along a first direction;
A first search line pair extending along a second direction orthogonal to the first direction and transmitting the first data during the first data search;
A second search line pair extending along the second direction and transmitting second data during second data search;
The first match line is connected to the first search line pair and the first match line, and is based on a comparison result between the information held in the data cell and the first data transmitted to the first search line pair. A first logic cell that drives
The second match line is connected to the second search line pair and the second match line, and is based on a comparison result between information held in the data cell and second data transmitted to the second search line pair. And a second logic operation cell for driving the semiconductor device. A bit line pair extending along the first direction and connected to the data cell;
A word line extending along the first direction and connected to the data cell;
The first logical operation cell is:
Connected between the first match line and the power supply line and transmitted to one search line of the first search line pair and information held in the first storage node of the data cell at the time of the first data search. A first logic unit for driving the first match line according to a comparison result with the information to be performed;
Connected between the first match line and the power supply line, and transmitted to the other search line of the first search line pair and information held in the second storage node of the data cell at the time of the first data search A second logic unit for driving the first match line according to a comparison result with information to be performed,
The second logical operation cell is:
Information that is connected between the second match line and the power supply line and is stored in the first storage node and transmitted to one search line of the second search line pair during the second data search. A third logic unit for driving the second match line according to the comparison result with
Information that is connected between the second match line and the power supply line, and that is stored in the second storage node and transmitted to the other search line of the second search line pair during the second data search And a fourth logic unit for driving the second match line according to the comparison result with
The first logic unit includes first and second transistors connected in series between the power line and the first match line,
The second logic unit includes third and fourth transistors connected in series between the power supply line and the first match line,
The third logic unit includes fifth and sixth transistors connected in series between the power line and the second match line,
The fourth logic unit includes seventh and eighth transistors connected in series between the power line and the second match line,
Gates of the first and fifth transistors are connected to the first storage node;
Gates of the third and seventh transistors are connected to the second storage node;
A gate of the second transistor is connected to one of the first search line pair;
A gate of the fourth transistor is connected to the other of the first search line pair;
A gate of the sixth transistor is connected to one of the second search line pair;
A gate of the eighth transistor is connected to the other of the second search line pair;
The data cell is
A first inverter having an input connected to the first storage node and an output connected to the second storage node;
A second inverter having an input connected to the second storage node and an output connected to the first storage node;
A ninth transistor of the first conductivity type having one end connected to the first storage node, the other end connected to one of the bit line pair, and a gate connected to the word line;
A tenth transistor of a first conductivity type having one end connected to the second storage node, the other end connected to the other of the bit line pair, and a gate connected to the word line;
A second conductivity type first region, the first conductivity type second region, and the second conductivity type third region are sequentially formed in a direction in which the word line extends,
The first region includes the ninth and tenth transistors, a first conductivity type thirteenth transistor constituting the first inverter, and a first conductivity type fourteenth transistor constituting the second inverter. Arranged,
In the second region, a second conductivity type 15th transistor constituting the first inverter and a second conductivity type 16th transistor constituting the second inverter are arranged,
The semiconductor device according to claim 12, wherein the first to eighth transistors of the first conductivity type are disposed in the third region. A bit line pair extending along the first direction and connected to the data cell;
A word line extending along the first direction and connected to the data cell;
The first logical operation cell is:
Connected between the first match line and the power supply line and transmitted to one search line of the first search line pair and information held in the first storage node of the data cell at the time of the first data search. A first logic unit for driving the first match line according to a comparison result with the information to be performed;
Connected between the first match line and the power supply line, and transmitted to the other search line of the first search line pair and information held in the second storage node of the data cell at the time of the first data search A second logic unit for driving the first match line according to a comparison result with information to be performed,
The second logical operation cell is:
Information that is connected between the second match line and the power supply line and is stored in the first storage node and transmitted to one search line of the second search line pair during the second data search. A third logic unit for driving the second match line according to the comparison result with
Information that is connected between the second match line and the power supply line, and that is stored in the second storage node and transmitted to the other search line of the second search line pair during the second data search And a fourth logic unit for driving the second match line according to the comparison result with
The first logic unit includes first and second transistors connected in series between the power line and the first match line,
The second logic unit includes third and fourth transistors connected in series between the power supply line and the first match line,
The third logic unit includes fifth and sixth transistors connected in series between the power line and the second match line,
The fourth logic unit includes seventh and eighth transistors connected in series between the power line and the second match line,
Gates of the first and fifth transistors are connected to the first storage node;
Gates of the third and seventh transistors are connected to the second storage node;
A gate of the second transistor is connected to one of the first search line pair;
A gate of the fourth transistor is connected to the other of the first search line pair;
A gate of the sixth transistor is connected to one of the second search line pair;
A gate of the eighth transistor is connected to the other of the second search line pair;
The data cell is
A first inverter having an input connected to the first storage node and an output connected to the second storage node;
A second inverter having an input connected to the second storage node and an output connected to the first storage node;
A ninth transistor of the first conductivity type having one end connected to the first storage node, the other end connected to one of the bit line pair, and a gate connected to the word line;
A tenth transistor of a first conductivity type having one end connected to the second storage node, the other end connected to the other of the bit line pair, and a gate connected to the word line;
A first conductive type first region and a first conductive type second region are formed in a direction in which the word line extends;
The first region includes the ninth and tenth transistors, a first conductivity type thirteenth transistor constituting the first inverter, and a first conductivity type fourteenth transistor constituting the second inverter. Arranged,
The second region includes a second conductivity type 15th transistor constituting the first inverter, a second conductivity type 16th transistor constituting the second inverter, and the second conductivity type first to first transistors. The semiconductor device according to claim 12, wherein an eighth transistor is arranged.

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