JPH07193511A - Parallel/serial conversion circuit - Google Patents

Abstract

PURPOSE:To miniaturize a parallel/serial conversion circuit obtaining output data of variable byte width from input data of prescribed byte width. CONSTITUTION:A frame length counter 10 measures the pulse interval of a frame signal FS, identifies data width to be outputted and outputs a control signal CS corresponding to data width. A parallel/serial converter 40 in a prestage converts the input data signal ID of six byte width into the data signals MD1 and MD2 of first output byte width (two bytes). A parallel/serial converter 50 in a poststage converts the data signal MD1 into the data signal ND of second byte width (one byte). A data selector 60 selects either the data signal MD2 or ND in accordance with the control signal, and outputs it as an output data signal OD2 or OD1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel / serial conversion circuit, and more particularly to a circuit for performing a data width reduction conversion process in byte units of cell data for ATM (asynchronous transfer mode) exchange.

[0002]

2. Description of the Related Art In a cell data processing apparatus for ATM exchange, a 53-byte ATM cell is usually added with 1-byte dummy data to be 54 bytes, which is organized into a block of 9 × 6 bytes. Accordingly, it is converted into a block of 54 × 1 bytes (53 × 1 bytes when dummy data is deleted) or a block of 27 × 2 bytes, and then inversely converted and processed in synchronization with the frame pulse. When the period of the basic clock signal is T, the period of the frame pulse is 53T in the unit of 1 byte and 27T in the unit of 2 bytes. A parallel / serial conversion circuit is used to reduce the processing byte unit of data from a large value to a small value.

As shown in FIG. 2, a conventional parallel-serial conversion circuit is composed of a one-stage parallel-serial converter 70 having a fixed byte conversion ratio. If the output data width is varied, the output is performed. If so, a circuit is constructed for each variable width.

[0004]

SUMMARY OF THE INVENTION This conventional parallel
In the serial conversion circuit, when the data input with a constant input data width is output with the output data width changed, the reduction ratio of the data width cannot be changed according to the output data width. It is necessary to form a circuit for directly converting the output data width to the target output data width, and there is a problem that the device becomes large and the cost becomes high.

[0005]

The parallel-serial conversion circuit of the present invention is a parallel-serial conversion circuit for parallel-serial converting input data having a constant byte width to obtain output data having a variable byte width. The period of the input frame signal is measured by the basic clock according to the byte width to be output, and it is identified whether the byte width to be output is the first byte width or the second byte width smaller than this. A frame length counter that outputs a control signal indicating an identification result, a first parallel-serial converter that parallel-serial converts the input data and outputs the data as the first byte width data, and the first parallel-serial converter. A second parallel serial signal for parallel / serial converting the output data of the serial converter and outputting the data as the second byte width data. And Al converter, parallel the first in response to the control signal from the frame length counter
And a data selector for selecting one of the outputs of the serial converter and the second parallel / serial converter and outputting it as the output data of the variable byte width.

Further, a divided clock for synchronously outputting the output data of the first parallel-serial converter as the input of the second parallel-serial converter is generated by dividing the basic clock. A clock selector, and a clock selector that selects either the basic clock or the divided clock according to a control signal from the frame length counter and supplies the selected clock to the first parallel-serial converter. it can.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The input data width is 6 bytes (48 bits) and the output data width is 1 byte (8 bits) and 2 bytes (1 bit).
6 bit) variable case is shown. The data output cycle is constant at "T". That is, when the output data width is 1 byte, the data input speed is 6 bytes / 6T, and when the output data width is 2 bytes, the data input speed is 6 bytes /
It becomes 3T.

The parallel-serial conversion circuit of this embodiment determines the output data width by measuring the frame pulse interval of the frame signal FS input according to the variable output data width with the basic clock signal C1 of the cycle T. The frame length counter 10 that outputs the control signal CS indicating the determination result
And a clock frequency divider 20 for generating a frequency-divided clock signal C2 having a period 2T, which is obtained by frequency-dividing the clock signal C1 by two, and one of the input clock signal C1 and the frequency-divided clock signal C2 is selected according to the control signal CS. Clock selector 30
And a 6-byte unit input data signal ID (ID1: period 6T, ID2: period 3T) is parallel-serial converted according to the clock signal from the clock selector 30, and a 2-byte unit data signal MD (MD1: period 2T, MD
2: a first parallel / serial converter 40 which outputs as a cycle T) and a data signal MD1 in units of 2 bytes are parallel / serial converted according to an input clock signal C1.
A second parallel-serial converter 50 that outputs a byte-based data signal ND (cycle T), and a data signal M
A data selector 60 that selects either D2 or the data signal ND according to the control signal CS and outputs it as the output data signal OD2 in units of 2 bytes (cycle T) or the output data signal OD1 in units of 1 byte (cycle T). I have it. The clock frequency divider 20 can be included in the parallel / serial converter 50.

Next, the operation will be described.

The frame length counter 10 counts the frame pulse interval of the frame signal FS based on the clock signal C1 (cycle T), and the frame pulse interval is 27T.
In the case of, the data width of the output data signal is 2 bytes (OD
2), the control signal CS is output with a value indicating 2 bytes (for example, “1”), and when the frame pulse interval is 53T, the data width of the output data signal is 1 byte (OD1). It is determined and the control signal CS is output with a value indicating 1 byte (for example, "0").

When the control signal CS is "1" (output data width 2 bytes), the clock selector 30 selects the input clock signal C1 and the parallel / serial converter 40 outputs 2.
A byte-width data signal MD2 is output, and the data selector 60 selects this data signal MD2 and outputs it as an output data signal OD2.

When the control signal CS is "0" (output data width 1 byte), the clock selector 30 selects the divided clock signal C2, and the parallel / serial converter 40 outputs the data signal MD1. Serial converter 5
0 outputs the data signal ND which is obtained by reducing the data width of the data signal MD1 to 1 byte, and the data selector 60 selects the data signal ND and outputs it as the output data signal OD1.

That is, the present parallel-serial conversion circuit synchronizes the output data signals without supplying a control signal from the outside for identifying two kinds of data widths of the output data signals such as ATM cell data to be output. The output data width can be changed by recognizing the output data width specified autonomously inside the circuit using the input frame signal to change the serial connection combination of the parallel / serial converters. Can be Due to this, in the prior art, it is necessary to use two large-capacity converters for converting 6 bytes (48 bits) to 1 byte (8 bits) and 6 bytes to 2 bytes (16 bits), respectively. According to the present invention, one converter for converting from 6 bytes to 2 bytes may be provided, and one converter having a small capacity for converting from 2 bytes to 1 byte may be used.

[0015]

The parallel-serial conversion circuit of the present invention includes a first parallel-serial converter for converting input data into output data having a larger byte width of the byte width to be output, and a first parallel converter. A small parallel second serial-to-serial converter that converts data whose byte width is smaller than the input byte width by the serial converter to output data of another byte width to be output Since the data width to be output from the signal is autonomously recognized and the output of any one of the first and second parallel-serial converters connected in series is selected, the output data of the variable byte width is obtained. It is possible to downsize and prevent the apparatus from becoming large and the cost from increasing. Further, since the control circuit for externally instructing the data width to be output is not required, the device configuration is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional parallel-serial conversion circuit.

[Explanation of symbols]

 10 frame length counter 20 clock divider 30 clock selector 40, 50 parallel / serial converter 60 data selector

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masato Sakamoto Inventor Masato Sakamoto, 4-28 Mita, Minato-ku, Tokyo NEC Communication Systems Co., Ltd.

Claims (2)

[Claims] 1. Input data having a constant byte width in parallel
In a parallel-serial conversion circuit that obtains output data of variable byte width by serial conversion, the cycle of the frame signal input according to the byte width of the output data to be output is measured with a basic clock, and the byte width to be output is A frame length counter for identifying whether it is a first byte width or a second byte width smaller than the first byte width and outputting a control signal indicating an identification result; and the first byte for parallel / serial conversion of the input data. A first parallel / serial converter for outputting as width data, and a second parallel / serial converter for performing parallel / serial conversion on output data of the first parallel / serial converter and outputting as second byte width data. A serial converter, and the first parallel-serial converter and the first parallel-serial converter in response to the control signal from the frame length counter. And a data selector that selects one of the outputs of the second parallel-serial converter and outputs it as the output data of the variable byte width, the parallel-serial conversion circuit. 2. A divided clock for synchronously outputting the output data of the first parallel-serial converter as an input of the second parallel-serial converter is generated by dividing the basic clock. A clock divider, and a clock selector that selects either the basic clock or the divided clock according to a control signal from the frame length counter and supplies the selected clock to the first parallel-serial converter. The parallel / serial conversion circuit according to claim 1.