JPH07193234A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To simultaneously perform the reduction in the manufacturing process number of an insulation gate field effect type transistor of a buried channel structure insulating gate and a short channel effect suppression. CONSTITUTION:The previous buried channel and source - drain regions, or a buried channel region and an LDD region are replaced with one impurity region 4 or 9. It can be realized by shallowing the depth of a buried region and heightening concentration. This manufacturing method is characterized by integrally forming the buried channel and the source - drain regions (a) or the buried channel and LDD regions (b) formed separately before are integrally formed at the time of forming the buried channel so that the process number reduction can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a buried channel structure insulated gate field effect transistor having an impurity layer of the same conductivity type as a source / drain region (hereinafter referred to as a buried layer) immediately below a gate insulating film, the impurity distribution of the buried layer and the source / drain region The relationship of the impurity distribution of the drain region is related to the present invention, which will be described.

Conventionally, the impurity distribution in the buried layer and the impurity distribution in the source / drain regions have been designed independently.
The reason for this is that the buried layer is introduced into the transistor in order to set the threshold voltage of the transistor to a desired value and the source / drain regions are formed in the transistor to form electrodes for external connection of the transistor. This is because the purpose is different in the first place. Usually, the concentration of the source / drain region is set to the highest concentration within an allowable range determined by the short channel effect or the like in order to reduce the parasitic resistance. Therefore, the concentration of the source / drain region is higher than that of the buried layer.

On the other hand, when the so-called short channel effect such as the decrease of the threshold voltage and the deterioration of reliability due to the miniaturization of the transistor becomes remarkable, the source / drain regions are offset to solve the problem. An LDD structure insulated gate field effect transistor has been invented which is composed of a high concentration part of the structure and a low concentration part following it. The low concentration source / drain region concentration of the LDD structure transistor is designed to be thinner than the conventional high concentration region, but is still higher than the concentration of the buried layer.

[0005]

Although the performance of the insulated gate field effect transistor has been improved by miniaturization, the problem of short channel effect has become apparent as the miniaturization progresses. Although the short channel effect has been reduced by adopting the LDD structure and the like, this has led to an increase in the number of manufacturing steps.
An example of the number of manufacturing steps of an LSI using insulated gate field effect transistors is about 150 or more for N-channel transistors, and about 250 for complementary transistors having N-channel and P-channel transistors in the substrate. More than a process. In this way LSI
The enormous number of steps required for manufacturing increases the manufacturing period and cost. Therefore, it is desired to provide a semiconductor device and a method of manufacturing the same that can reduce the number of steps.

It is an object of the present invention to form a buried layer and a source of an insulated gate field effect transistor manufactured in a buried channel.
An object of the present invention is to provide a semiconductor device which is resistant to a short channel effect and which can easily reduce the manufacturing steps by improving the impurity distribution in the drain region, and a manufacturing method thereof.

[0007]

In order to solve the above problems, a semiconductor device according to the present invention has a buried channel structure insulated gate having an impurity layer of the same conductivity type as a source / drain region in a semiconductor substrate region immediately below a gate insulating film. In the field-effect transistor, the source / drain and the semiconductor region directly under the gate insulating film have the same impurity distribution, or the source / drain region is composed of a high-concentration part of an offset structure and a low-concentration part following it. The low-concentration source / drain portion and the impurity distribution directly under the gate insulating film are made the same.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming an impurity layer of a reverse conductivity type with a semiconductor substrate to be a buried channel and source / drain regions later by using ion implantation, selective epitaxial growth, or the like. However, it does not have a step of forming a high concentration source / drain region or a low concentration source / drain region thereafter.

[0009]

4 (a) and 4 (b) show an example of the distribution of impurities along the direction from the source to the drain in the interface of the gate insulating film and the distribution of impurities in the direction of the depth from the interface of the gate insulating film in the channel region. Show. The dotted line is the conventional LDD
As can be seen from FIG. 4A, the impurity concentration of the buried layer in the channel region is lower than that of the low-concentration source / drain region (LDD region) in the impurity distribution of the structure. On the other hand, the solid line represents the impurity distribution of the present invention, which is characterized in that the buried layer and the low-concentration source / drain regions have substantially the same concentration. However, if the impurity concentration of the buried layer is simply increased to form the distribution shown in FIG. 4A, the threshold voltage fluctuates, and the on / off control of the transistor becomes difficult. Therefore, as shown in FIG. 4B, the impurity distribution in the depth direction of the channel region is changed. The embedding depth is set to be the deepest within the range where the on / off control of the transistor can be performed.
From the viewpoint of transistor control, it is desirable to make the buried layer depth shallow, but since the buried layer depth and the source / drain depth are made the same in the structure of the present invention, if it is too shallow, the source / drain resistance increases. This is because the current driving capability of the transistor is reduced. The threshold voltage is controlled by changing the well concentration immediately below the buried layer. The well concentration is increased to keep the threshold voltage constant. The structure of the present invention is suitable for miniaturization, since increasing the well concentration inevitably brings about improvement in the short channel effect.

With respect to the structure of the present invention, if the buried channel is modulated by the gate, the LDD region may be depleted to have a high resistance, or if the concentration is increased to make the LDD region have a low resistance, the buried channel becomes. There may be doubts that it will not be modulated.
In order to prevent the LDD region from being depleted, the buried layer depth is set to LD.
Make the band flat near the surface of the D area,
In addition, in the channel region, it may be set so that the vicinity of the surface is depleted due to the work function difference with the gate. Regarding the concentration, if it is too thin, the resistance in the LDD region becomes too high to make it practically unusable, and if it is too thick (-10 ²⁰ cm ^-3
Above), degeneration occurs and the Fermi level is pinned, so the channel cannot be modulated. However, although the range may be narrow, there are buried layer depths and concentrations that satisfy the conditions of the present invention. The LD at that time is shown in FIGS.
The band diagram in the depth direction in the D region and the channel region is shown. The band becomes flat on the surface of the LDD region, and since the LDD concentration is -10 ¹⁸ cm ^-3 or more, it functions sufficiently as a low concentration source / drain. In the channel area,
The gate and channel work function differences deplete the channel surface, turning off the transistor.

Next, the insulated gate field effect transistor having the structure of the present invention and how the manufacturing method thereof works to reduce the number of manufacturing steps will be described by using a conventional buried channel structure complementary transistor manufacturing method. Explain. FIG. 6A shows a stage in which the P well 2, the N well 12, and the element isolation oxide film 3 are formed on the P type silicon substrate 1. Next, a window is opened only in the region of the P well 2 by using a mask process,
A punch-through stopper is formed by ion implantation of boron fluoride, and an N-type buried layer 13 for adjusting the threshold voltage is formed by ion implantation of arsenic (FIG. 6B). Further, a window is opened only in the region of the N well 12 by using a mask process, and a punch-through stopper for the P-channel type transistor and a P-type buried layer for adjusting the threshold voltage are formed by ion implantation with arsenic and boron fluoride. 14 is formed (FIG. 6C). Subsequently, the gate electrode 7 is formed by forming the gate oxide film 6, depositing and patterning the gate electrode material (FIG. 6D). Next, a window is opened only in the P well 2 region, and arsenic is ion-implanted to form an N-type low-concentration source / drain region (LDD region) for an N-channel transistor.
15 is formed (FIG. 6E). Next, a window is opened only in the region of the N well 12 by a mask process, and boron fluoride ion implantation is performed to form a P-type low-concentration source / drain region (LDD region) 16 for the P-channel transistor (FIG. 6 (f). )). Next, HTO (High Tewpe
After depositing the rfture oxide film,
The sidewall 11 is formed by anisotropic etching. After that, by using the same method as that for forming the LDD region, a high-concentration N-type impurity region 5 and a high-concentration N-type impurity region 5 to be high-concentration source / drain regions for the N-channel transistor and the P-channel transistor are formed by two masking steps and ion implantation. A P-type impurity region 17 is formed (FIG. 6G). Next, the interlayer insulating film 8 is deposited on the entire surface, and contact holes are formed by a mask process and etching. Then, after aluminum for wiring is sputtered on the entire surface, an aluminum wiring 9 is formed by a mask process and etching to obtain a final device structure (FIG. 6H).

In the conventional structure, the buried layer in the channel portion and the low-concentration source / drain regions have different impurity distributions, so that it is necessary to form them individually as described above. On the other hand, in the structure of the present invention, since the impurities in the buried layer and the low-concentration source / drain regions are made the same, the low-concentration source / drain regions are collectively formed when the buried layer is formed.
The mask process for forming the low concentration source / drain can be omitted twice, and the number of manufacturing processes can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A structural diagram of FIGS. 1 (a) and 1 (b) and FIG.
3A, 3B, and 3A to 3D, the structure of an insulated gate field effect transistor according to the present invention and the manufacture in the case of an N channel type MOS transistor will be described. An example of the method will be described.

First, a method of manufacturing a transistor not including LDD will be described. FIG. 2A shows a stage in which a P well 2 having a boron concentration of 5 × 10 ¹⁶ cm ⁻³ and an element isolation oxide film 3 are formed on a P-type silicon substrate 1. Next, a high concentration P well 4 having a thickness of 20 nm and a boron concentration of 1.15 × 10 ²⁰ cm ⁻³ is grown by selective epitaxial growth. Next, a high-concentration N-type impurity region 5 to be a buried layer and a source / drain region is formed. For use as a source / drain region, the arsenic concentration is, for example, 5 × 10 ¹⁹ c
^{Thicken to} about m ^-3 . The thickness of the impurity region is determined according to the threshold voltage and the set values of the source / drain parasitic resistance, and is set to 10 nm, for example. Here, the high-concentration well and the buried layer are formed by selective epitaxial growth, but other impurity introduction methods such as ion implantation may be used as long as the same distribution can be formed. Next, a gate oxide film 6 having a thickness of 5 nm is formed, and a gate electrode 7 is formed by depositing and patterning a gate electrode material (FIG. 2B).

Next, the interlayer insulating film 8 is deposited on the entire surface to a thickness of, for example, 0.5 μm, a heat treatment is performed at 800 ° C. for 20 minutes, and then a contact hole is formed by a mask process and etching.
Next, after aluminum for wiring is sputtered on the entire surface, patterning is performed to form aluminum wiring 9, whereby a final device structure (FIG. 1A) can be obtained. In the case of this embodiment, the threshold voltage, which is one of the important parameters of the transistor, is about 0.3 V, and even if the buried layer concentration is increased, the threshold voltage equivalent to that of the conventional structure can be set. it can.

Next, a method of manufacturing a MOS transistor including LDD will be described. FIG. 3A shows a P-type silicon substrate 1 and a P well 2 having a boron concentration of 5 × 10 ¹⁶ cm ^−3.
This is the stage of forming the element isolation oxide film 3. Next, by selective epitaxial growth, the thickness is 20 nm and the boron concentration is 2 × 1.
A high concentration P well 4 of 0 ¹⁸ cm ^-3 is grown. Next, a low-concentration N-type impurity region 10 to be a buried layer and a low-concentration source / drain region (LDD region) is formed. The arsenic concentration is set to about 2 × 10 ¹⁸ cm ⁻³ for use as the low concentration source / drain regions. The thickness of the impurity region is determined according to the threshold voltage and the set values of the source / drain parasitic resistance, and is set to 10 nm, for example. Here, the high-concentration well and the buried layer are formed by selective epitaxial growth, but other impurity introduction methods such as ion implantation may be used as long as the same distribution can be formed. next,
A gate oxide film 6 having a thickness of 5 nm is formed, and a gate electrode 7 is formed by depositing and patterning a gate electrode material (FIG. 3B). Next, an HTO film is deposited on the entire surface, and a sidewall 11 is formed beside the gate electrode by an etch back process (FIG. 3C). Next, an offset high-concentration N-type impurity region 5 is formed by arsenic ion implantation (FIG. 3).
(D)). Next, the interlayer insulating film 7 is deposited on the entire surface to a thickness of 0.5 μm, for example, and a contact hole is formed by an asking step and etching. Next, after sputtering aluminum for wiring on the entire surface, patterning is performed to form aluminum wiring 9,
The final device structure (FIG. 1 (b)) can be obtained. In the case of the present embodiment, the threshold voltage, which is one of the important parameters of the transistor, is about 0.3 V, and even if the buried layer concentration is increased, the threshold voltage equivalent to that of the conventional structure can be set. it can.

An embodiment of an insulated gate field effect transistor having the structure of the present invention is shown in FIGS. 1 (a) and 1 (b). This is an exemplary embodiment of the method of manufacturing an insulated gate field effect transistor of the present invention.

Although the N-channel type transistor and the manufacturing method thereof are shown in the present embodiment, the present invention is obviously not peculiar to the N-channel type transistor and is generally used for P-channel type transistor and complementary type transistor. All insulated gate field effect transistors applicable to insulated gate field effect transistors, and therefore using the principles of the present invention, and methods of making the same are within the scope of the present invention.

[0019]

As described above, by using the transistor structure and the manufacturing method thereof according to the present invention, a transistor having a strong short-channel effect can be manufactured in a smaller number of steps than in the past, so that the manufacturing period and cost can be reduced. it can. In particular, when the present invention is applied to a complementary transistor, the mask process can be reduced twice, which is effective.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of the structure of a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a schematic cross-sectional view showing the manufacturing method of the present invention.

FIG. 4 is a diagram showing an example of impurity distribution in a conventional buried channel structure and the structure of the present invention.

FIG. 5 is a band diagram in the depth direction in the LDD region and the channel region in the structure of the present invention.

FIG. 6 is a diagram showing an example of a manufacturing procedure of a conventional buried channel structure semiconductor device.

[Explanation of symbols]

 1 P-type silicon substrate 2 P-well 3 Element isolation oxide film 4 High-concentration P-well 5 High-concentration N-type impurity region 6 Gate oxide film 7 Gate electrode 8 Interlayer insulating film 9 Aluminum wiring 10 Low-concentration N-type impurity 11 Sidewall 12 N well 13 N type buried layer 14 P type buried layer 15 N type low concentration source / drain region 16 P type low concentration source / drain region 17 High concentration P type impurity region 18 Photoresist

Claims (6)

[Claims] 1. A buried channel structure insulated gate field effect transistor having an impurity layer of the same conductivity type as a source / drain region in a semiconductor substrate region immediately below a gate insulating film, wherein a source / drain and a semiconductor region directly below the gate insulating film are formed. A semiconductor device having the same impurity distribution. 2. The source / drain region is composed of a high-concentration portion of the offset structure and a low-concentration portion following the offset structure, and the low-concentration source / drain portion has the same impurity distribution immediately below the gate insulating film. The semiconductor device according to. 3. The semiconductor device according to claim 1, wherein the embedding depth is deep within a range where ON / OFF control of the transistor can be performed. 4. The semiconductor device according to claim 3, wherein the threshold voltage is controlled by increasing the concentration of a layer having a conductivity type opposite to that of the buried layer, which is directly below the buried layer. 5. A step of forming an element isolation region in a semiconductor substrate and then forming a buried channel and an impurity layer of a reverse conductivity type with a semiconductor substrate to be a source / drain region later by ion implantation or selective epitaxial growth. The method for manufacturing a semiconductor device is characterized in that the source / drain region forming step is not performed thereafter. 6. In a field effect transistor including a low concentration source / drain region, after forming an element isolation region on a semiconductor substrate, ion implantation selective epitaxial growth or the like is used to form a buried channel and a low concentration source / drain region later. It has a step of forming a reverse-conductivity type impurity layer with the semiconductor substrate, and then does not carry out a low-concentration source / drain region forming step, and subsequently uses a sidewall to form an offset structure high-concentration source / drain region forming step A method for manufacturing a semiconductor device, comprising: