JPH07193202A - Gate array - Google Patents

Abstract

PURPOSE:To define the final function in an interconnection layer step after forming a chip divided at a region where a gate pattern suited to realize functions in the least areas every function block is regularly lengthwise and crosswise formed. CONSTITUTION:A base chip 101 is divided into a random logic block 111, data puss block 112, ROM block 113 and RAM block 114, each having a block- inherent gate pattern regularly arranged lengthwise and crosswise. The chip completes logic functions by adding interconnection layers. The blocks 111, 112, 113 and 114 are composed of a random logic gate pattern 121, data path gate pattern 122, data gate pattern 123 and RAM gate pattern 124, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array, and more particularly to a gate array in which the chip size can be easily optimized when the product is commercialized.

[0002]

2. Description of the Related Art The basic gate of a conventional gate array has a driving force of a transistor in the basic gate because it is unknown what kind of driving force is required and what kind of circuit is used. It is designed with a margin, and is also designed with an extra number of transistors in the basic gate.

By arranging such basic gates without a gap, for example, a base chip of a gate array called a gate spread type is constructed. The manufacturer prepares several types of base chips with different numbers of basic gates and provides them to customers (hereinafter referred to as users).

A user selects a base chip having an optimal number of gates from a base chip prepared in advance by a manufacturer, completes circuit design, and then provides wiring between basic gates to form a desired circuit.

The advantage of the gate array is that the delivery time is short because the construction period for producing the IC after the design is completed is only a few steps after the metal layer.

[0006] Further, there is an embedded array which is an improved version of the gate array, in which a part of the spread gate is replaced with a functional block called a macro cell or the like to provide a dedicated function such as a microcomputer, a DSP or an analog circuit. Is something that can be done.

Before starting the design, the user selects the macro cell to be used. The manufacturer creates a special base chip that incorporates macrocells on the base chip of a normal gate array while the user is designing. At the end of design, the user wires the completed base chip.

By adopting such a procedure, it is possible to obtain a highly functional IC as a normal gate array during the development period seen from the user.

[0009]

In the gate array, when the basic gates are connected to form a circuit, some of the basic gates are used as a wiring area, and therefore, the total number of gates and circuit elements are used. At present, the implementation rate, which is the ratio of the number of gates, cannot be increased so much.

Further, the base chip prepared by the manufacturer has a limited number of gates, and it is not always the case that the number of gates is as desired by the user, and a large one must be used. In other words, if the base chip prepared by the manufacturer is, for example, 1K gate, 5K gate, and 10K gate, and the circuit scale designed by the user is 2K gate including the gate used as the wiring area, As a result, the thing of 5K gate must be used, and 3K gate is wasted.

Further, even for the transistors in the basic gate, even if the driving force and the number of transistors are not required for the above-mentioned reason, a constant driving force and number are prepared, and there is much waste.

As described above, in the conventional gate array, there are many wastes such as the mounting rate, the chip size (gate scale), and the gate size, and these wastes become a factor that hinders the cost reduction at the time of commercialization.

[0013]

[Means for Solving the Problems] Instead of using a base chip prepared in advance like a conventional gate array, the circuit is divided into blocks for each function at the time of circuit design,
Consider in advance how much gate driving force is required for each block. For example, in a circuit group generally called a data path such as an ALU, a multiplexer, a register, etc., each gate is not usually required to have a large driving force, so that the basic gate can be realized by a transistor having a small area. Further, since various memory devices have clear gate connections and the required number of transistors, it is possible to realize a circuit with an optimized gate pattern with less waste. By assigning the basic gates, which have been optimized to some extent, to the respective parts, and then creating a dedicated base chip, the above problems are solved.

[0014]

[Operation] An IC is formed by the gate array having the structure as in the present invention.
By creating, it is possible to realize an IC that is more advantageous in area and power consumption than conventional ones.

[0015]

EXAMPLES Examples of the present invention will be described below.

In the following, the process used in the LSI manufacturing will be described by taking the ordinary CMOS technology as an example, but the concept of the present invention is not limited to it.

FIG. 1 is a diagram showing a structure of a base chip of a gate array according to the present invention. Here, the base chip is a chip in a state before the wiring layer is provided. The entire chip 101 includes a random logic block 111, a data path block 112, a ROM block 113,
It is divided into a RAM block 114. Inside each block, gate patterns peculiar to each block are regularly arranged vertically and horizontally. The base chip shown in FIG. 1 completes its logical function by adding a wiring layer.

The random logic block 111 is a random logic gate pattern 121, and the data path block 112 is a data path gate pattern 122.
Therefore, the ROM block 113 is composed of the ROM gate pattern 123, and the RAM block 114 is composed of the RAM gate pattern 124.

The data path means a multiplier, ALU,
Refers to the functional block of the arithmetic system that calculates data such as registers. In the data path, the signal is N bits (N
(= 16, 24, 32, etc.) The calculation is performed in units of collected words, and at that time, normally, a block for performing processing for each bit in the direction perpendicular to the data flow appears repeatedly for N bits. And the number of signal lines spanning between bits is usually smaller than the number of signal lines in the data flow direction. In this way, since the wiring direction is biased in one direction and is frequently repeated, the wiring pattern is regular. Therefore, the load wiring length is generally short, and the load driving capability required for the gate is also small. On the other hand, in a block other than the operation system in the logic circuit, that is, a block handling a control signal, the direction and the appearance of the signal line are irregular, so that it is called random logic.

FIG. 2 shows the structure of the random logic gate pattern 121. The N-diffusion layer 201, four polysilicon gates 202 arranged across the N-diffusion layer 201, the P-diffusion layer 203, It is composed of four polysilicon gates 204 arranged across the P-diffusion layer 203 and an N-well 205 surrounding the P-diffusion layer 203.

FIG. 3 shows the structure of a 4-input NAND gate realized by adding a wiring layer to the random logic gate pattern 121. Random logic gate pattern 1
Reference numeral 21 indicates an N-diffusion layer 201 and a P-diffusion layer 203, each of which has four polysilicon gates.
AND and NOR gates can be configured. 30 in the figure
1, 302, 303, 304 are four signal input terminals, 3
Reference numeral 05 is a signal output terminal. Further, 306 is a power source (VD
D) line and 307 are ground (GND) lines. Note that 311
Is a contact between the diffusion layer and the aluminum wiring layer, and 312 is a contact between the polysilicon gate layer and the aluminum wiring layer.

FIG. 4 shows an equivalent circuit diagram of the 4-input NAND gate of FIG.

FIG. 5 shows the structure of the gate pattern 122 for the data path 1 gate. As with FIG. 2, four polysilicon gates 502 are arranged across the N-diffusion layer 501 and the N-diffusion layer 501. , P-diffusion layer 503, four polysilicon gates 504 arranged across the P-diffusion layer 503, and an N-well 5 surrounding the P-diffusion layer 503.
However, the width of each of the N-diffusion layer 501 and the P-diffusion layer 503 is small. The reason why the diffusion layer width of the data path is smaller is that the load path of the data path is generally smaller than that of the random logic, and the load driving capability required for the gate is also smaller.

FIG. 6 shows the structure of the ROM gate pattern 123. The N-diffusion layer 601 and the N-diffusion layer 601 are shown in FIG.
Two polysilicon gates 602 disposed across the
Composed of and.

FIG. 7 shows the structure of a ROM cell (for 2 bits) realized by adding a wiring layer to the ROM gate pattern 123. In the figure, 701 and 702 are word lines, and 703 is V.
A DD side bit line, 704 is a GND side bit line. In the same figure, portions 705 and 706 are portions of aluminum wiring for writing cell data, and when they exist, "1" is written, and when they are missing, "0" is written.

FIG. 8 shows an equivalent circuit of a 1-bit NOR type ROM (horizontal ROM) using the ROM cell of FIG.

RAM gate pattern 124 shown in FIG.
FIG. 4 shows the structure of the structure shown in FIG. 1, in which four polysilicon gates 902, P-diffusion layers 903, and P-diffusion layers 903 are arranged across the N-diffusion layer 901 and the N-diffusion layer 901. It is composed of two polysilicon gates 904 and an N-well 905 surrounding the P-diffusion layer 903, but the widths of the N-diffusion layer 901 and the P-diffusion layer 903 are each smaller. Is.

FIG. 10 shows the structure of a STATIC RAM1 cell realized by adding a wiring layer to the RAM gate pattern 124. In the figure, 1001 and 1002 are true and complementary data lines, 1003 is a word line, 1004 is a power supply (VDD) line, and 1005 is a ground (GND) line.

FIG. 11 shows an equivalent circuit of the RAM cell of FIG.

What is important here is that a gate pattern forming a random logic block, a gate pattern forming a data path block, a gate pattern forming a ROM block, and a gate pattern forming a RAM block are respectively represented. This means that different characteristic patterns are provided to achieve the desired functions with the minimum area. At the same time, since the final logic function is realized in the wiring layer, if the required function cannot be completed in each block when the logic design is completed, other blocks must be used to realize the lacking function. Is possible.

First, FIG. 12, FIG. 13, FIG. 14, and FIG. 15 show the method of arranging the wiring layers when realizing the original random logic using the random logic gate pattern and realizing the data path, ROM, and RAM. Are shown respectively.

First, FIG. 12 shows a wiring pattern when an original random logic is realized by using a random logic gate pattern.
Is a gate, 1202 is a wiring in the X direction, and 1203 is a wiring in the Y direction. In random logic, the wiring density in any direction is not particularly low.

FIG. 13 shows a wiring pattern when a data path is realized by using a random logic gate pattern. In FIG. 13, 1201 is a gate pattern,
1302 is a wiring in the X direction, and 1303 is a wiring in the Y direction. Here, it is assumed that the direction of data flow is the X direction.
Since the data path has a small number of signals for calculation between bits, the density of the wirings 1303 in the Y direction perpendicular to the data flow becomes small. Further, since the wiring length is generally short, the density of the wirings 1302 in the X direction is also small.

FIG. 14 shows a wiring pattern when a 2-bit ROM cell is realized by using a random logic gate pattern. In FIG. 14, 1401 and 1402 are word lines, 1403 is a VDD side bit line, and 1404 is a line. GN
It is a D-side bit line. In the figure, portions 1405 and 1406 are aluminum wiring portions for writing cell data, and if they exist, "1" is written, and if they are missing, "0" is written.

FIG. 15 shows a wiring pattern when one bit of a RAM cell is realized by using a gate pattern for random logic. In FIG. 15, 1501 and 1502 are true and complementary data lines, and 1503 is a word. Line, 15
Reference numeral 04 is a power supply (VDD) line and 1505 is a ground (GND) line.

As described above, the data path and each of the ROM and RAM cells can be realized by using the gate pattern for the random logic. However, in the case of the data path, the vacant area of the wiring area is large, and in the case of each of the ROM and RAM cells, the area is several times larger than when using the gate patterns specific to the ROM and RAM shown in FIGS. You can see that

On the contrary, FIG. 16 shows a method of arranging the wiring layers when the original data path is realized by using the data path gate pattern and the random logic is realized. In the figure, 1601 is a gate, 1602 is an X-direction wiring, and 1603 is a Y-direction wiring.

In this case, the number of unusable gate patterns increases due to lack of the wiring area, and it is necessary to use a part of the gates for the buffer in order to drive a long wiring length. When the original random logic gate pattern is used, the occupied area becomes larger than that in FIG.

It is also possible to realize a gate for a data path or random logic by using a RAM gate pattern. Since the gate pattern for one bit of the RAM cell includes two PMOSs and four NMOSs, a 2-input NAND or 2-input NOR1 gate can be constructed. FIG. 17 shows a wiring layer arranging method in this case. In the figure, 1701 and 1702 are two signal input terminals, 170
3 is a signal output terminal. 1704 is a power source (VD
D) line, 1705 is a ground (GND) line.

However, since the gate width of the RAM gate pattern is narrow, it is necessary to use some RAM gate patterns for the buffer when the load driving capability is small and the load is large.

As described above, according to the present invention, if a required function cannot be completed in a certain block, it is possible to realize the insufficient function by using another block. Therefore, random logic, data path, ROM , RAM size need only be roughly allocated at the stage of creating a base chip. Of course, if the original function can be completed in each block, the chip can be configured with the minimum area. However, the number of gates and RO required when the design is not completed
It is difficult to accurately determine the M and RAM sizes.
Therefore, if it is attempted to start the creation of the base chip at the stage where the design is not completed and to complete the original function in each block, it becomes necessary to give redundancy to the size of each block, and eventually the chip size and Power consumption becomes excessive.

FIG. 18 shows the design procedure of the gate array of the present invention in comparison with the conventional one. Previously, functional design was completed (180
1) and when the approximate number of gates can be estimated (180
Select the base chip from the standard product group in 2) (1803)
Was. Then, when the logic design is completed (1804)
Then, a step of designing an aluminum wiring layer pattern based on the logic and arranging the wiring layer pattern on the base chip (180
5) was performed and the chip was completed (1806).

On the other hand, in the present invention, the functional design is completed.
(1811) Then, when it becomes possible to roughly estimate the functional block size (1812), a wafer is mounted on which a chip including functional blocks of a size with a slight margin to the estimated size is mounted. Start (1813). Most of the wafer creation process is up to the base chip creation stage (1814) for creating a polysilicon gate, so the logic design is completed.
After (1815), the wiring layer is determined and the wiring layer process (18
By executing step 16), it is possible to realize a chip that has the same construction period as the conventional gate array from the user's point of view, and has the area and power consumption that are close to those of a custom design.

[0044]

As described above, according to the present invention, when the functional design is completed, a base chip having a gate pattern necessary for realizing a functional block of a size with some margin in the estimated size is provided. After starting the creation and completing the logic design, only the wiring layer process can be executed to complete the chip, so the construction period seen from the user is the same as that of the conventional gate array, and the area and power consumption are close to those of the custom design. A high-performance chip can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a base chip of a gate array according to the present invention.

FIG. 2 is a configuration diagram of a gate pattern for random logic.

FIG. 3 is a configuration diagram of a 4-input NAND gate.

FIG. 4 is an equivalent circuit diagram of a 4-input NAND gate.

FIG. 5 is a configuration diagram of a gate pattern for a data path.

FIG. 6 is a configuration diagram of a ROM gate pattern.

FIG. 7 is a configuration diagram of a ROM cell.

FIG. 8 is an equivalent circuit diagram of a ROM.

FIG. 9 is a configuration diagram of a RAM gate pattern.

FIG. 10 is a configuration diagram of a RAM cell.

FIG. 11 is an equivalent circuit diagram of a RAM cell.

FIG. 12 is a wiring diagram of a random logic.

FIG. 13 is a wiring diagram of a data path.

FIG. 14 is a wiring diagram of a ROM cell.

FIG. 15 is a wiring diagram of a RAM cell.

FIG. 16 is a wiring diagram of a data path.

FIG. 17 is a configuration diagram of a 2-input NAND gate.

FIG. 18 shows a gate array design procedure.

[Explanation of symbols]

101 ... Entire base chip of gate array according to the present invention, 111 ... Random logic block, 112 ... Data path block, 113 ... ROM block, 11
4 ... RAM block, 121 ... Random logic gate pattern, 122 ... Data path gate pattern,
123 ... ROM gate pattern, 124 ... RAM gate pattern, 201 ... N-diffusion layer, 202 ... Polysilicon gate, 203 ... P-diffusion layer, 204 ... Polysilicon gate, 205 ... N-well, 301, 302, Thirty
3, 304 ... Signal input terminal, 305 ... Signal output terminal, 3
06 ... Power (VDD) line, 307 ... Ground (GND) line, 31
1 ... Contact between diffusion layer and aluminum wiring layer, 312 ... Contact between polysilicon gate layer and aluminum wiring layer, 501
... N-diffusion layer, 502 ... Polysilicon gate, 503 ...
P-diffusion layer, 504 ... Polysilicon gate, 505 ... N
-Well, 601 ... N-diffusion layer, 602 ... polysilicon gate, 701, 702 ... word line, 703 ... VDD side bit line, 704 ... GND side bit line, 705, 706
... Aluminum wiring for writing cell data, 901 ... N-diffusion layer, 902 ... Polysilicon gate, 903 ... P-diffusion layer, 904 ... Polysilicon gate, 905 ... N-well, 1001 ... True data line, 1002 ... Complementary data line, 1003 ... Word line, 1004 ... Power supply (VDD) line,
1005 ... Ground (GND) line, 1201 ... Gate, 120
2 ... Wiring in X direction, 1203 ... Wiring in Y direction, 1302
... X-direction wiring, 1303 ... Y-direction wiring, 1401,
1402 ... Word line, 1403 ... VDD side bit line, 1
404 ... GND side bit line, 1405, 1406 ... Aluminum wiring for writing cell data, 1501 ... True data line, 1502 ... Complementary data line, 1503 ... Word line, 1
504 ... Power supply (VDD) line, 1505 ... Ground (GND) line,
1601 ... Gate, 1602 ... Wiring in X direction, 1603
... Wiring in the Y direction, 1701, 1702 ... Signal input terminals,
1703 ... Signal output terminal, 1704 ... Power supply (VDD) line,
1705 ... Ground (GND) line, 1801 ... Functional design, 18
02 ... Gate number estimation, 1803 ... Base chip selection, 1
804 ... Complete logic design, 1805 ... Wiring layer process, 1806
... Chip completion, 1811 ... Function design, 1812 ... Function block scale estimation, 1813 ... Wafer creation start, 1814
… Completion of base chip, 1815… Completion of logic design, 181
6 ... Wiring layer process, 1817 ... Chip completion.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takanori Shimura 1-280 Higashi Koikekubo, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Yoichi Shiraishi 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Takashi Akazawa 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Mitsuru Hiraki 1-280, Higashi Renegakubo, Kokubunji, Tokyo Hitachi Ltd. (72) Inventor Atsushi Kiuchi 1-280, Higashi Koigokubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory

Claims (7)

[Claims] 1. A gate array which realizes a desired function by producing a base chip in which a large number of basic gate patterns composed of a single transistor or a plurality of transistors are arranged and connecting the gate patterns using a wiring layer. A gate array in which a user can configure a base chip by using one or more types of basic gate patterns. 2. In an application-specific IC, even when a process such as a diffusion layer in an initial step is required to realize a desired function, a user can design a desired circuit by designing only a wiring layer. An application-specific IC that can be realized. 3. As the basic gate pattern according to claim 1, in addition to a basic gate pattern for general logic circuits, a gate pattern that does not require a driving force, a gate pattern suitable for realizing a memory circuit, etc. are prepared. A gate array that is characterized. 4. A gate array which realizes a desired function by producing a base chip in which a large number of basic gate patterns composed of a single transistor or a plurality of transistors are arranged and connecting the gate patterns using a wiring layer. A gate array, wherein a base chip is prepared using a plurality of types of dedicated gate patterns according to claim 3. 5. The gate array according to any one of claims 1 to 3, wherein a macro cell can be mounted. 6. A gate array designing method, characterized in that, in a wiring designing method of a gate array, a data path section and a random logic section are separated, and wiring designing and layout are performed individually for each section. 7. A gate array which realizes a desired function by producing a base chip in which a large number of basic gate patterns composed of a single transistor or a plurality of transistors are arranged and connecting the gate patterns using a wiring layer. , A gate array characterized in that the user can freely optimize the size of the base chip.