JPH07183374A - Manufacture of dielectric isolating substrate - Google Patents

Abstract

PURPOSE:To reduce chip size and to simplify the manufacturing method by joining first and second semiconductor substrates directly, and removing the first semiconductor substrate of the joined substrate until the row part of a plurality of grooves in a apace provided inside the joined substrate appears. CONSTITUTION:An oxidizing gas is let in a space 16 provided inside a joined substrate composed of first and second semiconductor substrates 11 and 14 joined directly together, through a plurality of grooves 13a..., 13f,... of the space 16, as the grooves 13a,... 13f,... are connected to an external atmosphere on the main surface side of the joined substrare 15. As a result, an air passage for letting in the oxidizing gas becomes unnecessary, and it facilitates layout design. When the joined substrate 15 is left alone in an oxidizing atmosphere, the oxidizing gas is applied to the inside of the space 16 through the groove row. Accordingly, it becomes easy for the oxidizing gas to enter the inside of the space 16, and an oxide film 17 grows sufficiently and the space is buried with the oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate for forming a semiconductor device, and more particularly to a method for manufacturing a dielectric isolation substrate in which a dielectric layer is formed inside the bonded substrate by a direct bonding technique of the substrates. It is a thing.

[0002]

2. Description of the Related Art An intelligent power IC is a typical device that combines different functions of a power device and a control circuit into one chip. As a problem in realizing such one-chip, there are electric interference between the power device and the control circuit, temperature rise of the control circuit due to heat generation of the power device, and the like. Separation technology between the power device and the control circuit has become an important technology for compounding. As an element isolation structure that solves the above problems,
Several types of partial SOI structures have been proposed. An example thereof is a manufacturing process diagram (part 1) of FIG. 15, FIG. 16 and FIG.
This will be described in (2) and (3). In the figure, (4) of FIG. 16 is shown in a partially cutaway perspective view, and the other figures are shown in sectional views.

As shown in (1) of FIG. 15, a part of the main surface side of the first semiconductor substrate 301 is selectively etched by chemical etching or reactive ion etching,
For example, the first groove 302 having a depth of about 0.6 μm is formed.

Next, as shown in FIG. 15B, second grooves 303 and 304 are formed in the first semiconductor substrate 301 along both side walls of the first groove 302 by, for example, chemical etching or reactive ion etching. Form. Second above
The grooves 303 and 304 have, for example, a width of 90 μm and a depth of 17
It is set to μm.

Subsequently, a laminating step shown in FIG. 15C is performed. In this step, the main surface side of the first semiconductor substrate 301 and the main surface side of the second semiconductor substrate 305 are cleaned and activated. After that, the main surfaces of the first and second semiconductor substrates 301 and 305 are brought into close contact with each other, and, for example, 1
A high temperature heat treatment is performed at 100 ° C. for about 60 minutes. Then, the first and second semiconductor substrates 301 and 305 are directly bonded to form a bonded substrate 306. Therefore, FIG.
6 (4), the first groove 302 and the second groove 302
The grooves 303 and 304 serve as holes 307 penetrating the inside of the bonded substrate 306.

Further, as shown in FIG. 16 (5), the inside of the hole 307 is formed by leaving the bonded substrate 306 in an oxidizing atmosphere (eg, an atmosphere containing oxygen) at 900 ° C. for about 60 minutes. Pass oxidizing gas through. Then, the inner wall of the hole 307 is oxidized to form the oxide film 308. At this time, the first groove (302) is filled with the oxide film 308 because the gap between the first semiconductor substrate 301 and the second semiconductor substrate 305 is narrow. On the other hand, the second groove (30
3) and (304) have holes 307 surrounded by an oxide film 308.
Remains. The heat treatment conditions are set so that the first groove 302 is filled with the oxide film 308.

Next, as shown in (6) of FIG. 16, the first semiconductor substrate 301 forming the bonding substrate 306 is formed by polishing, for example, until the hole 307 is exposed.
Oxide film 30 in the portion indicated by the dashed line and the portion indicated by the dashed line 1
8 and are removed. Then, the oxide film 3 is formed on the bonding substrate 306.
Element forming regions 309 and 310 separated by 08 are formed. The element forming regions 309 and 310 are formed on the first semiconductor substrate 301.

Thereafter, as shown in FIG. 17 (7), polycrystalline silicon is deposited by, for example, a CVD method to fill the inside of the hole 307 and to form the bonded substrate 306.
A polycrystalline silicon layer 311 is formed on top.

Then, as shown in (8) of FIG. 17, the polycrystalline silicon layer 311 embedded in the hole (307) is left by a polishing method, for example, to leave a portion of the polycrystalline silicon layer 311 indicated by a chain double-dashed line. To remove. In this way
A dielectric isolation substrate 300 is formed in which element formation regions 309 and 310 electrically isolated by the oxide film 308 and the polycrystalline silicon layer 311 are provided on the second semiconductor substrate 305. Then, the oxide film 308 and the remaining polycrystalline silicon layer 3
11 and 11 become element isolation regions 312.

Here, the element forming region 310 formed of the first semiconductor substrate 301 having the junction between the first semiconductor substrate 301 and the second semiconductor substrate 305 becomes the power element forming region. Further, the element formation region 309 formed of the first semiconductor substrate 301 separated from the second semiconductor substrate 305 by the oxide film 308 and the polycrystalline silicon layer 311 serves as a control element formation region.

[0011]

However, in the manufacturing method described in the above-mentioned conventional technique, (5) in FIG.
As described above, it is necessary to supply an oxidizing gas (for example, oxygen) to the inside of the hole (307) through the hole (307). Therefore, in order to fill the narrow portion of the hole (307) with the oxide film (308), the second groove (303, 30)
It is necessary to design the width of 4) to be about 90 μm or wider. And this second groove (303, 30
Since the width of 4) defines the width of the element isolation region (312), the chip size becomes very large.

Further, since the hole (307) must be formed from the side end portion of the bonding substrate (306), the degree of freedom in pattern layout is extremely reduced. As a result, the chip size is increased, and the number of chips that can be taken from one bonded substrate (306) is reduced. As a result, the chip cost increases. Furthermore, in the above-mentioned conventional manufacturing method,
Manufacturing costs are high because two polishing steps are required.

It is an object of the present invention to provide a method for manufacturing a dielectric isolation substrate which has a reduced chip size and a simplified manufacturing method.

[0014]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a dielectric isolation substrate, which has been made to achieve the above object. That is, in the first step, a concave portion is formed at a predetermined position of the first semiconductor substrate, and then a groove array including a plurality of grooves deeper than the concave portion is formed on each side wall side thereof. Then, in a second step, the surface of the first semiconductor substrate on which the groove array is formed and the second semiconductor substrate are directly bonded to each other to form a bonded substrate. To form. Then, in a third step, the first semiconductor substrate of the bonded substrate is removed until the groove array portion of the space is exposed. Then, in a fourth step, the bonded substrate is left in an oxidizing atmosphere to grow an oxide film on the inner wall of the space, thereby filling the space with the oxide film and forming an oxide layer on the surface of the bonded substrate. Then, in a fifth step, by removing the oxide layer to expose the first semiconductor substrate, a first element formation region made of the first semiconductor substrate separated from the second semiconductor substrate by the dielectric layer of the oxide film, A second semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate bonded to each other
An element formation region is formed.

In the first step, as a first method, after forming a concave portion at a predetermined position of the first semiconductor substrate, a groove array consisting of a plurality of grooves deeper than the concave portion is formed on each side wall side thereof. To do. At that time, (a) the groove widths of the respective grooves are set to be substantially equal and wider than the depth value of the concave portion. (B) The interval between the grooves in the groove row direction is set to be narrower than 0.818 times the groove width. Each groove is formed under such conditions. After that, each process from the second process to the fifth process is performed.

In the first step, as a second method, after forming a concave portion at a predetermined position of the first semiconductor substrate, a groove array consisting of a plurality of grooves deeper than the concave portion is formed on each side wall side thereof. Form a row. At this time, (f) each groove is set to have substantially the same groove width and wider than the depth value of the concave portion. (G) The interval between the grooves in the groove row direction is 0.818 of the groove width.
Set narrower than double. (H) The interval between the parallel groove rows is set to be narrower than 0.818 times the groove width. (Vi) The interval between the groove rows arranged in positions where the grooves in the groove rows are arranged substantially orthogonal to each other is set to be narrower than 0.818 times the groove width. Each groove is formed under such conditions.
Then, each process from the 2nd process to the 5th process is performed.

In the first step, as a third method, after forming a concave portion at a predetermined position of the first semiconductor substrate, a groove array consisting of a plurality of grooves deeper than the concave portion is formed on each side wall side thereof. Form a row. At this time, the groove widths of the (c) grooves are set to be substantially equal to each other in the groove row direction and wider than the depth of the concave portions. (Vi) The groove width of the central row of each groove row is set narrower than the groove width of the groove rows on both sides. (S) The interval between the grooves in each groove row direction is set to be narrower than 0.818 times the groove width. (C) The width of the convex portion between the parallel groove rows is set to be 0.409 times smaller than the sum of the groove widths of the groove rows that sandwich the convex portion. (B) The spacing between the groove rows arranged at positions adjacent to each other in which the groove array directions of the groove rows are substantially orthogonal to each other is 0.
Set narrower than 818 times. Each groove is formed under such conditions. Then, each process from the 2nd process to the 5th process is performed.

In the first step, the first method is the fourth method.
After forming the concave portion at a predetermined position of the semiconductor substrate, a groove array consisting of a plurality of grooves deeper than the concave portion is formed on each side wall of the concave portion.
Form a row. At that time, (a) the groove width of each groove is set to be substantially equal in the groove row direction and wider than the depth value of the concave portion. (H) The interval between the grooves in each groove row direction is 0.81 of the groove width.
Set narrower than 8 times. Further, k is an arbitrary natural number satisfying 2 ≦ k <n, and the convex portion between the groove row of the k−1th row and the groove row of the kth row is defined as the convex portion of the k−1th row. ) K-
The width of the convex portion of the first row is set to be smaller than 0.409 times the sum of the groove width of the groove row of the k-1th row and the groove width of the groove row of the kth row, and 0.818 of the groove width of the groove row in the eye
Set wider than double. Furthermore, (g) The groove width of the k-th groove row is set to be wider than the k-1th groove row and narrower than the n-th groove row. Each groove is formed under such conditions. Then, each process from the 2nd process to the 5th process is performed.

In the first step, as a fifth method, a concave portion is formed at a predetermined position of the first semiconductor substrate, and then each side wall side thereof is formed in a direction substantially perpendicular to the side wall of the concave portion. A plurality of grooves deeper than the concave portion are formed in n rows. At that time, k is an arbitrary natural number satisfying 2 ≦ k <n, and the convex portion between the groove of the k−1th row and the groove of the kth row is the convex portion of the k−1th row, and ( The width of the convex portion in the (k-1) th row is set to be narrower than 0.409 times the sum of the groove width of the groove in the (k-1) th row and the groove width in the (k) th row, and k- It is set wider than 0.818 times the groove width of the groove in the first row. (D) The groove width of the kth row groove is set to be wider than the k-1th row groove width, narrower than the nth row groove width, and wider than the recessed portion depth.
Each groove is formed under such conditions. Then the second
Each step from the step to the fifth step is performed.

In the first step, as a sixth method, a first groove array consisting of m first grooves arranged in parallel with each other is formed in the recessed portion forming region set at a predetermined position of the first semiconductor substrate. The second groove array including the second groove of the m-th row is provided at a symmetrical position and is continuous with both ends of each first groove of the first groove array and both ends of each second groove of the second groove array. Providing the third groove, the first
A concave portion including a groove row, a second groove row, and a third groove is formed.
At that time, a portion between the first groove of the first row of the first groove row and the second groove of the first row of the second groove row is defined as the convex portion of the first row. Also, j is 2
As an arbitrary natural number ≦ j <m, the first groove in the j-th column and j
The first convex portion of the jth row is formed between the first groove of the −1st row and the second groove of the jth row is formed between the second groove of the jth row and the second groove of the j−1th row. 2 to be a convex portion. Then, (c) the groove width of the first groove in the j-th row is set to be wider than the groove width of the first groove in the (j-1) -th row and narrower than the groove width of the first groove in the m-th row. The width of the second groove is set to be wider than the width of the second groove in the j−1th row and narrower than the width of the second groove in the mth row, and the depth of each first groove and each The depth of the two grooves is set deeper than the groove width of the third groove.
(H) The width of the first convex portion in the j-th column is set to be wider than the width of the first convex portion in the (j−1) th column and narrower than the width of the first convex portion in the m-th column. Similarly, the width of the second convex portion in the jth column is set to be wider than the width of the second convex portion in the j−1th column and narrower than the width of the second convex portion in the mth column. (F) The width of the convex portion in the first row is set to be narrower than 0.409 times the sum of the first groove in the first row and the second groove in the first row. (F) The width of the first convex portion in the j-th row is 0. The sum of the groove width of the first groove in the (j-1) -th row and the groove width of the first groove in the j-th row.
The width is set to be narrower than 409 times and wider than 0.818 times the groove width of the first groove in the (j−1) th row.
Similarly, the width of the second convex portion in the j-th row is set to be smaller than 0.409 times the sum of the groove width of the second groove in the (j-1) -th row and the groove width of the second groove in the j-th row. At the same time, it is set to be wider than 0.818 times the groove width of the second groove in the (j-1) th row. (E) The groove width of the third groove is set to be equal to or wider than the groove width of the first groove in the m-th row or the groove width of the second groove in the m-th row, and the depth of the third groove is It is set deeper than the groove width of the third groove. By setting such conditions, a concave portion including the first groove row, the second groove row, and the third groove is formed. Subsequently, a groove array is formed along the outer circumference of the concave portion, which is continuous with the upper portion of the concave portion and has a plurality of grooves deeper than that. Then, each process from the 2nd process to the 5th process is performed.

[0021]

In the method of manufacturing the dielectric isolation substrate, the first semiconductor substrate and the second semiconductor substrate are directly bonded to each other, and the plurality of groove portions of the space provided therein remove a part of the first semiconductor substrate. As a result, the main surface side of the bonded substrate is in a state of communicating with the external atmosphere. Then, the oxidizing gas is introduced into the space through the plurality of groove portions. For this reason, it is not necessary to form a long ventilation path for introducing the oxidizing gas into the surface of the bonded substrate as in the conventional case, so that the layout design is facilitated.

When the bonded substrate is left in an oxidizing atmosphere, the oxidizing gas is supplied into the space through a plurality of groove portions formed on the main surface side of the bonded substrate. It becomes easier for gas to enter. For this reason,
The oxide film grows sufficiently inside the space to fill the space with the oxide film. At the same time, the first semiconductor substrate between the grooves is also oxidized, so that the groove array becomes a dielectric layer made of an oxide film. In this way, the first element formation region formed of the first semiconductor substrate separated from the second semiconductor substrate by the dielectric layer, and the second element formation region formed of the first semiconductor substrate and the second semiconductor substrate bonded to each other. And are formed.

According to the first method in the above-mentioned first step, when forming a groove array consisting of a plurality of grooves deeper than the concave portion,
Since the groove width of each groove is set to be substantially equal and wider than the depth value of the concave portion, before each groove is filled with the oxide film,
The concave portion of the space is filled with an oxide film. Since the distance between the grooves in the groove row direction is set to be narrower than 0.818 times the groove width, the inside of each groove is filled with an oxide film without any gap, and the first semiconductor substrate between the grooves is completely oxidized. To be done.
Therefore, the dielectric layer formed of the generated oxide film includes the first element formation region formed of the first semiconductor substrate separated from the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate bonded to each other. A second element formation region is formed.

In the second method in the first step, when forming two rows of grooves each having a plurality of grooves deeper than the recessed portions, the groove widths of the respective grooves are substantially equal and the depth of the recessed portions is set to a value. Since the width is set wider, the concave portion of the space is filled with the oxide film before each groove is filled with the oxide film. Then, the interval between the grooves in the groove row direction is set to be narrower than 0.818 times the groove width, and the distance between the parallel groove rows is set to 0.818 of the groove width.
The width of each groove is set to be narrower than double, and the interval between the groove rows that are arranged in positions adjacent to each other in which the groove array directions of the groove rows are substantially orthogonal to each other is set to be narrower than 0.818 times the groove width. The inside is filled with an oxide film without a gap, and the first semiconductor substrate between the grooves and between the groove rows is completely oxidized. Therefore, the first and second element forming regions are formed in the same manner as above.

The oxidation of the semiconductor substrate between the grooves in the first and second methods will be described. Usually, when a silicon substrate is used as a semiconductor substrate, if the surface of the silicon substrate is oxidized to form an oxide film, about 45% of the thickness of the oxide film is formed inside the silicon substrate. A thickness of 55% of the film thickness is formed on the surface of the silicon substrate before oxidation. Oxidation from the groove side to the silicon substrate stops when the inside of the groove is filled with an oxide film. From the above conditions, in order to grow the oxide film to completely fill the inside of the groove and completely oxidize the silicon substrate between the grooves, the interval between the grooves should be set to be narrower than 0.818 times the groove width. Good. By setting the conditions in this way, the silicon substrate between the grooves in the groove row direction is first completely oxidized.
At this time, since the groove is not filled with the oxide film, the oxidation from the side surface of the groove progresses by continuing the oxidation, and the groove is eventually filled with the oxide film.

On the other hand, if the distance between the grooves is set to be 0.818 times the groove width or more, the grooves are first filled with the oxide film, so that an unoxidized region is formed in the first semiconductor substrate between the grooves.

According to the third method in the first step, when three rows of grooves each having a plurality of grooves deeper than the concave portion are formed, the groove widths of the respective grooves are substantially equal and the depth value of the concave portion is set. Since the width is set wider, the concave portion of the space is filled with the oxide film before each groove is filled with the oxide film. Since the interval between the grooves in each groove row direction is set to be narrower than 0.818 times the groove width, even if the first semiconductor substrate between the grooves in the groove row direction is completely oxidized, the groove is formed as an oxide film. Not embedded in.

Since the groove width of the central row of each groove row is set to be narrower than the groove width of the groove rows on both sides, the grooves of the central row are first filled with the oxide film. The groove of the groove row of is not filled with the oxide film. Then, by further continuing the oxidation, an oxide film grows from the outside of the groove on both sides, and the groove is completely filled with the oxide film.

Further, since the width of the convex portion between the groove rows is set to be smaller than 0.409 times the sum of the groove widths of the groove rows sandwiching the convex portion, the first semiconductor as described above is used. When the silicon substrate is used as the substrate, the film thickness condition of the oxide film formed on the first semiconductor substrate and the oxidation from the groove side to the first semiconductor substrate are stopped when the inside of the groove is filled with the oxide film. The oxide film is grown inside the groove under the condition that the groove is completely filled, so that the groove is completely filled with the oxide film. At the same time, the first semiconductor substrate between the groove rows is completely oxidized.

Furthermore, since the interval between the groove rows which are arranged in the positions where the grooves of the groove rows are substantially orthogonal to each other and adjacent to each other is set to be narrower than 0.818 times the groove width, the groove rows are oxidized. The first semiconductor substrate between the trench rows is completely oxidized before being filled with the film.

On the other hand, if the interval between the grooves in each groove row direction is set to 0.818 times the groove width or more, the grooves are first filled with the oxide film, and therefore the unoxidized region is formed in the first semiconductor substrate between the grooves. Cause Further, if the width of the convex portion between the groove rows is set to 0.409 times or more the sum of the groove widths of the groove rows sandwiching the convex portion, the groove is first filled with the oxide film. An unoxidized region is formed on the first semiconductor substrate.

In the fourth method in the above-mentioned first step, when forming n rows of a groove row consisting of a plurality of grooves deeper than the concave portion, the groove widths of the respective grooves are substantially equal to each other in the groove row direction and the concave portions are formed. Set wider than the depth value of. From this fact, the concave portion of the space is filled with the oxide film before each groove is filled with the oxide film. Then, the interval between the grooves in each groove row direction is set to be narrower than 0.818 times the groove width.
Similar to the method described above, the spaces between the grooves in the groove row direction are completely oxidized before the grooves are filled with the oxide film.

Further, the width of the convex portion in the (k-1) th column is k-1.
0.4 of the sum of the groove width of the groove row and the groove width of the k-th groove row
The width is set to be narrower than 09 times, wider than 0.818 times the groove width of the groove row in the (k-1) th row, and k
Since the groove width of the groove row of the 1st row is set to be wider than the groove width of the groove row of the (k-1) th row and narrower than the groove width of the groove row of the nth row, the convex portions in the 1st row are projected in order. The ridges are completely oxidized. At the same time, the trenches are sequentially filled with the oxide film from the first trench array. Then, when the convex portion in the n-th row is completely oxidized, the groove in the n-th row is not filled with the oxide film. Therefore, by further oxidizing, the oxidation progresses from the outside of the groove array to fill the groove in the n-th column with an oxide film.

On the other hand, when the interval between the grooves in each groove row direction is set to 0.818 times the groove width or more, the grooves are first filled with the oxide film, so that the unoxidized region is formed in the first semiconductor substrate between the grooves. Occurs. Further, if the width of the convex portion between the groove rows is set to 0.409 times or more the sum of the groove widths of the groove rows sandwiching the convex portion, the groove is first filled with the oxide film. An unoxidized region is formed on the first semiconductor substrate. Further, when the convex portion of the k-1th row is set to 0.818 times or less the groove width of the groove row in the k-1th row, the groove row of the k-1th row is not filled with the oxide film.

In the fifth method of the first step, since the groove width of each groove is set to be equal and wider than the depth value of the concave portion, the concave shape of the space is filled before each groove is filled with the oxide film. The part is filled with an oxide film. Then, the width of the convex portion in the (k-1) th row is set to be smaller than 0.409 times the sum of the groove width of the groove in the (k-1) th row and the groove width in the kth row, and k
The groove width of the groove in the -1st row is set to be wider than 0.818 times, and the groove width of the groove in the kth row is wider than the groove width of the groove in the k-1th row. Since the width is set narrower than the width, the convex portions are completely oxidized in order from the convex portion in the first row. At the same time, the trenches are sequentially filled with the oxide film from the first trench array. Then, when the convex portion in the n-th row is completely oxidized, the groove in the n-th row is not filled with the oxide film. Therefore, by further oxidizing, the oxidation progresses from the outside of the groove array to fill the groove in the n-th column with an oxide film.

On the other hand, if the width of the convex portion between each groove is set to 0.409 times or more the sum of the groove widths of the grooves sandwiching the convex portion, the groove is first filled with the oxide film, so that the groove array An unoxidized region is formed on the first semiconductor substrate in between. If the width of the convex portion in the k-1th column is set to 0.818 times or less the groove width of the groove in the k-1th column, the groove in the k-1th column is not filled with the oxide film.

In the sixth method in the first step, j
The groove width of the first groove (second groove) in the row is wider than the groove width of the first groove (second groove) in the row j−1, and the first groove (second groove) in the m-th row is used.
Set narrower than the groove width of (groove). From this, even if the first groove (second groove) of the row is completely filled with the oxide film,
The first groove (second groove) in the second and subsequent rows is not completely filled with the oxide film. In addition, the width of the first convex portion (second convex portion) in the j-th column is wider than the width of the first convex portion (second convex portion) in the (j-1) -th column, and The width is set to be narrower than the width of the first convex portion (second convex portion). From this, the first convex portion (second
Even if the convex portion) is completely oxidized, the first convex portion (second convex portion) in the next row and thereafter is not completely oxidized.

Furthermore, since the depth of the first and second grooves is set deeper than the groove width of the third groove, the first and second grooves are filled with the oxide film grown in the groove width direction.

The width of the convex portion in the first row is set to the first and second widths in the first row.
The width is set to be narrower than 0.409 times the sum of the groove widths. At the same time, the width of the first convex portion (second convex portion) in the j-th column is set to j−
The width of the first groove (second groove) in the first row and the first groove (second groove) in the jth row
The width is set to be 0.409 times smaller than the sum of the width of the first groove (groove) and 0.818 of the width of the first groove (second groove) in the j−1th row.
Set wider than double. From this, the first and second convex portions are completely oxidized in order from the convex portion in the first row, and the first and second grooves are oxidized in order from the first and second groove rows in the first row. Embedded in the membrane. Then, the oxidation of the first and second convex portions and the formation of the oxide film of the first and second grooves are alternately performed.

Then, the groove width of the third groove is set to be wider than the groove width of the first groove (or the second groove) in the m-th row. From this, the third groove is not filled with the oxide film when the first and second convex portions in the m-th row are completely oxidized. Therefore, by further oxidizing, the oxidation progresses from the outside of the third groove and the third groove is filled with the oxide film. Since the depth of the third groove is set deeper than the groove width of the third groove, the third groove is filled with the oxide film by the growth of the oxide film from the side wall direction. Then, a plurality of grooves which are continuous with the third groove and which are deeper than the concave portion are formed, and the groove row formed along the outer circumference of the concave portion is also filled with the oxide film.

On the other hand, the width of each first convex portion (second convex portion) is the first groove (second groove) sandwiching the first convex portion (second convex portion).
If it is set to 0.409 times the sum of the groove widths of
Since the groove (second groove) is filled with the oxide film, an unoxidized region is formed in the first convex portion (second convex portion). If the width of the first convex portion (second convex portion) in the j-th column is set to 0.818 times or less of the width of the first groove (second groove) in the j−1-th column, the first
The groove (second groove) is not completely filled with the oxide film. Further, the depth of each first groove (second groove) is determined by the depth of the first groove (second groove).
If the width is shallower than the width of, the oxide film is filled from the third groove side, so that a region not filled with the oxide film is generated on the center side of the concave portion.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to sectional views of manufacturing steps shown in FIG.

As shown in FIG. 1A, in the first step, an etching mask (not shown) made of, for example, a resist is formed on the first semiconductor substrate 11 by a lithography technique. The first semiconductor substrate 11 is made of, for example, a silicon substrate whose main surface is mirror-finished. After that, the concave portion 12 is formed at a predetermined position of the first semiconductor substrate 11 by, for example, chemical etching or reactive ion etching. The depth D of the concave portion 12 is set to, for example, about 1 μm. Then, the etching mask (not shown) is removed by, for example, an asher process or a wet etching process.

After that, as shown in FIG. 1B, an etching mask (not shown) made of, for example, a resist is formed by a lithography technique. Then, for example, by reactive ion etching, a plurality of grooves 13a, ... 13f deeper than the concave portion 12 are formed on each side wall of the concave portion 12.
.. are formed in the first semiconductor substrate 11. The depth H of the grooves 13a, ... 13f ,.
It is formed deeper than the depth D of the concave portion 12, for example, H
= 20 μm or so. Also, each groove width w
₁₁ is formed to have a thickness of, for example, about 4 μm.

Then, the second step shown in FIG. 1C is performed. In this step, depending on the wafer bonding method,
The first semiconductor substrate 11 having the groove array 13 and the second semiconductor substrate 14 are directly bonded to each other to form a bonded substrate 15. The second semiconductor substrate 14 is made of, for example, a silicon substrate whose main surface is mirror-finished.

Therefore, a space 16 composed of the concave portion 12 and the groove array 13 is formed inside the bonded substrate 15.

Subsequently, the third step shown in FIG. 1D is performed. In this step, the first semiconductor substrate 11 (portion indicated by a chain double-dashed line) of the bonding substrate 15 is removed by, for example, a grinding method and a polishing method until the groove array 13 is exposed. For example, the first semiconductor substrate 11 is removed by a grinding method until just before the groove rows 13 are exposed. Then, the first semiconductor substrate 11 is removed by a polishing method until the groove rows 13 are exposed. that time,
For example, rough polishing is performed by lapping, and final polishing is performed by mechanochemical polishing.

Then, the fourth step shown in FIG. 1 (5) is performed. In this step, as an oxidizing atmosphere, for example, a mixed gas of oxygen and hydrogen is pressurized to about 3 MPa and at 1100 ° C.
The bonding substrate 15 is placed in an atmosphere heated to about 4
By leaving it for 00 minutes, an oxide film 17 is grown on the inner wall of the space 16. Then, the space 16 is replaced with the oxide film 1
Embed with 7. At this time, the grooves 13a, ..., 13f,
Since each groove width w _{11 of} ... Is formed wider than the depth H of the concave portion 12, the concave portion 12 is first filled with the oxide film 17, and then the grooves 13a, ..., 13f ,. Is filled with the oxide film 17. Further, the oxide layer 18 is also formed on the surface of the first semiconductor substrate 11 of the bonding substrate 15.

Thereafter, the fifth step shown in FIG. 1 (6) is performed. In this step, a wet etching solution such as a hydrofluoric acid solution that etches an oxide film is used to remove the oxide layer 1 described above.
8 (the part indicated by the chain double-dashed line) is removed. Then, the first semiconductor substrate 11 is exposed. Therefore, the first element formation region 22 made of the first semiconductor substrate (11) separated from the second semiconductor substrate 14 is formed by the dielectric layer 21 made of the oxide film (17). At the same time, the second element forming region 23 including the first semiconductor substrate (11) and the second semiconductor substrate (14) bonded to each other is formed.

The dielectric isolation substrate 1 is formed as described above.

In the above embodiment, the description has been made by focusing on one concave portion 12, but a plurality of concave portions may be provided to form a plurality of first element forming regions.

In the above embodiment, the plurality of grooves 13a, ..., 13f in the space 16 provided inside the bonded substrate 15 in which the first semiconductor substrate 11 and the second semiconductor substrate 14 are directly bonded together.
Since the main surface side of the bonding substrate 15 is in a state of communicating with the external atmosphere, the plurality of grooves 13a, ...
The oxidizing gas is introduced into the space 16 through 13f. For this reason, it is not necessary to form a long ventilation path for introducing the oxidizing gas into the surface of the bonded substrate as in the conventional case, so that the layout design is facilitated.

When the connection substrate 15 is left in an oxidizing atmosphere, the oxidizing gas is supplied into the space 16 through the grooves 13a, ..., 13f ,.
Oxidizing gas easily enters the space 16. Therefore, the oxide film 17 grows sufficiently inside the space 16, and the space 16 is filled with the oxide film 17.

Further, a plurality of grooves 13 deeper than the concave portion 12 are formed.
Width w _{11 of} each groove 13a, ..., 13f, ..
, 13f, ... Are set to be substantially equal and wider than the depth D of the recessed portion 12, so that the recessed portion 12 of the space 16 is filled before the grooves 13a, ..., 13f ,.
Are filled with an oxide film 17. Therefore, the second semiconductor substrate 1 is formed by the dielectric layer 21 formed of the oxide film 17.
A first element formation region 22 formed of the first semiconductor substrate 11 separated from the substrate No. 4 and a second element formation region 23 formed by joining the first semiconductor substrate 11 and the second semiconductor substrate 14 are formed.

Next, an example of the groove array in the first embodiment will be described with reference to FIG.

As shown in FIG. 2 (1), the concave portion 1 is formed.
2 has a plurality of grooves 13a, 13b, 13 deeper than the concave portion 12 on the side walls 12a, 12b, 12c, 12d side.
A groove array 13 including c, 13d, 13e, 13f, 13g, and 13h is formed. Depth H of each groove 13a to 13h
Is formed deeper than the depth D of the concave portion 12, and is formed to have a depth of, for example, H = 20 μm. Also, groove width w ₁₁
Is formed to have a thickness of, for example, about 4 μm.

The groove array 13 is set as follows. (A) The groove width w ₁₁ of each of the grooves 13a to 13h of the groove array 13 is set to be substantially equal. (A) The groove interval L ₁₁ between the grooves 13a to 13h in the groove row 13 direction is set to be narrower than 0.818 times the groove width w. Therefore, the groove interval L ₁₁ is about 3.2 μ.
It is set to about m.

Therefore, after performing the oxidation step of the fourth step of the embodiment described in (5) of FIG. 1 above, the oxide layer (18) of the fifth step is removed, so that (2) of FIG. )
As shown in FIG. 5, the inside of each of the grooves 13a to 13h (the portion indicated by the chain double-dashed line) is filled with the oxide film 17 without any gap, and
The first semiconductor substrate 11 between the grooves 13a to 13h is completely oxidized to become the oxide film 17. At this time, the groove width w ₁₁ of the grooves 13a to 13h is the concave portion (12).
Since it is formed wider than the depth H, the concave portion (1
2) is filled with the oxide film 17, and then the grooves 13a to 13 are formed.
h is filled with the oxide film 17.

Next, each groove 13a in the direction of the groove array 13
The reason why the groove interval L ₁₁ of ˜13 h is set to be narrower than 0.818 times the groove width w ₁₁ will be described with reference to FIG.

As shown in FIG. 3A, when an oxide film 212 having a film thickness t is formed on the silicon substrate 211 by the thermal oxidation method, the thickness of the oxide film 212 is about 45.
% Is formed under the surface of the initial silicon substrate 211, and about 55% of the thickness of the oxide film 212 is known to be formed over the surface of the initial silicon substrate 211.

Therefore, as shown in (2) of FIG.
For example, in order to fill the grooves 221 and 222 with the oxide film 212, the width w ₂₁₁ of each groove 221, 222, the groove 221 and the groove 2
Let L ₂₁₁ be the distance from the groove 22 and t be the film thickness of the oxide film 212 (the portion indicated by the chain double-dashed line) to be formed.
In order to bury 2, the film thickness of the oxide film 212 needs to be at least w ₂₁₁ = 2 × 0.55t. Also, the groove 22
In order to oxidize the silicon substrate 211 between 1 and 222, the film thickness of the oxide film 212 is at least L ₂₁₁ = 2 × 0.45t.
Only needed. If the relationship between L ₂₁₁ and w ₂₁₁ is calculated using the above two equations, the relationship L ₂₁₁ = 0.818w _{211 can} be calculated. Therefore, the trenches 221 and 222 are formed in the oxide film 21.
To embed with 2, the groove spacing L ₂₁₁ should be at least narrower than 0.818w ₂₁₁ . That is, L
_The relation of ₂₁₁ <0.818w ₂₁₁ is obtained.

Next, although not shown, the method of bonding the wafers in the above manufacturing method will be specifically described. In addition, each component is described with the reference numeral used in FIG. 1 described above.

For example, a mixed liquid of ammonia (NH ₃ ), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O), hydrogen chloride (H 2
Cl), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O), a mixed solution of hydrofluoric acid (HF) and water (H ₂ O), and the like. The semiconductor substrates 11 and 14 are immersed to remove organic substances and metals attached to their respective surfaces.
Further, washing with pure water is performed.

After that, an oxidation treatment is performed to form a film having a thickness of several nm on the surfaces of the first and second semiconductor substrates 11 and 14.
Form a thin oxide film (not shown) to a degree. This oxidation treatment is performed by, for example, sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide solution (H ₂
It is performed by immersing in a mixed solution with O ₂ ). Then, in order to make it hydrophilic, it is washed with pure water.

Then, the first and second semiconductor substrates 11 and 14 are exposed to a dry nitrogen (N ₂ ) atmosphere.
After drying, the main surface of the first semiconductor substrate 11 and the main surface of the second semiconductor substrate 14 are brought into close contact with each other. At this time, the first semiconductor substrate 11 and the second semiconductor substrate 14 are bonded to each other by hydrogen bonds of silanol groups and water molecules generated on each main surface. Furthermore, nitrogen (N ₂ ) and argon (Ar)
By performing a heat treatment at a temperature of about 1100 ° C. for about 1 hour in an inert gas atmosphere such as the above, a dehydration condensation reaction occurs on the bonding surfaces of the first and second semiconductor substrates 11 and 14. And silicon and oxygen can be bonded. When the reaction further progresses, the oxygen is released to the first and second semiconductor substrates 1
The silicon diffuses into the inside of 1, 14 and bonds with each other. In this way, the first and second semiconductor substrates 11 and 14 are
The substrates are directly bonded to each other to form the bonded substrate 15.

Next, a second embodiment will be described with reference to sectional views of the manufacturing process of FIG. 4 and plan views of the manufacturing process of FIG.

As shown in (1) of FIG. 4, in the first step, the first semiconductor substrate 1 made of a silicon substrate whose main surface is mirror-polished in the same manner as described in (1) of FIG. 1 above.
An etching mask (not shown) made of a resist is formed on the surface 1 by a lithography technique. Then, for example by chemical etching or reactive ion etching,
The concave portion 12 is formed at a predetermined position on the first semiconductor substrate 11. The depth D of the concave portion 12 is set to, for example, about 1 μm. Then, the etching mask (not shown) is removed by, for example, an asher process or a wet etching process.

Then, as shown in (2) of FIG. 4 and (1) of FIG. 5, an etching mask (not shown) made of, for example, a resist is formed by a lithography technique. After that, for example, by reactive ion etching, the concave portion 12 is formed.
A groove array 31 including grooves 31a and 31b and a groove array 32 including grooves 32a and 32b are formed on the semiconductor substrate 11 on the side wall 12a side. Similarly, on the side wall 12b side of the concave portion 12, a groove array 33 and grooves 34a, 34b, which are formed by grooves 33a, 33b
and a groove array 34 formed of a groove b on the side wall 12c side.
A groove array 35 composed of a and 35b and a groove array 36 composed of grooves 36a and 36b are formed. Further, the groove 37 is formed on the side wall 12d side.
A groove array 37 including a and 37b and a groove array 38 including grooves 38a and 38b are formed. Each of the groove arrays 31 to 38 is formed deeper than the depth D of the concave portion 12, for example, the depth H is about 20 μm. The groove width w ₂₁ is formed to be, for example, about 2.0 μm.

The groove arrays 31 to 38 are designed under the following conditions.

(F) Grooves 31a-38a and 31b-
The groove width w _{21 of} 38b is set to be substantially equal. (G) The groove interval L ₂₁ in the groove rows 31 to 38 is set to be narrower than 0.818 times the groove width w. Therefore, the groove spacing L ₂₁ is set to about 1.6 μm, for example. (H) The interval L ₂₂ between the parallel groove arrays, for example, the groove array 31 and the groove array 32 is set to be narrower than 0.818 times the groove width w ₂₁ . Therefore, the groove row interval L ₂₂ between the groove rows 31 and 32 is set to about 1.6 μm. Similarly, the groove row spacing L ₂₃ between the groove row 33 and the groove row 34, the groove row spacing L ₂₄ between the groove row 35 and the groove row 36, and the groove row spacing ₂₅ between the groove row 37 and the groove row 38 are also the groove width w. Set narrower than 0.818 times ₂₁ . Therefore,
The groove row intervals L ₂₂ , L ₂₃ , L ₂₄ , and L ₂₅ are set to about 1.6 μm, for example. (X) Distance L between the groove array 32 and the grooves 33, 34, 37, 38
₂₆ is set to be narrower than 0.818 times the groove width w ₂₁ . The distance L ₂₇ between the groove array 36 and the grooves 33, 34, 37, 38 is set to be narrower than 0.818 times the groove width w ₂₁ . Therefore, the intervals L ₂₆ and L ₂₇ are set to the same value as the above L ₂₂ , for example.

Then, as shown in (3) of FIG. 4, a step similar to the second step described in (3) of FIG.
The first semiconductor substrate 11 and the second semiconductor substrate 14 are directly bonded to each other to form a bonded substrate 15. The second semiconductor substrate 14
Is made of, for example, a silicon substrate whose main surface is mirror-finished. Therefore, a space 39 including the concave portion 12 and the groove rows 31 to (38) is formed inside the bonded substrate 15.

Subsequently, the third step shown in FIG. 4 (4) is performed. In this step, the groove rows 31 to (3) are formed by, for example, a grinding method and a polishing method, as described in (3) of FIG. 1 above.
The first semiconductor substrate 11 (portion indicated by a chain double-dashed line) of the bonded substrate 15 is removed until 8) appears.

Then, the fourth step shown in (5) of FIG. 4 and (2) of FIG. 5 is performed. In this step, the oxide film 40 is grown on the inner wall of the space 39 in the same manner as described in (5) of FIG. Then, the space 39 is replaced with the oxide film 4
Embed with 0. At this time, the grooves 31a to 38a, 31b to
Since the groove width w ₂₁ of the groove 38b is formed wider than the depth D of the concave portion 12, the concave portion 12 is first filled with the oxide film 40, and then the grooves 31a to 38a and 31b to 38b are filled with the oxide film 40. Be done. Then, the oxide layer 41 is also formed on the surface of the first semiconductor substrate 11 of the bonding substrate 15. The oxide layer 41 in FIG. 5B is omitted.

Thereafter, the fifth step shown in FIG. 4 (6) is performed. In this step, the oxide layer 41 (the portion indicated by the chain double-dashed line) is removed by wet etching in the same manner as described in (6) of FIG. Then, the first semiconductor substrate 1
Show 1 out. In this way, the first element formation region 43 made of the first semiconductor substrate 11 separated from the second semiconductor substrate 14 is formed by the dielectric layer 42 made of the oxide film 40. At the same time, a second element forming region 44 composed of the first and second semiconductor substrates (11, 14) bonded to each other is formed.

In the second embodiment, when forming the plurality of groove rows 31 to 38 deeper than the concave portion 12, the grooves 31a to 31a.
Since the widths w ₂₁ of the grooves 38a, 31b to 38b are set to be substantially equal to each other and wider than the depth H of the concave portion 12, each groove 31a is formed.
-38a and 31b-38b are filled with the oxide film 40, the concave portion 12 of the space 39 is filled with the oxide film 40.

The groove spacing L ₂₁ in the groove rows 31 to 38 is set to be narrower than 0.818 times the groove width w ₂₁ , so that the parallel groove rows, for example, the groove rows 31 and 32. The groove row interval L ₂₂ is set to be narrower than 0.818 times the groove width w ₂₁ , and similarly, the groove row interval L ₂₃ between the groove row 33 and the groove row 34, and the groove row 35.
The groove row distance L ₂₄ between the groove row 36 and the groove row 36 and the groove row distance L ₂₅ between the groove row 37 and the groove row 38 are also set to be narrower than 0.818 times the groove width w ₂₁ . Further, the gap L ₂₆ between the groove row 34 and the grooves 31, 32, 35, 36, and the groove row 38 and the grooves 31, 32, 35, 36.
Since the distance L ₂₇ between the groove and the groove is set to be narrower than 0.818 times the groove width w ₂₁ , the inside of each of the grooves 31a to 38a and 31b to 38b is filled with the oxide film 40 without any gap, and between the grooves and between the groove rows. The first semiconductor substrate 11 is completely oxidized.
Therefore, similar to the first embodiment, the first and second element formation regions 43 and 44 separated by the dielectric layer 42 are formed.

Next, a third embodiment will be described with reference to sectional views of the manufacturing process of FIG. 6 and a layout diagram of FIG.

As shown in (1) of FIG. 6, in the first step, the first semiconductor substrate 11 made of a silicon substrate whose main surface is mirror-polished in the same manner as described in (1) of FIG. 1 above. An etching mask (not shown) made of a resist is formed on the top by a lithography technique. Then
The depth D is, for example, 1 at a predetermined position of the first semiconductor substrate 11 by, for example, chemical etching or reactive ion etching.
The concave portion 12 having a size of about μm is formed. Then, the etching mask (not shown) is removed by, for example, an asher process or a wet etching process.

As shown in (2) of FIG. 6 and (1) of FIG. 7, three groove rows 51 are formed on the side wall 12a side of the concave portion 12 by the lithography technique and etching (for example, reactive ion etching). , 52, 53 are formed. Each groove row 5
1, 52, 53 are grooves 51a and 51b, and groove 5
2a and 52b and grooves 53a and 53b. Similarly,
Groove rows 54, 55, 56 are formed on the side wall 12b side. Each of the groove rows 54, 55, 56 includes grooves 54a and 54a.
b, grooves 55a and 55b, and grooves 56a and 56b.
Groove rows 57, 58, 59 are formed on the side wall 12c side. Each of the groove rows 57, 58, 59 includes grooves 57a and 57, respectively.
b, grooves 58a and 58b, and grooves 59a and 59b.
Further, groove rows 60, 61, 62 are formed on the side wall 12d side. Each of the groove rows 60, 61, 62 includes grooves 60a and 60b, grooves 61a and 61b, and grooves 62a and 62b.

The groove arrays 51 to 62 are designed under the following conditions.

(C) The grooves 51a, 51b, 54a, 5
The groove width w ₃₁ of 4b, 57a, 57b, 60a, 60b is set to be substantially equal in the direction of the groove rows 51, 54, 57, 60. Further, the grooves 52a, 52b, 55a, 55b, 58
The groove width w ₃₂ of a, 58b, 61a, 61b is set to the groove row 5 concerned.
It is set to be substantially equal in the directions of 2, 55, 58 and 61. Further, the grooves 53a, 53b, 56a, 56b, 59a, 5
The groove width w ₃₃ of 9b, 62a, 62b is set to the respective groove row 53, 5
It is set to be substantially equal in the directions of 6, 59 and 62. This groove width w
₃₃ is set equal to the groove width w ₃₁ . And each of the above groove rows 5
1 to 62 are formed deeper than the depth D of the concave portion 12, for example, the depth H is about 20 μm.

(C) Of the groove rows 51 to 62, the groove width w ₃₂ of the central groove row 52, 55, 58, 61 is equal to the groove row 51, 5
Groove width w ₃₁ of 4, 57, 60 and groove rows 53, 56, 5
It is set narrower than the groove width w _{33 of} 9, 62. For example, the groove width w ₃₁ and the groove width w ₃₃ are formed to about 2.0 μm, and the groove width w ₃₂
Is formed to have a thickness of about 1.8 μm.

(S) The groove interval L ₃₁ of the groove rows 51, 54, 57, 60 is set to be narrower than 0.818 times the groove width w ₃₁ . Groove spacing L _{32 in the} groove rows 52, 55, 58, 61 directions
Is set narrower than 0.818 times the groove width w ₃₂ . Further, the groove spacing L ₃₃ in the groove rows 53, 56, 59, 62 is set to the groove width w.
Set narrower than 0.818 times ₃₃ . (C) Convex portions 63, 6 between the parallel groove rows 51-53
4, convex portions 65 and 66 between the groove rows 54 to 56, and the groove row 57
Convex portion 67, 68 between the through 59, the width W ₃₁ of the convex portions 69 and 70 between the groove array 60 to 62 is narrower set than 0.409 times the sum of the groove width w _31, w ₃₂ To do. For example, each width W ₃₁ is
It is formed to have a thickness of about 1.5 μm.

(So) Groove row 53 and groove rows 54, 55, 56,
60, 61, 62 and the groove interval L ₃₄ , and the groove array 59 and the groove array 54, 55, 56, 60, 61, 62 groove interval L _35.
Is set to be narrower than 0.818 times the groove width w ₃₁ . Therefore, the groove intervals L ₃₄ and L ₃₅ are set to the same value as the groove interval L ₃₁ , for example.

Then, as shown in (3) of FIG. 6, a step similar to the second step described in (3) of FIG.
The first semiconductor substrate 11 and the second semiconductor substrate 14 are directly bonded to each other to form a bonded substrate 15. The second semiconductor substrate 14
Is made of, for example, a silicon substrate whose main surface is mirror-finished. Therefore, a space 71 including the concave portion 12 and the groove arrays 51 to 62 is formed inside the bonded substrate 15.

Subsequently, a third step shown in FIG. 6 (4) is performed. In this step, the first semiconductor substrate 11 of the bonding substrate 15 is removed by the grinding method and the polishing method, for example, until the groove arrays 51 to 62 are exposed, as described in (3) of FIG. 1 above.

Then, the fourth step shown in FIG. 6 (5) and FIG. 7 (2) is performed. In this step, the oxide film 72 is grown on the inner wall of the space 71 in the same manner as described in (4) of FIG. Then, the space 71 is replaced with the oxide film 7
Embed with 2. At this time, since the groove widths w ₃₁ , w ₃₂ , and w ₃₃ are formed wider than the depth D of the concave portion 12, the concave portion 12 is first filled with the oxide film 72, and then the groove rows 51 to 6 are formed.
2 is embedded in the oxide film 72. Then, the oxide layer 73 is also formed on the surface of the bonding substrate 15. In addition, (2) of FIG.
The oxide layer 73 in FIG.

Thereafter, the fifth step shown in FIG. 6 (6) is performed. In this step, the oxide layer 73 is removed by wet etching in the same manner as described in (5) of FIG. Then, the first semiconductor substrate 11 is exposed. In this way, the second dielectric layer 74 made of the oxide film 72 is formed.
A first element formation region 75 composed of the first semiconductor substrate 11 separated from the semiconductor substrate 14 is formed. At the same time, the second element forming region 76 formed of the first and second semiconductor substrates (11, 14) bonded to each other is formed.

Next, the convex portions 63 and 64 between the parallel groove rows 51 to 53 and the convex portions 65 and 6 between the groove rows 54 to 56 are provided.
6, the convex portions 67, 68 between the groove rows 57 to 59, the groove row 60
The reason why each width W ₃₁ of the convex portions 69 and 70 between ˜62 is set smaller than 0.409 times the sum of the groove widths w ₃₁ and w ₃₂ will be described with reference to FIG.

The oxide film formed by the thermal oxidation method is formed as described in (1) of FIG. That is, when the oxide film 212 having a film thickness t is formed on the silicon substrate 211, the thickness t of the oxide film 212 is about 45.
% Is formed under the surface of the initial silicon substrate 211, and about 55% of the thickness of the oxide film 212 is known to be formed over the surface of the initial silicon substrate 211.

Therefore, as shown in FIG. 8, for example, in order to fill the grooves 221, 222, 223 with the oxide film 212 (the portion indicated by the chain double-dashed line), the respective grooves 221, 222, 2
23 groove widths w ₂₂₁ , w ₂₂₂ , w ₂₂₃ (at this time w ₂₂₂ <
w ₂₂₁ , w ₂₂₂ <w ₂₂₃ , w ₂₂₁ = w ₂₂₃ ), and the width of the silicon substrate 211 (convex portion) between the grooves ₂₂₁ and 222 is W ₂₂₁ and the silicon substrate 211 between the grooves 222 and 223. If the width of the (convex portion) is W ₂₂₂ = W ₂₂₁ , and the film thickness of the oxide film 212 to be formed is t, the following conditions are required. First, t> w ₂₂₂ for filling the groove _222.
A film thickness t of the oxide film 212 of /(2×0.55) is required. Further, between the grooves 221, 222 and the groove 22.
In order to oxidize the silicon substrate 211 between 2, 223,
t> w ₂₂₁ /(2×0.45), t> w ₂₂₂ / (2 ×
The film thickness t of the oxide film 212 of 0.45) is required.
If the relationship between W ₂₂₁ and w ₂₂₁ and w ₂₂₂ is calculated using the above equations, the relationship W ₂₂₁ <0.409 (w ₂₂₁ + w ₂₂₂ ) can be calculated. The trenches 221 and 223 are formed on the oxide film 212.
The burying is performed by further oxidizing and growing the oxide film 212 from the outside of the trenches 221 and 223.

In the third embodiment, when forming a plurality of groove rows 51 to 62 deeper than the concave portion 12, each groove width w ₃₁ , w ₃₂ , w ₃₃ is set to be smaller than the depth D of the concave portion 12. Since it is set wide, each groove 51a-62a, 51b-62b, 5
Before the 1c to 62c are filled with the oxide film 72, the space 7
The concave portion 12 of No. 1 is filled with the oxide film 72.

Then, the groove intervals L ₃₁ and L ₃₃ are set to the groove width w ₃₁ (w
₃₃ ) and the groove interval L ₃₂ is set to be narrower than 0.818 times the groove width w ₃₂ , so that the silicon substrate 11 between the grooves in the groove rows 51 to 62 is completely formed. Even if the groove arrays 51 to 62 are oxidized, the oxide films 72 are not filled.

Further, since the groove width w ₃₂ is set to be narrower than the groove widths w ₃₁ and w ₃₃ , the central groove rows 52, 55, 58 and 6 are formed.
1 is first buried in the oxide film 72. Therefore, at that time, the groove rows 51, 53, 54, 56, 57, 59 on both sides are
60 and 62 are not completely filled with the oxide film 72.
Therefore, by continuing further oxidation, the groove rows 5 on both sides are
The oxide film 72 grows from the outside of the 1, 53, 54, 56, 57, 59, 60, 62, and the groove rows 51, 53, 5
4,56,57,59,60,62 are completely embedded.

Moreover, the width W ₃₁ of each of the convex portions 63 to 70 is set smaller than 0.409 times the sum of the groove widths w ₃₁ and w ₃₂ . From this, as described in FIG. 8 above, the oxide film 72 formed on the first semiconductor substrate (silicon substrate) 11 is formed.
Film thickness conditions and the convex portions 63 and 64 from the groove rows 51 to 53 side.
The oxidation to the (first semiconductor substrate 11) stops on the basis of the oxide film growth condition that the inside of the groove rows 51 to 53 is stopped in a state where the inside of the groove rows 51 to 53 is filled with the oxide film 72. By growing 72, the groove arrays 51 to 53 are completely filled with the oxide film 72. Along with that, the convex portion 6
3,64 is completely oxidized. The above phenomenon is caused by the groove array 54-
56, the groove rows 57 to 59, and the groove portions 60 to 62, respectively, the convex portions 65 and 66, the convex portions 67 and 68, and the convex portions 69 and 70.
In the same manner as above, it is completely oxidized.

On the other hand, although not shown, when the groove interval L ₃₁ is set to 0.818 times or more the groove width w ₃₁ , it is possible to set the groove row 51,
Since 54, 57 and 60 are filled with the oxide film 72, an unoxidized region is formed in the first semiconductor substrate 11 between the trenches. Similarly, when the groove interval L ₃₂ is set to 0.818 times or more the groove width w ₃₂ , and when the groove interval L ₃₃ is set to 0.818 times or more the groove width w ₃₃ , the first semiconductor between the grooves is also set. An unoxidized region is formed on the substrate 11. Further, the width W ₃₁ of the convex portions 63 to 70 is set to the groove width w _31.
And the groove width w ₃₂ (w ₃₃ ) are set to 0.409 times or more, the groove arrays 51 to 62 are first filled with the oxide film 72, so that the first semiconductor substrate 11 between the groove arrays 51 to 62 is formed. A non-oxidized region is generated in.

Next, a fourth embodiment will be described with reference to FIGS. 9 and 10.

As described in (1) of FIG. 1 above, the first
In the process, by lithography technology and etching,
The depth D is, for example, 1 at a predetermined position of the first semiconductor substrate (11).
A concave portion (12) of about μm is formed. After that, an etching mask (not shown) formed by a lithography technique
Are removed by, for example, an asher process or a wet etching process.

Then, as shown in the partial layout diagram of FIG. 9, the sidewall 1 of the concave portion 12 is formed by the lithography technique and etching (eg, reactive ion etching).
On the first semiconductor substrate 11 on the 2a side, n rows (hereinafter, described as 4 rows with n = 4) of groove rows 81 to 84 are formed. Although not shown, similar groove rows are formed on the other side wall side of the concave portion 12. The groove array 81 includes, for example, the grooves 81a, 81b,
81c, and the other groove arrays are similarly composed of the groove arrays 82, 82a to 82c, the groove array 83, the grooves 83a to 83c, and the groove array 84, the grooves 84a to 84c.

The groove arrays 81 to 84 are designed under the following conditions.

(T) The groove widths w ₄₁ , w ₄₂ , w ₄₃ and w ₄₄ of the groove rows 81 to 84 are set to be substantially equal in the groove row 81 to 84 direction. The depth H (depth direction not shown) of each groove row 81 to 84 is set deeper than the depth D (depth direction not shown) than the concave portion 12, for example, H = 20 μm. Set to.

(H) The groove interval L ₄₁ in the groove array 81 direction is set to be narrower than 0.818 times the groove width w ₄₁ . Similarly for the other groove rows 82 to 84, the groove widths w ₄₂ , L ₄₃ are respectively set to the groove intervals L ₄₂ , L ₄₃ , L _{44 in} the groove row 82 to 84 directions.
set to be narrower than 0.818 times the w _43, w _44.

Further, k is an arbitrary natural number satisfying 2 ≦ k ≦ n, and here, as n = 4, as a natural number satisfying 2 ≦ k ≦ 4, for example, the first row (k−1th row) of the groove rows 81 and 2 The space between the first row (k-th row) of the groove rows 82 is defined as the first row (k−1th row) of the convex portion 85. Similarly, the convex portion 86 of the second row and the groove row 8 of the third row are provided between the groove row 82 of the second row and the groove row 83 of the third row.
A space between the third and fourth groove rows 84 is a third row convex portion 87.

(T) Convex portion 85 of the first column (k-1th column)
Width W ₄₁ (W _k-1 ) of the first row (k-1 row) of the groove row 81
Of the groove width w ₄₁ (w _k−1 ) of the second row and the groove width w ₄₂ (w _k ) of the groove row 82 of the second row (k-th row) is set to be smaller than 0.409 times the length. Similarly, the width W ₄₂ (W _k ) of the convex portion 86 is
The sum of the groove width w ₄₂ (w _k ) and the groove width w ₄₃ (w _{k + 1} ) is 0.4.
The groove width is set to be narrower than the length of 09 times.
_It is set wider than 0.818 times ₄₂ (w _k ). Similarly, the width W ₄₃ of the convex portion 87 is set to be narrower than 0.409 times the sum of the groove width w ₄₃ and the groove width w _44, and more than 0.818 times the groove width w _43. Set widely.

(T) The width w of the groove row 82 of the second row (kth row)
₄₂ (w _k ) is the groove width w of the groove row 81 of the first row (k-1th row)
_The width is set to be wider than ₄₁ (w _k-1 ) and narrower than the groove width w ₄₄ (w _n ) of the groove row 84 in the fourth row (nth row). Similarly, the width w ₄₃ is set to be wider than the groove width w _{2 and} narrower than the groove width w ₄₄ ,
The groove width w ₄₄ is set wider than the groove width w ₄₃ .

Thereafter, the same steps as the steps from the second step to the fifth step described in (3) onward of FIG. 1 are performed, and as shown in the sectional view of FIG.
An oxide film (89) is generated in a space (88) formed by the concave upper portion (12) and the groove rows (81) to (89) inside the bonded substrate 15 composed of the second semiconductor substrate 14 and , The oxide film (89) is embedded. Then, the dielectric layer 90 is formed of the oxide film (89). Further, by removing an oxide layer (not shown) formed on the surface layer of the first semiconductor substrate 11, the first element formation region 91 formed of the first semiconductor substrate 11 separated by the dielectric layer 90 is bonded to the first element formation region 91. 1. Second element formation region 92 composed of second semiconductor substrate (11, 14)
To form.

In the fourth embodiment, when forming a plurality of groove rows 81 to 84 deeper than the concave portion 12, each groove width w ₄ to.
Since each of w ₄₄ is set to be substantially equal to each direction of the groove rows 81 to 84 and is set to be wider than the depth D of the concave portion 12, each groove row 81 to 84 is filled with the oxide film 89. Previously, the concave portion 12 of the space 88 was formed on the oxide film 89.
Embedded in.

Since each of the groove intervals L _{41 to} L ₄₄ in each direction of each groove row 81 to 84 is set to be narrower than 0.818 times the corresponding groove widths w _{41 to} w ₄₄ , As described in the third method, the groove rows 81 to
Before the groove 84 is filled with the oxide film 89, each groove row 81 to 8 is formed.
The first semiconductor substrate 11 between the grooves in the four directions is completely oxidized.

Further, for example, the width W ₄₁ of the convex portion 85 is set to the groove width w.
_It is set to be narrower than 0.409 times the sum of ₄₁ and w ₄₂ , and the widths W ₄₂ and W _{43 of} the other convex portions 86 and 87 are similarly set to be 0.409 times the sum of the groove widths on both sides thereof. Since the groove widths w ₄₁ to w ₄₄ of the groove rows 81 to 84 are set to be wide from w _{41 in} order, the convex portions 85 in the first row are completely oxidized. Along with that, the first row of grooves 8
The oxide film 89 is filled in order from 1. However, when the convex portion 87 of the third row is completely oxidized, the groove row 84 of the fourth row is not filled with the oxide film 89. Then, by further oxidizing, the oxidation proceeds from the outside of the groove array 84, and the groove array 84 is filled with the oxide film 89.

On the other hand, although not shown, when the groove spacing L ₄₁ in the groove array 81 direction is set to 0.818 times or more the groove width w ₄₁ , the first semiconductor substrate 11 between the grooves 81a, 81b, 81c.
The groove array 81 is filled with the oxide film 89 before the oxide is oxidized. Therefore, the first gap between the grooves 81a, 81b, 81c
An unoxidized region is formed on the semiconductor substrate 11. Other groove rows 82-
When the groove intervals L ₄₂ , L ₄₃ , and L ₄₄ are set in the same manner as described above for 84, unoxidized regions are formed in the first semiconductor substrate 11 in the groove row 82 to 84 directions.

When the width W ₄₁ of the convex portion 85 is set to 0.409 times or more the sum of the groove width w ₄₁ and the groove width w ₄₂ on both sides of the convex portion 85, the groove arrays 81 and 82 are formed of the oxide film 89 first. Since it is embedded, an unoxidized region is formed in the convex portion 85. Further, similarly to the above, the width W ₄₂ of the convex portion 86 is set to the groove width on both sides thereof.
Set to 0.409 times or more of the sum of w ₄₂ and groove width w ₄₃ ,
And 0.409 times or more the sum of the groove width w ₄₃ and the groove width w ₄₄ on both sides of the width W ₄₃ of the convex portion 87, the convex portion 86 and the convex portion 87 will be formed on the first semiconductor substrate 11. Produces an unoxidized region. The width W ₄₂ is 0.818 of the groove width w ₄₂ .
If it is set to be equal to or less than twice, a region not filled with the oxide film 89 is generated in the groove array 82. If the width W ₄₃ is set to 0.818 times or less the groove width w _43, a region not filled with the oxide film 89 is generated in the groove array 83.

Next, a fifth embodiment will be described with reference to FIGS. 11 and 12.

As described with reference to FIG. 11A, in the first step, the depth D is, for example, 1 μm at a predetermined position of the first semiconductor substrate 11 by the lithography technique and the etching.
A concave portion (12) of about m is formed. After that, an etching mask (not shown) formed by a lithography technique
Are removed by, for example, an asher process or a wet etching process.

Then, as shown in the partial layout diagram of FIG. 11, the concave portion is formed on the first semiconductor substrate 11 in a direction substantially perpendicular to the side wall 12a of the concave portion 12 by the lithography technique and etching (for example, reactive ion etching). 1
2. Grooves 101-1 and 101-2 in n rows deeper than the depth D of 2
, ..., 101-k, ..., 101-n are formed. Further, the groove 101-1 in the first row is shared and the groove 1
In the direction symmetrical to 01-1, similar grooves 101-2,
..., 101-k, ... 101-n are formed. That is, the grooves 101-n, ..., 101-k ,.
101-2, 101-1, 101-2, ..., 101
A groove array 101 composed of -k, ... 101-n is formed. Each of the grooves 101-1 to 101-n is formed to have a depth H = 20 μm, for example. Although not shown, similar groove rows are formed on the other side wall side of the concave portion 12.

The groove array 101 is designed under the following conditions.

K is an arbitrary natural number satisfying 2 ≦ k ≦ n,
A space between the groove 101-k-1 in the k-1th row and the groove 101-k in the kth row is defined as a convex portion 102-k-1 in the k-1th row.

(D) The width W _k-1 of the convex portion 102-k-1 in the k-1th row is defined as the groove width w _k-1 of the groove 101-k-1 in the k-1th row.
And the groove width w _k of the groove 101-k in the k-th row, 0.409
The length is set to be narrower than double the length and wider than the length 0.818 times the groove width w _k-1 .

(D) The width w _k of the groove 101-k in the k-th column is k
The width is set to be wider than the width w _k-1 of the groove 101-k-1 in the _first row and narrower than the width w _n of the groove 101-n in the nth row. Then, as described above, the groove 101-1 is shared in the symmetric direction by 10
1-2, ..., 101-k, ..., 101-n are formed.

Thereafter, the steps from the second step to the fifth step described in (3) onward of FIG. 1 are performed, and as shown in the sectional view of FIG. 12, the first semiconductor substrate 11 and the second semiconductor The concave portion (1
2) and the space (10) formed by the groove array (101).
3) is filled with an oxide film (104). Then, the oxide film (104) forms the dielectric layer 108. Further, by removing an oxide layer (not shown) formed on the surface layer of the first semiconductor substrate 11, the first layer separated by the dielectric layer 108 is removed.
A first element formation region 109 made of the semiconductor substrate 11 and a second element formation region 110 made of the joined first and second semiconductor substrates (11, 14) are formed.

In the fifth embodiment, each groove 101-1 to 10-1 is used.
01-n the groove width w ₁ to w _n from the set wider than the depth D of the concave portion 12, before the grooves 101-1 to 101-n are buried with the oxide film 104, a concave space 103 The portion 12 is filled with the oxide film 104.

Then, the convex portion 102-k-1 of the (k-1) th column
The width W _k-1 of the, of the sum of the groove width w _k-1 and the groove width w _k 0.40
Narrower than 9 times and 0.8 of groove width w _k-1
Set it wider than 18 times the length. Groove 1 in the kth row
The width w _k of 01-k is set wider than the groove width w _{k−1 and} narrower than the groove width w _n . From this, the convex portion 102 of the first row
−1, the convex portions 102 are completely oxidized, and the grooves 101-1 to 10-10 are sequentially arranged from the groove 101-1 in the first row.
1-n is filled with the oxide film 104. Then, at the time when the convex portion 102-n-1 of the (n-1) th column is completely oxidized,
The groove 101-n in the n-th column is not filled with the oxide film 104. Therefore, by further oxidizing the groove array 101
Oxidation progresses from the outside of the trenches and the trenches 101-n are formed on the oxide film 104.
Embed with.

On the other hand, although not shown, the convex portion 102-k
The width W _k of the grooves 101-k, 101-k + 1 is set to 0.409 times or more of the sum of the groove widths w _k , w _{k + 1} of the grooves 101-k, 101-k + 1 sandwiching the grooves 101-k, 101-k + 1. Since k + 1 is filled with the oxide film 104, the convex portions 102-1 to 102- between the grooves are formed.
An unoxidized region is generated at n-1. Further, when the width W _k-1 is set to 0.818 times or less of the groove width w _k-1 , the groove 101
A region which is not filled with the oxide film 104 is generated at −k−1.

Next, a sixth embodiment will be described with reference to FIGS.

As shown in the layout diagram of FIG. 13 and the sectional view of FIG. 14A, the first semiconductor substrate 11 is formed by the lithography technique and etching in the first step.
A concave portion 12 having a depth D of, for example, about 1 μm is formed at a predetermined position. The concave portions 12 are arranged in parallel with the first grooves 1 in the m rows.
21-1, 121-2, ..., 121-j, ...,
121-m first groove array 131 and the first groove array 1
31 and the second groove 122 of m rows arranged in parallel with 31
1, 122-2, ..., 122-j, ..., 122
-M second groove row 132 and each of the first grooves 121-
Both ends of 1 to 121-m and each second groove 122-1 to 122-
and a third groove 123 formed continuously with m.

The first and second groove rows 131 and 132 and the third groove 123 are designed under the following conditions.

Then, the first groove 121-1 of the first row of the first groove array 131 and the second groove 122-1 of the first row of the second groove array 132.
The portion between 1 and 1 is the convex portion 124-1 (125-1) in the first column. Further, j is an arbitrary natural number satisfying 2 ≦ j <m,
The first groove 121-j in the j-th row and the first groove 121 in the j-1th row
The first convex portion 124-j in the j-th column is between −j-1 and j
Second groove 122-j in row and second groove 122- in row j-1
The second convex portion 125-j in the j-th column is located between j-1 and j-1.

(C) Groove width w of the first groove 121-j in the j-th row
_j is set to be wider than the groove width w _j-1 of the first groove 121-j-1 in the _j- 1th row and smaller than the groove width w _m of the first groove 121-m in the m-th row. Also, the groove width w of the second groove 122-j in the j-th row
_j is set to be wider than the groove width w _j-1 of the second groove 122-j-1 in the _j- 1th row and smaller than the groove width w _m of the second groove 122-m in the m-th row. The first groove row 131 and the second groove row 132
Since they are symmetrically arranged, the groove widths in the same row are indicated by the same symbols. Hereinafter, it shows similarly. With that, each first
Depth H ₁ of grooves 121-1 to 121-m and each second groove 1
22 - 1 to 122-m depth H ₂ is set deeper than the groove width w ₃ of the third groove 123.

(H) The width W _j of the first convex portion 124-j in the j-th column is the width W _j of the first convex portion 124-j-1 in the j-1 th column.
The width W of the first convex portion 124-m in the m-th row which is wider than _j-1
Set narrower than _m . Similarly, the second convex portion 1 of the j-th column
The width W _j of 25-j is the second convex portion 125- of the j−1th column.
The second convex portion 125 in the m-th row, which is wider than the width W _{j-1 of j-1}
Setting narrowly than the width W _m of -m.

(F) Convex portion 124-1 (125) in the first row
The groove width of the first groove 121-1 of the width W ₁ of the first row of -1) w ₁
And the groove width w ₁ of the second groove 122-1 in the first row, 0.4
Set narrower than 09 times.

(F) The width W _j of the first convex portion 124-j in the j-th row is the groove width w _j-1 of the first groove 121-j-1 in the j-1-th row.
And 0.4 of the sum of the groove width w _j of the first groove 121-j in the j-th row.
The groove width is set to be narrower than 09 times and wider than 0.818 times the groove width w _j-1 . Similarly, the second in the jth column
The width W _j of the convex portion 125-j is set to the second groove 12 in the j−1th row.
2-j-1 and sets smaller than 0.409 times the sum of the groove width w _j of the groove width w _j-1 and j-th column of the second groove 122-j of the groove width w _j-1 It is set wider than 0.818 times.

[0131] (e) second grooves 12 the groove width w ₃ of the groove width w _m or m-th column of the first groove 121-m of the m-th column of the third groove 123
As well as wider than the groove width w _m of 2-m, a depth H ₃ of the third groove 123 is set deeper than the groove width w _3.

By setting the conditions as described above,
The first groove row 131, the second groove row 132, and the third groove 123 are provided to form the concave portion 12.

Then, by using the lithography technique and etching, a groove array similar to that described in the first to fifth embodiments is formed, for example, as described in the sixth embodiment.
Groove rows 151, 152, 153, 15 whose groove widths change in order
4 is formed on the outside of the side surfaces 12a, 12b, 12c, 12d of the concave portion 12 so as to be continuous with the third groove 123. Therefore, the groove array 151 includes, for example, the first and second groove arrays 131 and 132 and the first and second convex portions 1.
24-1 to 124-m, 125-1 to 125-m are arranged in the opposite order, and a plurality of grooves 15 deeper than the concave portion 12 are formed.
1-m, ..., 151-j, ..., 151-2, 1
51-1, 151-2, ..., 151-j, ...,
It consists of 151-m. The other groove rows 152 to 154 are also formed in the same manner as the groove row 151. Further, the grooves 151-m to 151-1 to 151- are also provided outside the corners of the concave portion 12.
151-m + 1, 151-m + 2 in an array continuous to the array of m
To place.

Thereafter, the respective steps from the second step to the fifth step described in (3) onward of FIG. 1 are performed. Then, as shown in the sectional view of (2) of FIG. 14, the concave portion (12) and the grooves 151-m + 2, 151- are formed inside the joint substrate 15 including the first and second semiconductor substrates 11 and 14. m + 1, 151-m
~ 151-1 ~ 151-m, 151-m + 1, 151-m +
In the space (141) formed by 2 and 2, an oxide film (14
2) is generated and the space (141) is converted into an oxide film (14).
Embed in 2). Then, the oxide layer (142) forms the dielectric layer 143. Further, by removing an oxide layer (not shown) formed on the surface layer of the first semiconductor substrate 11, the first element formation region 144 made of the first semiconductor substrate 11 separated by the dielectric layer 143, A second element formation region 145, which is a region in which the second semiconductor substrate (11, 14) is joined, is formed.

In the sixth embodiment, the first and second columns of the jth column are
The groove width w _j of the grooves 121-j and 122-j is set to be wider than the groove width w _{j-1 and} narrower than the groove width w _m . In addition, the width W _j of the first and second convex portions 124-j and 125-j in the j-th column is
It is set wider than the width W _{j-1 and} narrower than the width W _m . Further, the width W ₁ of the convex portion 124-1 (125-1) in the first row is set to 1
Groove width w ₁ of the first groove 121-1 of the first row and second groove 1 of the first row
22-1 set to be narrower than 0.409 times the sum of the groove width w ₁ of the. And the first and second convex portions 124-j, 1 of the j-th column
The width W _j of the 25-j, and sets smaller than 0.409 times the sum of the groove width w _j-1 and the groove width w _j, the groove width w _j-1
It is set wider than 0.818 times. From this, 1
From the convex portion 124-1 (125-1) in the row,
Second convex portions 124-2 to 124-m, 125-1 to 12
5-m is completely oxidized, and first and second grooves 121-1 and 122-1 in the first row are arranged in order from the first and second grooves 12.
1-1 to 121-m and 122-1 to 122-m are filled with the oxide film 142. Then, the first and second convex portions 12
Oxidation of 4-1 to 124-m, 125-1 to 125-m and first and second grooves 121-1 to 121-m, 122-1 to 1
22-m oxide film formation is performed alternately.

[0136] Moreover depth H ₂ is the first m-th column of the depth H ₁ and the second grooves 122-1 through 122-m of each of the first groove 121-1 to 121-m, the second groove 121- m, 122-m since the setting deeper than the groove width w _m of the first groove with the oxide film 142 grown from the groove width direction 121-1 to 121
-M and each of the second grooves 122-1 to 122-m are the oxide film 1
Embedded at 42.

Since the depth H ₃ of the third groove 123 is set deeper than the groove width w ₃ , the third groove 123 is filled with the oxide film 142 by the growth of the oxide film 142 from the side wall direction. Further, the groove rows 151 to 154 are also filled with the oxide film 142.

On the other hand, for example, the width W _j of the first convex portion 124-j is set to the first groove 121-that sandwiches the first convex portion 124-j.
0.409 of the sum of the groove widths w _j and w _j-1 of j, 121-j-1
If it is set to double or more, first groove 121-j, 121-
Since j-1 is filled with the oxide film 142, the first convex portion 1
An unoxidized region is formed at 24-j. Similarly, the width W _j of the second convex portion 125-j is defined by the groove widths w _j and w _j-1 of the second grooves 122-j and 122-j-1 sandwiching the second convex portion 125-j. Even if the sum is set to 0.409 times or more, the second convex portion 125
An unoxidized region is generated at −j. When the width W _j of the first convex portion 124-j in the j-th column is set to 0.818 times or less the groove width w _j-1 , the first groove 121-j-1 in the j-1-th column is oxidized. It is not completely filled with the membrane 142. Similarly, the second in the jth column
Even if the width W _j of the convex portion 125-j is set to 0.818 times or less of w _j-1 , the second groove 122-j-1 in the j-1th column is completely filled with the oxide film 142. Absent.

Further, each of the first and second grooves 121-1 to 121
The depths H ₁ and H _{2 of} −m, 122-1 to 122-m are the first and second grooves 121-1 to 121-m, 122-1 to 12-1, respectively.
When the groove width is smaller than 22-m, the oxide film 142 is filled from the outer peripheral side of the concave portion 12, so that there is a region not filled with the oxide film 142 at the center side of the concave portion 12.

[0140]

As described above, according to the first aspect of the invention, the first and second semiconductor substrates are directly bonded to each other, and
When the semiconductor substrate side is polished, the plurality of groove portions of the space provided inside the bonded substrate are in a state of communicating with the external atmosphere on the main surface side. Therefore, the oxidizing gas can be introduced into the space through the plurality of groove portions in the subsequent oxidation step. In this way, since the oxidizing gas can be introduced into the space from the thickness direction of the bonded substrate, it is not necessary to lay out the ventilation passage for the oxidized gas in the in-plane direction of the bonded substrate. Therefore, since the chip size can be reduced, high integration can be achieved, and the layout design can be simplified.

When the connection substrate is left in an oxidizing atmosphere, the oxidizing gas is supplied to the inside of the space through a plurality of groove portions formed on the main surface side of the bonded substrate. Becomes easier to enter. Therefore, the oxide film grows sufficiently inside the space, and the space can be completely filled with the oxide film. At the same time, the first semiconductor substrate between the grooves can be completely oxidized. Therefore, no unoxidized region is generated in the dielectric layer, and the quality of the dielectric layer can be improved.

According to the second aspect of the present invention, the groove widths of the plurality of grooves are set to be substantially equal and wider than the depth of the recessed portions, so that the recessed portions of the space are oxidized before each groove is filled with the oxide film. It can be embedded with a membrane. Since the distance between the grooves in the groove row direction is set to be narrower than 0.818 times the groove width, the first semiconductor substrate between the grooves can be completely oxidized and the inside of each groove can be completely covered with an oxide film. Can be completely embedded. In this way, a dielectric layer composed of oxidized regions along each groove array can be formed.

According to the third aspect of the invention, since the oxidized region is formed by the two groove rows, the oxidized region can be set wide. Moreover, since the groove width of each groove is set to be substantially equal and wider than the depth of the concave portion, before each groove is filled with the oxide film,
The concave portion of the space can be filled with an oxide film. Then, the distance between the grooves in the groove row direction, the distance between the parallel groove rows, and the distance between the groove rows that are arranged at positions where the groove array directions of the groove rows are substantially orthogonal and adjacent to each other are defined as 0 of the groove width. .818
Since the width is set to be narrower than twice, the inside of each groove can be completely filled with an oxide film without a gap, and the first semiconductor substrate between the grooves and between the groove rows can be completely oxidized. In this way, a dielectric layer composed of oxidized regions along each groove array can be formed.

According to the fourth aspect of the invention, since the oxidized region is formed by the three groove rows, the oxidized region can be set wide. Since the groove width of each groove is set to be substantially equal and wider than the depth of the concave portion, the concave portion of the space can be filled with the oxide film before the groove is filled with the oxide film. Further, since the interval between the grooves in each groove row direction is set to be narrower than 0.818 times the groove width, the first semiconductor substrate between the grooves can be completely oxidized. Further, the groove width of the central row is set narrower than the groove width of the groove rows on both sides thereof, and the width of each convex portion is narrower than 0.409 times the sum of the groove widths of the groove rows sandwiching the convex portion. Since the setting is made, first, the central row of trenches can be completely filled with the oxide film. The ridges on both sides can then be completely oxidized. After that, the groove rows on both sides can be completely filled with the oxide film. Further, since the interval between the groove rows arranged in the positions where the grooves of the groove rows are arranged substantially orthogonal to each other and adjacent to each other is set to be narrower than 0.818 times the groove width, the first semiconductor substrate between the groove rows is It can be completely oxidized. In this way, a dielectric layer composed of oxidized regions along each groove array can be formed.

According to the fifth aspect of the invention, since the oxidized region is formed by a plurality of groove arrays, the oxidized region can be set wide. Since the groove width of each groove is set to be substantially equal in the groove row direction and wider than the depth of the concave portion, the concave portion of the space can be filled with the oxide film before the groove is filled with the oxide film. Further, since the interval between the grooves in each groove row direction is set to be narrower than 0.818 times the groove width, the spaces between the grooves in the groove row direction can be completely oxidized before the grooves are filled with the oxide film. . Further, the width of the convex portion in the k-1th row is set to be 0.409 times smaller than the sum of the groove widths in the k-1th row and the groove row in the kth row, and the groove in the k-1th row is set. The groove width is set to be wider than 0.818 times the groove width in the row, and the groove width of the k-th groove row is wider than that of the (k-1) -th groove row and is larger than that of the n-th groove row. Since each of the convex portions is set to be narrow, the convex portions in the first row can be completely oxidized in order. At the same time, each groove can be sequentially filled with an oxide film from the first row of grooves. The n-th groove array can be filled with an oxide film by promoting oxidation from the outside. In this way, a dielectric layer composed of oxidized regions along each groove array can be formed.

According to the sixth aspect of the present invention, the groove width of each groove is set to be equal and wider than the depth of the recessed portion, so that the recessed portion of the space is filled with the oxide film before each groove is filled with the oxide film. It becomes possible to embed with. The width of the convex portion in the (k-1) th row is set to be smaller than 0.409 times the sum of the groove widths in the (k-1) th row and the kth row, and the groove in the (k-1) th row groove is set. The width is set to be wider than 0.818 times the width, and the groove width of the k-th groove is wider than the groove width of the (k-1) -th groove.
Since the groove width of the groove in the row is set to be narrower, the convex portions in the first row can be completely oxidized in order from the convex portion. At the same time, the grooves can be completely filled with the oxide film in order from the first row of grooves. Then, in order to fill the last remaining groove in the n-th column with an oxide film, it is possible to completely fill the groove by advancing the oxidation from the outside of the groove in the n-th column. In this way, a dielectric layer composed of oxidized regions along each groove array can be formed.

According to the invention described in claim 7, when forming the concave portion, the groove width of the first groove (second groove) is set to be wider in order from the first row, and the first convex portion (second groove) is formed. The width of the convex portion) is also set wider from the first column. Further, the width of the convex portion in the first row is set to be smaller than 0.409 times the sum of the groove widths in the first and second grooves in the first row. And the first convex portion in the j-th column (second convex portion)
Is set to be narrower than 0.409 times the sum of the groove width of the first groove (second groove) in the j-1th row and the groove width of the first groove (second groove) in the jth row. Together with the first groove (second groove) in the j-1th row
The groove width is set to be wider than 0.818 times the groove width. Further, the depth of the first and second grooves is set deeper than the groove width. With this setting, each of the first and second convex portions can be oxidized by oxidation from the side wall direction, and the first and second grooves can be filled with the oxide film grown from the side wall direction. Then, the first convex portion (second convex portion) in the first row, and then 1
The first and second grooves in the second row, the first and second convex portions in the second row, and the first and second grooves in the second row are arranged in the order of the first and second grooves.
The convex portion can be completely oxidized and the first and second grooves can be completely filled with the oxide film. In this way, an oxidized region can be formed in the concave portion. Further, since the groove row continuous to the concave portion is formed on the outer peripheral side of the concave portion,
The groove array can also be filled with an oxide film to form an oxide region. Therefore, it is possible to form a dielectric layer that is composed of each oxidized region and separates the element formation region.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a first embodiment.

FIG. 2 is a layout diagram of a groove array according to the first embodiment.

FIG. 3 is an explanatory diagram of conditions for filling the trench with an oxide film.

FIG. 4 is a cross-sectional view of the manufacturing process of the second embodiment.

FIG. 5 is a layout diagram of a groove array according to a second embodiment.

FIG. 6 is a cross-sectional view of the manufacturing process of the third embodiment.

FIG. 7 is a layout diagram of a groove array according to a third embodiment.

FIG. 8 is an explanatory diagram of conditions for filling the trench with an oxide film.

FIG. 9 is a partial layout diagram of a first step of the fourth embodiment.

FIG. 10 is a completed sectional view of the fourth embodiment.

FIG. 11 is a partial layout diagram of the first step of the fifth embodiment.

FIG. 12 is a completed sectional view of the fifth embodiment.

FIG. 13 is a layout diagram of the first process of the sixth embodiment.

FIG. 14 is a cross-sectional view of the manufacturing process of the sixth embodiment.

FIG. 15 is a manufacturing process diagram (1) of a conventional example.

FIG. 16 is a manufacturing process diagram (2) of the conventional example.

FIG. 17 is a manufacturing process diagram (3) of the conventional example.

[Explanation of symbols]

1 Dielectric Separation Substrate 11 First Semiconductor Substrate 12 Recess 12a to 12d
Side wall 13 Groove row 13a to 13h
Groove 14 Second semiconductor substrate 15 Bonding substrate 16 Space 17 Oxide film 18 Oxide layer 21 Dielectric layer 22 First element formation region 23 Second element formation region 31a to 38a Groove 31b to 38b
Grooves 31-38 Groove row 39 Space 40 Oxide film 41 Oxide layer 42 Dielectric layer 43 First element formation region 44 Second element formation region 51-62 Groove row 51a-62a Groove 51b-62b
Groove 71 Space 72 Oxide film 73 Oxide layer 74 Dielectric layer 75 First element formation region 76 Second element formation region 81-84 Groove row 81a-81c
Grooves 82a to 82c Grooves 83a to 83c
Grooves 84a to 84c Grooves 85 to 87 Convex portions 88 Space 89 Oxide film 90 Dielectric layer 91 First element formation region 92 Second element formation region 101 Groove row 101-1 to 101-n Groove 102-1 to 10
2-n convex portion 103 space 104 oxide film 108 dielectric layer 109 first element formation region 110 second element formation region 121-1 to 12
1-m 1st groove 122-1 to 122-m 2nd groove 124-1 to 12
4-m convex portion 125-1 to 125-m convex portion 123 third groove 131 groove row 132 groove row D (concave portion) depth H ₁ (groove) depth H ₂ (groove) depth L ₁₁ groove interval L ₂₁ groove interval L _{22 to} L ₂₅ groove array interval L ₂₆ , L ₂₇ interval L _{31 to} L ₃₃ groove interval L ₃₄ , L ₃₅ groove array interval L _{41 to} L ₄₃ groove interval w ₁₁ groove width w ₂₁ groove width w ₃₁ to w ₃₃ groove width w ₄₁ to w ₄₄ groove width w ₁ to w _n groove width w ₁ to w _m groove width W ₃₁ width W ₁ of the wide W ₁ to _W-n convex portion of the convex portions - W _m Convex width

Claims (7)

[Claims] 1. A first step of forming a concave portion at a predetermined position of a first semiconductor substrate, and then forming a groove array including a plurality of grooves deeper than the concave portion on each side wall of the concave portion, Forming a space composed of the concave portion and the groove array inside the bonded substrate by directly bonding the first semiconductor substrate and the second semiconductor substrate having the groove array to form a bonded substrate. 2 steps, the first of the bonding substrate until the groove row portion of the space is exposed.
A third step of removing the semiconductor substrate, and leaving the bonded substrate in an oxidizing atmosphere to grow an oxide film on the inner wall of the space and fill the space with the oxide film, and also to the surface of the bonded substrate. A fourth step of forming an oxide layer, and a step of forming a first semiconductor substrate separated from a second semiconductor substrate by a dielectric layer of the oxide film by removing the oxide layer to expose the first semiconductor substrate. 1 element formation region,
A method of manufacturing a dielectric isolation substrate, comprising: a fifth step of forming a second element forming region including a first semiconductor substrate and a second semiconductor substrate bonded to each other. 2. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein, in the first step, after forming a concave portion at a predetermined position of the first semiconductor substrate, the concave portion is formed on each side wall of the concave portion. When forming a groove array consisting of a plurality of grooves deeper than the groove portion, (a) the groove width of each groove is set to be substantially equal and wider than the depth value of the recessed portion, and (b) the groove array. It is characterized in that the interval between the grooves in the direction is set to be narrower than 0.818 times the groove width to form each groove, and then each step from the second step to the fifth step is performed. Manufacturing method of dielectric isolation substrate. 3. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein in the first step, after forming a concave portion at a predetermined position of the first semiconductor substrate, the concave portion is formed on each side wall of the concave portion. When forming two rows of grooves consisting of a plurality of grooves deeper than the
The width of each groove is set to be substantially equal and wider than the depth value of the concave portion, and (g) the interval between the grooves in the groove row direction is narrower than 0.818 times the groove width. Set,
(H) The distance between the parallel groove rows is 0.818 of the groove width.
The width of the groove rows is set to be narrower than double, and the distance between the groove rows that are arranged at the positions where the grooves of the groove rows are substantially orthogonal to each other are set to be narrower than 0.818 times the groove width. A method for manufacturing a dielectric isolation substrate, comprising forming the grooves, and then performing the steps from the second step to the fifth step. 4. The method of manufacturing a dielectric isolation substrate according to claim 1, wherein in the first step, after forming a concave portion at a predetermined position of the first semiconductor substrate, the concave portion is formed on each side wall of the concave portion. When forming 3 rows of grooves consisting of multiple grooves deeper than the
The width of each groove is set to be substantially equal in the groove row direction and wider than the depth value of the recessed portion.
The groove width of the central row of each groove row is set to be narrower than the groove width of the groove rows on both sides, and (s) the interval between the grooves in each groove row direction is narrower than 0.818 times the groove width. And (c) the width of the convex portion between the parallel groove rows is set to be smaller than 0.409 times the sum of the groove widths of the groove rows that sandwich the convex portion, (so) the groove row Each groove is formed by setting the interval between the groove rows that are substantially orthogonal to each other in the arrangement direction of the groove rows and is narrower than 0.818 times the groove width of the adjacent groove row. After that, each of the steps from the second step to the fifth step is performed, and the method for manufacturing a dielectric isolation substrate, comprising: 5. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein in the first step, after forming a concave portion at a predetermined position of the first semiconductor substrate, the concave portion is formed on each side wall of the concave portion. When forming n rows of groove rows consisting of a plurality of grooves deeper than the
The groove width of each groove is set to be substantially equal in the groove row direction and wider than the depth value of the concave portion, and (h) the interval between the grooves in each groove row direction is 0.818 times the groove width. Is set to be narrower than k, and k is an arbitrary natural number satisfying 2 ≦ k <n, and the convex portion between the groove row of the k−1th row and the groove row of the kth row is the convex shape of the k−1th row. And the width of the convex portion in the k−1th row is narrower than 0.409 times the sum of the groove width of the k−1th groove row and the kth groove row. The groove width of the groove row in the (k-1) th row is set to be wider than 0.818 times the groove width of the groove row in the (k-1) th row, and Wider than the groove width of the n-th groove row, each groove is formed, and then each step from the second step to the fifth step is performed. Method for manufacturing separation substrate. 6. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein, in the first step, after forming a recessed portion at a predetermined position of the first semiconductor substrate, substantially each side wall of the recessed portion is formed. When forming a plurality of grooves deeper than the concave portion in n rows in the right angle direction, k is an arbitrary natural number satisfying 2 ≦ k <n, and is defined as between the groove of the k−1th row and the groove of the kth row. The convex portion is a convex portion in the k−1th row, and (n) the width of the convex portion in the k−1th row is the groove width of the groove in the k−1th row and the groove width of the kth row. Is set to be narrower than 0.409 times the sum of the above, and is set to be wider than 0.818 times the groove width of the groove in the (k-1) th row, and (d) the groove width of the kth row is set to (k-1). It is set to be wider than the groove width of the groove of the row and narrower than the groove width of the groove of the n-th row and wider than the depth of the concave portion,
A method for manufacturing a dielectric isolation substrate, comprising forming the grooves, and then performing the steps from the second step to the fifth step. 7. Any one of claims 1 to 6
The method for manufacturing a dielectric isolation substrate according to item 1, wherein in the first step, a first groove formed of m rows of parallel first grooves is formed in a formation region of a concave portion set at a predetermined position of the first semiconductor substrate. A second groove row composed of m second grooves arranged in parallel with the groove row is provided at symmetrical positions, and both ends of each first groove of the first groove row and both ends of each second groove of the second groove row are provided. And a third groove continuous with the first groove row, the second groove row, and the third groove row.
When forming a concave portion formed of a groove, the convex portion of the first row is provided between the first groove of the first row of the first groove row and the second groove of the first row of the second groove row. , And j is 2 ≦
As an arbitrary natural number j <m, the first groove in the j-th column and j−
The first convex portion of the j-th row is formed between the first groove of the first row and the second convex portion of the j-th row is formed between the second groove of the j-th row and the second groove of the j−1-th row. As the convex portion, the groove width of the first groove in the (c) jth row is j−
The groove width of the first groove in the first row is set to be wider than that of the first groove in the m-th row, and the groove width of the second groove in the j-th row is set to be smaller than that of the second groove in the j−1-th row. The groove width is set wider than the groove width and narrower than the groove width of the second groove in the m-th row, and the depth of each first groove is set larger than the value of the groove width of the first groove in the m-th row. The depth of the second groove is set deeper than the groove width, and the width of the first convex portion in the (j) th row is wider than the width of the first convex portion in the (j-1) th row and (m) in the mth row. The width of the second convex portion of the j-th column is set to be narrower than the width of the first convex portion, and the width of the second convex portion of the j-th column is wider than the width of the second convex portion of the j-1th column. The width of the convex portion in the first row is set to be smaller than the sum of the first groove in the first row and the second groove in the first row.
It is set narrower than 409 times, and (f) the width of the first convex portion in the jth row is the sum of the groove width of the first groove in the j−1th row and the groove width of the first groove in the jth row. While setting it narrower than 0.409 times,
The width of the second convex portion in the jth row is set to be wider than 0.818 times the groove width of the first groove in the j−1th row and the width of the second groove in the j−1th row and j 0.40 of the sum of the width of the second groove of the row
The width is set to be narrower than 9 times, and is set to be wider than 0.818 times the groove width of the second groove in the (j-1) th row.
The groove width of the third groove is set equal to or wider than the groove width of the first groove in the m-th row or the groove width of the second groove in the m-th row, and the depth of the third groove is set to the third groove. Is set deeper than the groove width of No. 1 to form a concave portion including the first groove row, the second groove row, and the third groove, and then the concave upper portion is continuously formed along the outer circumference of the concave portion. A method for manufacturing a dielectric isolation substrate, characterized in that a groove array composed of a plurality of grooves deeper than the concave portion is formed, and then each of the steps from the second step to the fifth step is performed.