JPH07183296A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH07183296A
JPH07183296A JP5323952A JP32395293A JPH07183296A JP H07183296 A JPH07183296 A JP H07183296A JP 5323952 A JP5323952 A JP 5323952A JP 32395293 A JP32395293 A JP 32395293A JP H07183296 A JPH07183296 A JP H07183296A
Authority
JP
Japan
Prior art keywords
polyimide resin
resin film
layer
via hole
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5323952A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Sekine
浩良 関根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP5323952A priority Critical patent/JPH07183296A/en
Publication of JPH07183296A publication Critical patent/JPH07183296A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures

Abstract

PURPOSE:To provide excellent dimensional accuracy of a viahole of a polyimide resin film and to accurately expose a surface of an Al bonding pad by increasing the shape and the size of the viahole in a second polyimide resin film larger than those of a viahole in a first polyimide resin film layer. CONSTITUTION:The shape and the size of a viahole in a second polyimide resin film 6 is controlled by regulating the developing and etching times with alkaline aqueous solution to be larger than those of a first layer viahole 5. Then, using the obtained first and second polyimide resin films 4, 6 as mask materials, an inorganic insulating layer 3 of an upper part of an Al bonding pad 2 of a wiring layer is dry-etched by using mixed gas of fluorine, and the pad 2 is exposed. An exposed part 7 is formed in shape smaller than that of the pad of the layer 2, thereby obtaining a moisture resistant reliability of a semiconductor device using it.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、さらに詳しくは半導体素子などの表面を保護する
ためのポリイミド系樹脂膜によるビアホールが形成され
た半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a via hole made of a polyimide resin film for protecting the surface of a semiconductor element or the like.

【0002】[0002]

【従来の技術】従来、半導体などの各種電子部品の表面
保護膜や層間絶縁膜として、ポリイミド系樹脂が用いら
れている。このポリイミド系樹脂は、PSG、Si
2、SiNなどの無機絶縁膜に比較して凹凸の大きい
基板上に平坦な膜を形成できるとともに、1μm以上の
厚い膜を容易に形成でき、さらに他の有機材料に比較し
て耐熱性が高いなどの利点を有するため、バイポーラI
Cの層間絶縁膜に採用され、最近ではメモリー素子のα
線遮蔽膜やバッファーコート膜として幅広く用いられて
いる。
2. Description of the Related Art Conventionally, a polyimide resin has been used as a surface protective film or an interlayer insulating film for various electronic parts such as semiconductors. This polyimide resin is PSG, Si
Compared to inorganic insulating films such as O 2 and SiN, it is possible to form a flat film on a substrate having large irregularities, a thick film of 1 μm or more can be easily formed, and heat resistance is higher than that of other organic materials. Bipolar I because it has advantages such as high price
It has been adopted for the interlayer insulating film of C
Widely used as a line shield film and buffer coat film.

【0003】ポリイミド系樹脂膜は、ポリアミド酸溶液
をスピン法などにより半導体基板であるウエハ上に塗布
し、熱処理して形成される。またポリイミド系樹脂膜に
はビアホールなどのパターンを形成する必要があるが、
このパターンはフォトレジストを介したウエットエッチ
ング工程などにより形成されている。上記パターンの形
成法としては、(1)220〜350℃で熱処理したポ
リイミド樹脂膜上にマスク材としてネガレジストパター
ンを形成した後、ヒドラジン系溶液を用いてポリイミド
樹脂膜をエッチングしてパターン化する方法、(2)1
10〜160℃で熱処理したポリイミド系樹脂膜上にマ
スク材としてポジレジストを形成し、露光した後、アル
カリ性水溶液を用いてポジレジストの現像とポリイミド
樹脂膜のエッチングを同時に行ってパターン化する方法
などが知られている。
The polyimide resin film is formed by applying a polyamic acid solution on a wafer, which is a semiconductor substrate, by a spin method or the like, and heat-treating it. In addition, it is necessary to form a pattern such as a via hole in the polyimide resin film,
This pattern is formed by a wet etching process using a photoresist. As a method of forming the pattern, (1) a negative resist pattern is formed as a mask material on a polyimide resin film which is heat-treated at 220 to 350 ° C., and then the hydrazine-based solution is used to etch and pattern the polyimide resin film. Method, (2) 1
A method in which a positive resist is formed as a mask material on a polyimide resin film that has been heat-treated at 10 to 160 ° C., and after exposure, patterning is performed by simultaneously developing the positive resist using an alkaline aqueous solution and etching the polyimide resin film. It has been known.

【0004】近年、半導体業界では、有機溶剤使用の規
制強化および半導体の生産工程時間の短縮化が図られて
おり、(1)の方法ではヒドラジン系溶液およびフェノ
ール系レジスト剥離液を多量に用いるという欠点があ
り、またヒドラジン系溶液でのエッチング処理がバッチ
式となり工程が一旦途切れ、さらにエッチング時間が長
いため、生産工程時間の短縮化が図りにくいという欠点
があるため、最近では、有機溶剤をほとんど使用せず、
また(1)の方法に較べてポリイミド樹脂膜のエッチン
グ時間が短い(2)の方法が主流となっている。
In recent years, in the semiconductor industry, regulations on the use of organic solvents have been tightened and semiconductor production process time has been shortened. In the method (1), a large amount of hydrazine-based solution and phenol-based resist stripping solution are used. However, since the etching process with hydrazine-based solution is batch type and the process is interrupted and the etching time is long, it is difficult to shorten the production process time. Without using,
Further, the method (2) is predominantly used, in which the etching time of the polyimide resin film is shorter than the method (1).

【0005】しかしながら、(2)の方法の場合には、
アルカリ性水溶液を用いて現像およびエッチングする
際、半導体基板表面に露出しているAlボンディングパ
ッド(電極)部がアルカリ性水溶液によって溶解または
変色するなどの問題があった。この問題は、ビアホール
の形成の際のポリイミド系樹脂膜の膜厚が厚くなるほ
ど、さらにエッチング時間が長くなるほど大きくなる。
However, in the case of the method (2),
When developing and etching using an alkaline aqueous solution, there is a problem that the Al bonding pad (electrode) portion exposed on the surface of the semiconductor substrate is dissolved or discolored by the alkaline aqueous solution. This problem becomes more serious as the thickness of the polyimide resin film at the time of forming the via hole becomes thicker and as the etching time becomes longer.

【0006】上記の問題を解決するため、無機絶縁膜
(P−SiNなどのパッシベーション膜)を形成してA
lボンディングパッドを露出しないようにした半導体基
板上にポリイミド系樹脂膜を形成し、該樹脂膜のビアホ
ールの形成時にはエッチング液であるアルカリ性水溶液
がAlボンディングパッド部に接触しないようにし、ビ
アホール形成後は、ポリイミド系樹脂膜をマスク材とし
て、ビアホール部をドライエッチングしてAlボンディ
ングパッド部表面を露出させる方法が採られている。し
かし、このような方法では、ポリイミド系樹脂膜の膜厚
が厚くなると、ビアホールのパターン精度が悪くなり、
解像度も低下するため、Alボンディングパッド部表面
を露出させることが難しくなるという問題がある。
In order to solve the above problems, an inorganic insulating film (passivation film such as P-SiN) is formed to form A.
l A polyimide resin film is formed on a semiconductor substrate in which the bonding pad is not exposed, an alkaline aqueous solution that is an etching solution is prevented from coming into contact with the Al bonding pad portion when forming a via hole of the resin film, and after forming the via hole A method is employed in which the via hole is dry-etched to expose the surface of the Al bonding pad using the polyimide resin film as a mask material. However, in such a method, when the film thickness of the polyimide-based resin film is increased, the pattern accuracy of the via hole is deteriorated,
Since the resolution is also lowered, there is a problem that it becomes difficult to expose the surface of the Al bonding pad portion.

【0007】[0007]

【発明が解決しようとする課題】本発明は、前記の従来
技術の問題を解決し、膜厚の厚いポリイミド系樹脂膜を
を用いてビアホールを形成した場合でもポリイミド系樹
脂膜のビアホールの寸法精度に優れ、Alボンディング
パッド部表面を精度よく露出させることができる半導体
装置の製造方法を提供するものである。
DISCLOSURE OF THE INVENTION The present invention solves the above-mentioned problems of the prior art and, even when a via hole is formed using a thick polyimide resin film, the dimensional accuracy of the via hole of the polyimide resin film is high. It is intended to provide a method of manufacturing a semiconductor device, which is excellent in exposure and can expose the surface of the Al bonding pad portion with high accuracy.

【0008】[0008]

【課題を解決するための手段】本発明は、無機絶縁膜が
形成された基板上に、有機四塩基酸二無水物とジアミン
とを有機溶剤中で反応させて得られるポリアミド酸溶液
を塗布し、熱処理した後、ポリイミド系樹脂膜のビアホ
ールを形成し、該ポリイミド系樹脂膜をマスク材として
上記基板上の無機絶縁膜をドライエッチングして半導体
装置を製造する方法において、前記ポリイミド系樹脂膜
のビアホールを形成する際に、第一層のポリイミド系樹
脂膜のビアホールを形成した後、さらに該ビアホール上
に第一層のポリイミド系樹脂膜より厚い膜厚の第二層の
ポリイミド系樹脂膜のビアホールを形成する半導体装置
の製造方法およびこの製造方法において、前記第一層の
ポリイミド系樹脂膜の膜厚を3μm以下の範囲とし、か
つ該第二層のポリイミド系樹脂膜のビアホールの形状寸
法を、第一層のポリイミド系樹脂膜のビアホールの形状
寸法より大とする半導体装置の製造方法に関する。
According to the present invention, a polyamic acid solution obtained by reacting an organic tetrabasic acid dianhydride and a diamine in an organic solvent is applied onto a substrate on which an inorganic insulating film is formed. In the method of manufacturing a semiconductor device by forming a via hole of a polyimide resin film after heat treatment and dry-etching the inorganic insulating film on the substrate using the polyimide resin film as a mask material, When forming a via hole, after forming a via hole of the first layer polyimide resin film, further via hole of the second layer polyimide resin film thicker than the first layer polyimide resin film on the via hole In the method for manufacturing a semiconductor device and the method for manufacturing the same, the film thickness of the polyimide resin film of the first layer is within a range of 3 μm or less, and The geometry of the via hole of bromide-based resin film, a method of manufacturing a semiconductor device which larger than the geometry of the via hole of the polyimide resin film of the first layer.

【0009】本発明に用いられるポリアミド酸溶液は、
例えば、N−メチル−2−ピロリドン、N,N−ジメチ
ルアセトアミド、N,N−ジメチルホルムアミド等の有
機溶剤中に、4,4′−ジアミノジフェニルエーテルな
どのジアミンを溶解させ、次に3,3′,4,4′−ベ
ンゾフェノンテトラカルボン酸二無水物などの有機四塩
基酸二無水物を加えて50℃以下、より好ましくは室温
付近またはそれ以下の温度で攪拌、反応させて得られ
る。ポリアミド酸溶液の市販品としては、例えばPI
Q、PIX(日立化成工業社製商品名)等が挙げられ
る。
The polyamic acid solution used in the present invention is
For example, a diamine such as 4,4′-diaminodiphenyl ether is dissolved in an organic solvent such as N-methyl-2-pyrrolidone, N, N-dimethylacetamide, N, N-dimethylformamide, and then 3,3 ′. It can be obtained by adding an organic tetrabasic dianhydride such as 4,4'-benzophenonetetracarboxylic dianhydride and stirring and reacting at a temperature of 50 ° C or lower, more preferably around room temperature or lower. Examples of commercially available polyamic acid solutions include PI
Q, PIX (trade name of Hitachi Chemical Co., Ltd.) and the like.

【0010】また感光性ポリアミド酸溶液も用いること
ができる。この感光性ポリアミド酸には特に制限はな
く、例えば感光基をエステル結合で導入した感光性ポリ
アミド酸に増感剤、光重合開始剤などを加えたもの、ポ
リアミド酸に炭素−炭素二重結合を有するアミン化合物
を加えたものに光重合開始剤、増感剤、ビスアジドなど
を加えたもの、ポリアミド酸にイソシアナートエチルメ
タクリレートを反応させて得られる反応物に1,6−ヘ
キサンジオールジアクリレートなどの不飽和化合物、光
重合開始剤、増感剤などを加えたもの等が好ましく用い
られる。これらの市販品としては、PL−5035、P
L−2135(日立化成工業社製商品名)などが挙げら
れる。
A photosensitive polyamic acid solution can also be used. There is no particular limitation on the photosensitive polyamic acid, for example, a photosensitive polyamic acid having a photosensitive group introduced by an ester bond to which a sensitizer, a photopolymerization initiator or the like is added, and a polyamic acid having a carbon-carbon double bond. A photopolymerization initiator, a sensitizer, bisazide, etc. added to the amine compound, and a reaction product obtained by reacting polyamic acid with isocyanate ethyl methacrylate such as 1,6-hexanediol diacrylate. Those containing an unsaturated compound, a photopolymerization initiator, a sensitizer and the like are preferably used. These commercially available products include PL-5035, P
L-2135 (trade name, manufactured by Hitachi Chemical Co., Ltd.) and the like can be mentioned.

【0011】ポリイミド系樹脂膜は、上記のポリアミド
酸溶液を50〜80℃の温度で攪拌して使用上適切な粘
度に調整した後、例えば半導体基板上にスピン塗布し、
ホットプレート、温風式乾燥器等で100〜400℃の
範囲の温度で3時間以内で熱処理し、脱水閉環して得ら
れる。本発明において、ポリイミド系樹脂膜のパターン
は、第一層のポリイミド系樹脂膜のビアホールを形成
し、さらに該ビアホール上に第一層のポリイミド系樹脂
膜より厚い膜厚の第二層のポリイミド系樹脂膜を形成
し、再度ビアホールが形成されるが、これらのポリイミ
ド系樹脂膜のビアホールの形成には、下記に示すような
ポジレジストを用いた公知の方法を採用することができ
る。
The polyimide-based resin film is prepared by stirring the above polyamic acid solution at a temperature of 50 to 80 ° C. to adjust the viscosity to a value suitable for use, and then spin-coating the semiconductor substrate, for example.
It can be obtained by heat-treating at a temperature in the range of 100 to 400 ° C. for 3 hours or less with a hot plate, a hot air dryer or the like, and dehydration ring closure. In the present invention, the pattern of the polyimide resin film, the via hole of the polyimide resin film of the first layer is formed, and the polyimide resin of the second layer having a thickness larger than that of the polyimide resin film of the first layer is formed on the via hole. The resin film is formed, and the via hole is formed again. The well-known method using a positive resist as shown below can be adopted for forming the via hole of these polyimide resin films.

【0012】まずポリイミド系樹脂膜上に、ポジレジス
ト液を例えばスピン等により塗布し、ホットプレート上
で110℃で120秒以内で熱処理してポジレジストを
形成する。このポジレジストには特に制限はなく、例え
ばノボラック樹脂とナフトキノンジアジド混合物が用い
られ、市販品としてはOFPR−5000(東京応化工
業社製商品名)、RI−7912P(日立化成工業社製
商品名)等が挙げられる。
First, a positive resist solution is applied onto the polyimide resin film by, for example, spin and heat treated on a hot plate at 110 ° C. for 120 seconds or less to form a positive resist. The positive resist is not particularly limited, and for example, a mixture of novolac resin and naphthoquinonediazide is used, and commercially available products are OFPR-5000 (trade name of Tokyo Ohka Kogyo Co., Ltd.) and RI-7912P (trade name of Hitachi Chemical Co., Ltd.). Etc.

【0013】次にポジレジスト上にフォトマスクを載せ
て露光処理した後、公知の写真食刻技術によるアルカリ
現像液を用いたパドル法等でポジレジストの露光部の現
像と該露光部に対応した前記ポリイミド系樹脂膜のエッ
チングを連続して行ってビアホールを形成する。該アル
カリ現像液には、水酸化テトラメチルアンモニウム水溶
液2.38%(NMD−3:東京応化工業社製)などが
用いられる。ポリイミド系樹脂膜のビアホール形成後の
ポジレジストは、剥離液等を用いて公知の方法により除
去される。
Next, a photomask is placed on the positive resist and exposed to light, and then the exposed portion of the positive resist is developed and the exposed portion is dealt with by a paddle method or the like using an alkali developing solution by a known photo-etching technique. The polyimide resin film is continuously etched to form a via hole. As the alkali developer, 2.38% tetramethylammonium hydroxide aqueous solution (NMD-3: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used. The positive resist after forming the via hole of the polyimide resin film is removed by a known method using a stripping solution or the like.

【0014】本発明において、第一層のポリイミド系樹
脂膜のビアホールの寸法は、Alボンディングパッドの
面積より小さくしてドライエッチング後にパッドの全面
が露出されないようにし、かつ基板内でのビアホールの
寸法精度のばらつきが小さいことが好ましい。ビアホー
ルの形状寸法がAlボンディングパッドの面積よりも広
い場合には、ドライエッチング後にAlボンディングパ
ッド全面が露出し、その後の耐湿信頼性試験で不良発生
の頻度が高くなる。また第二層のポリイミド系樹脂膜
は、第一層のポリイミド系樹脂膜上に該第一層のポリイ
ミド系樹脂膜より厚い膜厚となるように形成され、第一
層と同様の方法でビアホールの形成が行われる。第一層
のポリイミド系樹脂膜の膜厚は、ビアホール寸法の高精
度化および微細加工性の点から3μm以下の範囲とする
のが好ましく、またその第2層のビアホールの形状寸法
は、第一層のポリイミド系樹脂膜のビアホールの形状寸
法より大とすることが好ましい。第二層のポリミド系樹
脂膜は、エッチング性および半導体装置の製造時におけ
る応力緩和性の点から3〜30μmの厚さとすることが
好ましい。
In the present invention, the size of the via hole in the polyimide resin film of the first layer is smaller than the area of the Al bonding pad so that the entire surface of the pad is not exposed after dry etching, and the size of the via hole in the substrate. It is preferable that the variation in accuracy is small. If the via hole has a larger dimension than the area of the Al bonding pad, the entire surface of the Al bonding pad is exposed after dry etching, and the frequency of occurrence of defects increases in the subsequent moisture resistance reliability test. The second layer of polyimide resin film is formed on the first layer of polyimide resin film to be thicker than the first layer of polyimide resin film, and the via hole is formed in the same manner as the first layer. Is formed. The thickness of the polyimide resin film of the first layer is preferably in the range of 3 μm or less from the viewpoint of improving the precision of via hole dimensions and fine processing, and the shape dimension of the via hole of the second layer is The size is preferably larger than the shape size of the via hole of the polyimide resin film of the layer. It is preferable that the second layer polyimide resin film has a thickness of 3 to 30 μm from the viewpoints of etching properties and stress relaxation properties at the time of manufacturing a semiconductor device.

【0015】このように膜厚の薄い第一層のポリイミド
系樹脂膜によるビアホールの形状を、膜厚の厚い第二層
のポリイミド系樹脂膜によるビアホールの形状の前に行
うことにより、Alボンディングパット上部に形成され
るパターンの寸法精度が向上し、かつ寸法のばらつきも
少なくなる。第一層および第二層のポリイミド系樹脂膜
によってビアホールを形成した後は、ビアホール部の無
機絶縁膜をドライエッチングにより除去し、基板上のA
lボンディングパッド部表面を露出させる。ドライエッ
チングの反応性ガスには、酸素(O2)、四弗化炭素
(CF4)、アルゴン(Ar)などが用いられるが、他
のガスを混合して用いても何ら差し支えない。
As described above, the shape of the via hole made of the first layer polyimide resin film having a small thickness is formed before the shape of the via hole made of the second layer polyimide resin film having a large film thickness, whereby the Al bonding pad is formed. The dimensional accuracy of the pattern formed on the upper part is improved and the dimensional variation is reduced. After the via holes are formed by the first-layer and second-layer polyimide resin films, the inorganic insulating film in the via holes is removed by dry etching, and A on the substrate is removed.
l The surface of the bonding pad is exposed. Oxygen (O 2 ), carbon tetrafluoride (CF 4 ), argon (Ar) and the like are used as the reactive gas for dry etching, but other gases may be mixed and used without any problem.

【0016】図1は、本発明の半導体装置の製造方法の
一実施例を示す説明図である。図1において、半導体基
板1上に所定形状に形成されたAl(アルミニウム)か
らなる配線層および電極(ボンディングパッド)2が、
シリコン酸化膜からなるいわゆるパッシベーション膜の
無機絶縁層3で被覆されている。この半導体基板上に、
ポリアミド酸溶液をスピン塗布し、熱処理により溶媒を
除去し、一部を脱水閉環して第一層ポリイミド系樹脂膜
4を形成する。この第一層ポリイミド系樹脂膜4上にフ
ェノールノボラック系のポジレジストを成膜し、フォト
マスクを介して露光した後、公知の写真食刻技術により
アルカリ性水溶液でポジレジストの現像と第一層ポリイ
ミド系樹脂膜4のエッチングを行い、Alボンディング
パッド上部にビアホール5を形成する。次いでポジレジ
ストを有機系溶剤を用いてパドル法、スプレ法等で剥離
除去した後、200〜400℃の範囲の温度で3時間以
内で熱処理し、完全に脱水閉環したパターン化された第
一層ポリイミド系樹脂膜4を得る(a)。
FIG. 1 is an explanatory view showing an embodiment of a method for manufacturing a semiconductor device of the present invention. In FIG. 1, a wiring layer made of Al (aluminum) and an electrode (bonding pad) 2 formed in a predetermined shape on a semiconductor substrate 1 are
It is covered with an inorganic insulating layer 3 which is a so-called passivation film made of a silicon oxide film. On this semiconductor substrate,
The polyamic acid solution is spin-coated, the solvent is removed by heat treatment, and a part of the solution is dehydrated and ring-closed to form the first layer polyimide resin film 4. A phenol novolac-based positive resist is formed on the first-layer polyimide-based resin film 4, exposed through a photomask, and then developed with an alkaline aqueous solution by a known photoetching technique and the first-layer polyimide is developed. The system resin film 4 is etched to form a via hole 5 above the Al bonding pad. Then, the positive resist is stripped and removed using an organic solvent by a paddle method, a spray method, etc., and then heat-treated at a temperature in the range of 200 to 400 ° C. for 3 hours or less to completely dehydrate and ring-close the patterned first layer. A polyimide resin film 4 is obtained (a).

【0017】ビアホールの形成された第一層のポリイミ
ド系樹脂膜4上に、さらにポリアミド酸溶液を第一層の
ポリイミド系樹脂膜4より膜厚が厚くなるようにスピン
塗布し、熱処理により溶媒を除去し、一部を脱水閉環し
て第二層のポリイミド系樹脂膜6を形成する。次いで上
記と同様の方法でAlボンディングパッド上部のビアホ
ールの形成を行い、ビアホール5を形成し、その後、ポ
ジレジストを剥離除去し、200〜400℃の範囲の温
度で3時間以内で熱処理し、完全に脱水閉環したビアホ
ールの形成された第二層ポリイミド系樹脂膜6を得る
(b)。図1の(b)に示すように第二層のポリイミド
系樹脂膜のビアホールの形状寸法は、アルカリ性水溶液
による現像およびエッチング時間等を調節して第一層の
ビアホールの形状寸法より大きく形成される。次に、得
られた第一層および第二層のポリイミド系樹脂膜4、6
をマスク材として配線層であるAlボンディングパッド
2上部の無機絶縁層3をフッ素系の混合ガスを用いてド
ライエッチングし、Alボンディングパッド2を露出さ
せる(c)。露出部7はその下部に上面図を示すように
配線層2のAlボンディングパッド部より小さい形状と
され、これが用いられる半導体装置の耐湿信頼性が確保
される。
A polyamic acid solution is further spin-coated on the first-layer polyimide resin film 4 in which the via holes are formed so as to be thicker than the first-layer polyimide resin film 4, and a solvent is applied by heat treatment. It is removed and a part of it is dehydrated and ring-closed to form the second layer polyimide resin film 6. Then, a via hole is formed on the Al bonding pad in the same manner as described above to form a via hole 5, and then the positive resist is peeled and removed, followed by heat treatment at a temperature in the range of 200 to 400 ° C. for 3 hours or less to completely remove the positive resist. A second-layer polyimide resin film 6 having a via hole formed by dehydration ring closure is obtained (b). As shown in FIG. 1B, the via hole of the polyimide resin film of the second layer is formed larger than the via hole of the first layer by adjusting the development time with an alkaline aqueous solution and the etching time. . Next, the obtained polyimide resin films 4 and 6 of the first layer and the second layer
Using the as a mask material, the inorganic insulating layer 3 on the Al bonding pad 2 which is a wiring layer is dry-etched using a fluorine-based mixed gas to expose the Al bonding pad 2 (c). The exposed portion 7 has a shape below the Al bonding pad portion of the wiring layer 2 as shown in the top view, and the moisture resistance reliability of the semiconductor device using this is secured.

【0018】[0018]

【実施例】以下、本発明を実施例により詳しく説明する
が、本発明はこれらに限定されるものではない。 実施例1 4,4′−ジアミノジフェニルエーテル54.05g
(0.27モル)および1,3−ビス(アミノプロピ
ル)テトラメチルジシロキサン7.45g(0.03モ
ル)をN−メチル−2−ピロリドン800g中によく攪
拌溶解させ、3,3′,4,4′−ベンゾフェノンテト
ラカルボン酸二無水物48.33g(0.15モル)お
よびピロメリット酸二無水物32.71g(0.15モ
ル)を徐々に加えながら反応させ、粘度13ポアズ(2
5℃)、樹脂分濃度4.6重量%のポリアミド酸溶液を
得た。
EXAMPLES The present invention will now be described in detail with reference to examples, but the present invention is not limited thereto. Example 1 54.05 g of 4,4'-diaminodiphenyl ether
(0.27 mol) and 1,3-bis (aminopropyl) tetramethyldisiloxane 7.45 g (0.03 mol) were well dissolved in 800 g of N-methyl-2-pyrrolidone with stirring to give 3,3 ', The reaction was carried out while gradually adding 4,4'-benzophenone tetracarboxylic acid dianhydride 48.33 g (0.15 mol) and pyromellitic dianhydride 32.71 g (0.15 mol), and a viscosity of 13 poise (2
A polyamic acid solution having a resin content of 4.6% by weight was obtained.

【0019】このポリアミド酸溶液を、図1(a)に示
すように、Al配線層および電極2および無機絶縁膜
(P−Si34)層3が形成された半導体基板1上に、
3000rpmで30秒間スピン塗布した後、ホットプレ
ートで100℃で60秒間、さらに130℃で60秒間
熱処理(プリベーク)し、2.8μm厚のポリイミド系
樹脂膜層4からなる表面保護膜を形成した。このポリイ
ミド系樹脂層4上にフェノールノボラック樹脂系の感光
性樹脂(ポジ型フォトレジスト、OFPR−5000:
東京応化工業社製商品名)をスピン塗布して成膜した
後、樹脂層4の所定部分であるボンディングパッド部お
よびスクライブラインのみを選択的に除去するため、ス
ルホール寸法100μm四角およびスクライブライン幅
寸法70μmのフォトマスクを介して公知の写真食刻技
術により露光した後、水酸化テトラメチルアンモニウム
水溶液系の現像液NMD−3(濃度2.38重量%、東
京応化工業社製商品名)を食刻液に用いて23℃で80
秒間パドル法により、ポジレジスト層の現像とポリイミ
ド系樹脂膜層4のエッチングを同時に行い、ビアホール
5を形成した。
As shown in FIG. 1 (a), this polyamic acid solution is applied onto a semiconductor substrate 1 on which an Al wiring layer, an electrode 2 and an inorganic insulating film (P-Si 3 N 4 ) layer 3 are formed.
After spin coating at 3000 rpm for 30 seconds, heat treatment (prebaking) was performed at 100 ° C. for 60 seconds and further at 130 ° C. for 60 seconds on a hot plate to form a surface protective film made of a polyimide resin film layer 4 having a thickness of 2.8 μm. A phenol novolac resin-based photosensitive resin (positive photoresist, OFPR-5000:
After spin-coating a film (trade name of Tokyo Ohka Kogyo Co., Ltd.) to form a film, only the bonding pad portion and the scribe line, which are predetermined portions of the resin layer 4, are selectively removed. After exposure by a known photo-etching technique through a 70 μm photomask, tetramethylammonium hydroxide aqueous solution developer NMD-3 (concentration 2.38% by weight, product name of Tokyo Ohka Kogyo Co., Ltd.) is etched. 80 at 23 ° C for liquid
The via hole 5 was formed by simultaneously developing the positive resist layer and etching the polyimide resin film layer 4 by the paddle method for a second.

【0020】次にポジレジスト層のみを食刻する酢酸−
n−ブチルでスプレ法により室温下で60秒間処理して
ポジレジストを剥離した後、温風式乾燥器に投入し、2
00度で30分間、次いで300℃で30分間熱処理
し、膜厚2μmのビアホールの形成された第一層のポリ
イミド系樹脂膜4を得た。ビアホールの形状は良好で寸
法精度に優れ、ばらつきも見られなかった。次に図1
(b)に示すように、第一層ポリイミド系樹脂膜4上に
上記ポリアミド酸組成物を粘度140ポアズ、樹脂分濃
度18.6重量%に調製して1700rpmで20秒間ス
ピン塗布した後、ホットプレートを用いて100℃で9
0秒間、さらに125℃で90秒間熱処理し、35μm
厚の第二層ポリイミド系樹脂膜6を形成した。次にこの
第二層ポリイミド樹脂層膜6上に上記(a)と同様にし
てポジレジストを形成し、露光した後、NMD−3を用
いて23℃で260秒間パドル法によりポジレジストの
現像とポリイミド系樹脂膜6のエッチングを同時に行
い、第一層のポリイミド樹脂層4のビアホールの形状寸
法よりも大きい形状寸法のビアホールを形成した。
Next, acetic acid for etching only the positive resist layer
After treating with n-butyl by spraying at room temperature for 60 seconds to remove the positive resist, the positive resist was put into a hot air drier, and 2
Heat treatment was performed at 00 ° C. for 30 minutes and then at 300 ° C. for 30 minutes to obtain a first-layer polyimide resin film 4 having a via hole with a thickness of 2 μm. The shape of the via hole was good, the dimensional accuracy was excellent, and there was no variation. Next in FIG.
As shown in (b), the above polyamic acid composition was prepared on the first layer polyimide resin film 4 to have a viscosity of 140 poise and a resin concentration of 18.6% by weight, and spin-coated at 1700 rpm for 20 seconds, and then hot. 9 at 100 ° C using plate
Heat treatment for 0 seconds, then at 125 ℃ for 90 seconds, 35μm
A thick second layer polyimide resin film 6 was formed. Next, a positive resist is formed on the second layer polyimide resin layer film 6 in the same manner as in the above (a), and after exposure, the positive resist is developed by paddle method at 23 ° C. for 260 seconds using NMD-3. The polyimide resin film 6 was simultaneously etched to form a via hole having a larger dimension than that of the via hole of the first polyimide resin layer 4.

【0021】第二層のポリイミド系樹脂膜6上のポジレ
ジストを上記(a)と同様にして剥離した後、温風式乾
燥器を用いて200℃で30分間、さらに350℃で6
0分間熱処理し、第二層により深さ(第二層ポリイミド
樹脂層膜の厚さ)が20μmのビアホールとした。次に
ポリイミド系樹脂膜4、6をマスク材としてドライエッ
チング装置(アルバック社製:CSE−1110)を用
いて酸素と四弗化炭素の比率が10/100SCCMの
混合ガスで圧力2.5kg/cm2 、RFパワー450Wで
異方性エッチング法で90秒間ドライエッチング処理を
行い、図1(c)に示すようにビアホール5の底部のA
lボンディングパッド表面を露出させた。露出部7の形
状は、図1(c)の下部に上面図を示すように、Alボ
ンディングパッド2の寸法より小さく、かつ寸法精度の
良好なものであった。第一層と第二層ポリイミド系樹脂
膜からなる表面保護膜の膜厚はドライエッチングにより
第二層ポリイミド系樹脂膜6が0.7μm減少し、2
1.3μmであった。
The positive resist on the second layer polyimide resin film 6 was peeled off in the same manner as in (a) above, and then the hot air dryer was used for 30 minutes at 200 ° C. and then at 350 ° C. for 6 minutes.
Heat treatment was performed for 0 minutes to form a via hole having a depth (thickness of the second layer polyimide resin layer film) of 20 μm by the second layer. Next, using a dry etching device (CSE-1110 manufactured by ULVAC, Inc.) with the polyimide resin films 4 and 6 as a mask material, a mixed gas having a ratio of oxygen and carbon tetrafluoride of 10/100 SCCM is used and the pressure is 2.5 kg / cm. 2. Dry etching was performed for 90 seconds by anisotropic etching with an RF power of 450 W, and as shown in FIG.
l The surface of the bonding pad was exposed. The shape of the exposed portion 7 was smaller than the dimension of the Al bonding pad 2 and had good dimensional accuracy, as shown in the top view at the bottom of FIG. The film thickness of the surface protection film composed of the first layer and the second layer polyimide resin film was reduced by 0.7 μm in the second layer polyimide resin film 6 by dry etching,
It was 1.3 μm.

【0022】実施例2 実施例1において、第一層ポリイミド系樹脂膜4に感光
性ポリアミド酸組成物(PL−5035、粘度2ポア
ズ、樹脂分濃度19.7重量%、日立化成工業社製商品
名)を3300rpmで30秒間スピン塗布した後、ホ
ットプレートを用いて90℃で70秒間熱処理(ブリベ
ーク)を行い、膜厚4.7μmのポリイミド樹脂膜を形
成した。次に公知の写真食刻技術により露光した後、N
−メチル−2−ピロリドンを主成分とする現像液PL−
DEVELOPER−2N(日立化成工業社製商品名)
を用いて、24℃で60秒間静止パドル法によりポリイ
ミド樹脂膜の現像を行い、寸法精度の良いビアホール5
を形成し、窒素雰囲気の乾燥機を用いて140℃で30
分間、次いで200℃で30分間、さらに330℃で6
0分間熱処理して得られたポリイミド樹脂膜の厚みは2
μmであった以外は実施例1と同様にして第二層ポリイ
ミド系樹脂膜6を形成した。この表面保護膜は、ドライ
エッチング処理により良好なAl配線層および電極2を
露出することができた。
Example 2 In Example 1, a photosensitive polyamic acid composition (PL-5035, viscosity 2 poise, resin content concentration 19.7% by weight, manufactured by Hitachi Chemical Co., Ltd.) was used for the first layer polyimide resin film 4. Was spin-coated at 3300 rpm for 30 seconds and then heat-treated (bribake) at 90 ° C. for 70 seconds using a hot plate to form a polyimide resin film having a thickness of 4.7 μm. Then, after exposing by a known photo-etching technique, N
-Developer PL containing methyl-2-pyrrolidone as a main component-
DEVELOPER-2N (trade name, manufactured by Hitachi Chemical Co., Ltd.)
The polyimide resin film is developed by a static paddle method at 24 ° C. for 60 seconds using a via hole 5 with high dimensional accuracy.
At 30 ° C. at 140 ° C. using a dryer in a nitrogen atmosphere.
Minutes, then 200 ° C for 30 minutes, then 330 ° C for 6 minutes
The thickness of the polyimide resin film obtained by heat treatment for 0 minutes is 2
The second layer polyimide resin film 6 was formed in the same manner as in Example 1 except that the thickness was μm. This surface protective film was able to expose the favorable Al wiring layer and the electrode 2 by the dry etching treatment.

【0023】比較例1 実施例1において、ブリベーク後の膜厚が35μmのポ
リイミド系樹脂膜を表面保護膜として形成した以外は、
実施例1と同様にしてポリイミド系樹脂膜のパターン化
および無機絶縁膜のドライエッチングを行った。このと
きの半導体装置の製造方法の説明図を図2に示した。図
2(a)におけるポリイミド系樹脂膜10の形成および
パターン化を、図1の第二層ポリイミド系樹脂膜の形成
およびパターン化の条件と同様にして行い、また図2
(a)におけるビアホール5A、5Bの底部の無機絶縁
層3のドライエッチングも実施例1と同様の方法で行っ
た。ドライエッチング後のポリイミド系樹脂膜10の膜
厚は19.3μmであったが、ビアホール5A、5Bの
形状が丸型に近く、半導体基板面内での寸法のばらつき
が見られたため、Alボンディングパッド上部の露出部
7A、7B(オーバエッチング発生)の形状も、その下
部に上面図を示すように、丸形を呈しており、また露出
部7Bでは無機絶縁膜3の寸法のほうが大きくAlボン
ディングパッド2表面の全面が完全に露出していた。
Comparative Example 1 In Example 1, except that a polyimide resin film having a film thickness of 35 μm after bribking was formed as a surface protective film.
Patterning of the polyimide resin film and dry etching of the inorganic insulating film were performed in the same manner as in Example 1. An explanatory view of the method for manufacturing the semiconductor device at this time is shown in FIG. The formation and patterning of the polyimide resin film 10 in FIG. 2A is performed under the same conditions as the formation and patterning of the second layer polyimide resin film of FIG.
Dry etching of the inorganic insulating layer 3 at the bottoms of the via holes 5A and 5B in (a) was also performed in the same manner as in Example 1. The thickness of the polyimide-based resin film 10 after dry etching was 19.3 μm, but the via holes 5A and 5B had a shape close to a round shape, and the dimensional variation within the semiconductor substrate surface was observed. The upper exposed portions 7A and 7B (occurrence of over-etching) also have a round shape as shown in the top view below, and the exposed portion 7B has a larger size of the inorganic insulating film 3 than the Al bonding pad. 2 The entire surface was completely exposed.

【0024】[0024]

【発明の効果】本発明の製造方法によれば、膜厚の厚い
ポリイミド系樹脂膜を用いてパターンを形成した場合で
もポリイミド系樹脂膜のパターン形状寸法に優れるた
め、Alボンディングパッド部表面を精度よく露出させ
ることができ、耐湿信頼性等に優れた不良発生の少ない
半導体装置を得ることができる。
According to the manufacturing method of the present invention, even when a pattern is formed using a thick polyimide resin film, the pattern shape dimension of the polyimide resin film is excellent, so that the surface of the Al bonding pad portion can be accurately measured. It is possible to obtain a semiconductor device which can be well exposed and is excellent in moisture resistance reliability and the like, and in which few defects occur.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法の一実施例を示
す説明図。
FIG. 1 is an explanatory view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

【図2】従来の半導体装置の製造方法を示す説明図。FIG. 2 is an explanatory diagram showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1…半導体基板、2…Al配線層および電極、3…無機
絶縁膜層、4…第一層ポリイミド系樹脂膜(保護膜)、
5、5A、5B…ビアホール、6…第二層ポリイミド系
樹脂膜(保護膜)、7、7A、7B…露出部、10…ポ
リイミド系樹脂膜。
1 ... Semiconductor substrate, 2 ... Al wiring layer and electrode, 3 ... Inorganic insulating film layer, 4 ... First layer polyimide resin film (protective film),
5, 5A, 5B ... Via holes, 6 ... Second layer polyimide resin film (protective film), 7, 7A, 7B ... Exposed part, 10 ... Polyimide resin film.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/28 301 L 8826−4M 21/312 B 7352−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 21/28 301 L 8826-4M 21/312 B 7352-4M

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 無機絶縁膜が形成された基板上に、有機
四塩基酸二無水物とジアミンとを有機溶剤中で反応させ
て得られるポリアミド酸溶液を塗布し、熱処理した後、
ポリイミド系樹脂膜のビアホールを形成し、該ポリイミ
ド系樹脂膜をマスク材として上記基板上の無機絶縁膜を
ドライエッチングして半導体装置を製造する方法におい
て、前記ポリイミド系樹脂膜のビアホールを形成する際
に、第一層のポリイミド系樹脂膜のビアホールを形成し
た後、さらに該ビアホール上に第一層のポリイミド系樹
脂膜より厚い膜厚の第二層のポリイミド系樹脂膜のビア
ホールを形成することを特徴とする半導体装置の製造方
法。
1. A polyamic acid solution obtained by reacting an organic tetrabasic acid dianhydride and a diamine in an organic solvent is applied on a substrate on which an inorganic insulating film is formed, and after heat treatment,
In the method of forming a via hole of a polyimide resin film and manufacturing a semiconductor device by dry-etching the inorganic insulating film on the substrate using the polyimide resin film as a mask material, when forming the via hole of the polyimide resin film In addition, after forming a via hole of the first layer polyimide resin film, further forming a via hole of the second layer polyimide resin film thicker than the first layer polyimide resin film on the via hole. A method for manufacturing a characteristic semiconductor device.
【請求項2】 第一層のポリイミド系樹脂膜の膜厚を3
μm以下の範囲とし、かつ該第二層のポリイミド系樹脂
膜のビアホールの形状寸法を、第一層のポリイミド系樹
脂膜のビアホールの形状寸法より大とする請求項1記載
の半導体装置の製造方法。
2. The thickness of the polyimide resin film of the first layer is 3
2. The method of manufacturing a semiconductor device according to claim 1, wherein the via hole of the polyimide resin film of the second layer is larger than the via hole of the polyimide resin film of the first layer. .
JP5323952A 1993-12-22 1993-12-22 Manufacture of semiconductor device Pending JPH07183296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5323952A JPH07183296A (en) 1993-12-22 1993-12-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5323952A JPH07183296A (en) 1993-12-22 1993-12-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH07183296A true JPH07183296A (en) 1995-07-21

Family

ID=18160466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5323952A Pending JPH07183296A (en) 1993-12-22 1993-12-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH07183296A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287750B1 (en) 1996-05-17 2001-09-11 Nec Corporation Method of manufacturing semiconductor device in which opening can be formed with high precision
JP2009283593A (en) * 2008-05-21 2009-12-03 Seiko Epson Corp Method of manufacturing semiconductor apparatus
JP2010067650A (en) * 2008-09-09 2010-03-25 Sharp Corp Semiconductor device, manufacturing method for the semiconductor device, and power module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287750B1 (en) 1996-05-17 2001-09-11 Nec Corporation Method of manufacturing semiconductor device in which opening can be formed with high precision
JP2009283593A (en) * 2008-05-21 2009-12-03 Seiko Epson Corp Method of manufacturing semiconductor apparatus
JP2010067650A (en) * 2008-09-09 2010-03-25 Sharp Corp Semiconductor device, manufacturing method for the semiconductor device, and power module

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