JPH07183254A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form stable low-resistance contacts without lowering the element separating characteristics of the contacts by setting the ion implanting angle at a specific value or larger when the ion of an impurity is obliquely implanted into polycrystalline silicon in contact holes. CONSTITUTION:After forming contact holes through an insulating film 110 formed on a semiconductor substrate having a functional area, a first polycrystalline silicon layer 111 is formed on the entire surface of the semiconductor substrate coated with the film 110 by chemical vapor growth. Then the ion of an impurity is obliquely implanted into the silicon 111 at an angle equal to or wider than tan<-1> (2X(radius of contact hole-thickness of first polycrystalline silicon film)/(depth of contact hole). Then, after forming second polycrystalline silicon 112 by chemical vapor deposition, the first and second silicon layers 111 and 112 are etched off from the entire surface of the substrate except those in the contact holes. The thickness of the first silicon layer 111 is set at, for example, about <1/3 of the diameter of the contact holes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a contact manufacturing method.

[0002]

2. Description of the Related Art Conventionally, as a technique for forming a contact in a semiconductor device, for example, Japanese Patent Laid-Open No. 2-281620.
There is a method of manufacturing a semiconductor device proposed in. This conventional technique will be described with reference to FIGS. 6, 7, 8, 9 and 10. In the NMOS semiconductor device, first, as shown in FIG. 6A, a device isolation film (LOCOS) (302) and an N-channel LD are formed on a P-type semiconductor substrate (301).
N ⁺ diffusion layers (303) and N ⁻ diffusion layers (304) which are source / drain regions of the D transistor, a gate insulating film (gate oxide film) (305), and N ⁺ polycrystalline silicon (306) which is a gate electrode. Approximately 1.5 phosphosilicate glass (PSG) film (308) is formed on the silicon oxide film (307).
An interlayer film (310) (this is a combination of 307 and 308) formed by μm chemical vapor deposition is formed. Next, as shown in FIG. 6B, a contact hole having a radius of about 0.5 μm is patterned by using a photoresist (309).

Next, as shown in FIG. 7C, the interlayer film (310) is etched by plasma etching using the photoresist (309) as a mask until the N ⁺ diffusion layer (303) is exposed. Then, after removing the photoresist, FIG.
As shown in (d), the first polycrystalline silicon (311)
Is grown to a thickness of about 0.2 μm by chemical vapor deposition.
Next, as shown in FIGS. 8E and 8F, oblique rotation ion implantation is performed so as to enter the contact bottom portion and the contact side surface. Next, as shown in FIG. 9G, the thickness of the second polycrystalline silicon (312) is reduced to about 0.5 μm by chemical vapor deposition.
m, fill the contact hole, and then, as shown in FIG.
As shown in (h), heat treatment is performed in nitrogen at 900 ° C. for 20 minutes to activate the impurities implanted in the polycrystalline silicon and sufficiently diffuse into the polycrystalline silicon. Next in FIG.
By etching back as shown in 0 (i), polycrystalline silicon remains in the contact hole and a buried contact is obtained.

[0004]

In recent years, as semiconductor devices have been highly integrated, the element separation intervals have been reduced and the contact intervals have been reduced accordingly. In order to reduce the resistance of the contact, phosphorus is doped by the oblique rotation ion implantation method in which both the contact bottom portion and the contact side surface are implanted. In this method, the impurities injected into the bottom surface are diffused in the element isolation direction by activation and subsequent heat treatment, and the element isolation interval between contacts is shortened.
At this time, when a potential difference occurs between the contacts across the element isolation, the parasitic transistor formed between the N ⁺ layers under the contact deteriorates the element isolation, resulting in a decrease in the threshold voltage (VT2) of the parasitic transistor, resulting in a large current leak. was there. Moreover, in order to suppress the above-mentioned VT2 decrease,
There is a problem that the contact resistance becomes too high when the amount of impurities injected into the contact portion is reduced.

Particularly, as shown in FIG. 10 (i), when a wiring layer made of a silicide of a refractory metal such as tungsten silicide or titanium silicide is deposited after the contact hole is filled with a polycrystalline silicon layer (see FIG. (Not shown), the problem becomes serious. That is, the impurities introduced into the first polycrystalline silicon on the inner wall of the contact hole are diffused into the silicide of the refractory metal by the subsequent heat treatment, and the impurity concentration of the first polycrystalline silicon on the inner wall of the contact hole is reduced. It may drop extremely and show an abnormally high resistance of several tens of MΩ. In order to prevent this phenomenon, it is necessary to introduce impurities in the first polycrystalline silicon on the inner wall of the contact hole so as to have a higher concentration. In this case, however, the problem of deterioration of the element isolation characteristic VT2 is particularly serious in the conventional technique. Is. It is an object of the present invention to provide a method for forming a stable low resistance contact without deteriorating element isolation characteristics.

[0006]

DISCLOSURE OF THE INVENTION The present invention is to solve the above-mentioned problems and comprises a step of forming a contact hole in an insulating film formed on a semiconductor substrate having a functional region, and a step of forming the insulating film. A step of performing chemical vapor deposition on the entire surface of the semiconductor substrate having the first polycrystalline silicon layer,
The impurity is obliquely ion-implanted at an angle of not less than n ⁻¹ (2 × (contact opening radius−first polycrystalline silicon film thickness) / (contact hole depth (insulating film thickness))
Of the first polycrystalline silicon, the step of implanting the second polycrystalline silicon into the polycrystalline silicon, the step of chemically vapor-depositing the second polycrystalline silicon, and the step of completely etching the first and second polycrystalline silicon while leaving the contact holes in the contact holes. And the angle at which the impurity is obliquely ion-implanted is tan ⁻¹ (2 × contact opening radius−2 × first polycrystalline silicon film thickness) or less. The method is also a method for manufacturing a semiconductor device, characterized in that the thickness of the first polycrystalline silicon layer is less than about 1/3 of the diameter of the contact hole.

[0007]

In the present invention, when impurities are obliquely ion-implanted into polycrystalline silicon in a contact hole, the ion implantation angle is tan ^-1 (2 x (contact hole radius-polycrystalline polysilicon thickness) / contact). Impurities are not injected into the bottom of the contact hole by implanting at an angle equal to or greater than the depth of the hole).

[0008]

Embodiments of the present invention are shown in FIGS. 1, 2, 3 and 4.
Will be explained. When the present invention is applied to an NMOS type semiconductor device, first, as shown in FIG. 1A, an element isolation film (LO) is formed on a P type semiconductor substrate (P type silicon substrate) (101).
COS) (102) and the N ⁺ diffusion layer (10) which is the source / drain region of the N-channel LDD transistor.
3), N ^- diffusion layer (104), gate insulating film (gate oxide film) (105), N ⁺ polycrystalline silicon (106) which is a gate electrode, and silicon oxide film (107) on top of phosphosilicate glass (PSG). ) Interlayer film (110) (107 and 10) obtained by growing the film (108) by chemical vapor deposition of about 1.0 μm.
8 together).

Next, as shown in FIG. 1B, a contact hole having a radius of about 0.2 μm is patterned using a photoresist (109). Next, as shown in FIG. 2C, the interlayer film (1) is formed by using the photoresist (109) as a mask.
10) by plasma etching of the N ⁺ diffusion layer (10
Etch until 3) appears. Next, after removing the photoresist, as shown in FIG. 2D, a first polycrystalline silicon (111) is grown to a thickness of about 0.1 μm by chemical vapor deposition. The thickness of the first polycrystalline silicon (111) is preferably less than about 1/3 of the contact hole diameter. Next, as shown in FIG. 3E, an N-type impurity such as phosphorus (P) is obliquely ion-implanted to dope the polycrystalline silicon (111) on the side surface of the contact hole opening with phosphorus (P).

Here, as to the implantation angle, as shown in FIG. 5, the depth of the contact hole is (h), the radius of the contact hole (opening) is (r), and the film thickness of the first polycrystalline silicon is (a). Then, the implantation angle (θ) is tan ⁻¹ (2r-2a) / h <θ <tan ⁻¹ (2r
/ H). For example, r = 0.2 μm, h = 1.2 μ
When m and a = 0.1 μm, tan ⁻¹ (0.17) =
Perform at 9.6 degrees. As a result, as shown in FIG. 3F, the distribution is such that the bottom surface of the contact hole is not injected.
The depth (h) of the contact hole is equal to the “thickness of the insulating film”.

Next, as shown in FIGS. 4 (i) and 4 (j), a second polycrystalline silicon (112) is grown to a thickness of about 600 nm and then etched back, and thereafter, for activation of impurities, Heat treatment is performed in nitrogen at 850 ° C. for 30 minutes. As a result, P diffuses into the polycrystalline silicon to obtain a buried contact.

[0012]

According to the present invention, the angle is tan ⁻¹ (2 × (contact hole radius −
Impurities are not injected into the bottom of the contact hole by injecting at an angle of (polycrystalline polysilicon thickness) / contact hole depth) or more. Therefore, heat treatment for activating the impurities and heat treatment in the subsequent process are performed on the substrate. It is possible to minimize the deterioration of VT2 due to the diffused impurities.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a process of an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view of the process of the embodiment of the present invention following FIG.

FIG. 3 is a vertical cross-sectional view of the process of the embodiment of the present invention, following FIG. 2;

FIG. 4 is a vertical cross-sectional view of the process of the embodiment of the present invention, following FIG.

FIG. 5 is an explanatory diagram of a contact hole according to the embodiment of this invention.

FIG. 6 is a vertical cross-sectional view of a conventional process.

FIG. 7 is a vertical cross-sectional view following FIG. 6 of the process of the related art.

FIG. 8 is a vertical cross-sectional view of the process of the related art, continuing from FIG. 7;

FIG. 9 is a vertical cross-sectional view following FIG. 8 of the process of the related art.

FIG. 10 is a vertical cross-sectional view of the process of the related art, continuing from FIG. 9;

[Explanation of symbols]

101, 301 P-type silicon substrate 102, 302 LOCOS 103, 303 N ⁺ diffusion layer 104, 304 N ⁻ diffusion layer 105, 305 Gate oxide film 106, 306 N ⁺ polycrystalline polysilicon 107, 307 Silicon oxide film 108, 308 PSG Films 109, 309 Photoresist 110, 310 Interlayer film 111, 311 First polycrystalline silicon 112, 312 Second polycrystalline silicon

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/08 331 9170-4M

Claims (3)

[Claims] 1. A step of forming a contact hole in an insulating film formed on a semiconductor substrate having a functional region, and a chemical vapor deposition of a first polycrystalline silicon layer on the entire surface of the semiconductor substrate having the insulating film. Process and impurities tan ⁻¹
(2 × (contact opening radius−first polycrystalline silicon film thickness) / (contact hole depth)) Impurity is obliquely ion-implanted into the first polycrystalline silicon at an angle of not less than 2. A method of manufacturing a semiconductor device, comprising: a step of performing chemical vapor deposition of polycrystalline silicon, and a step of completely etching the first and second polycrystalline silicon, leaving a contact hole. 2. The angle at which the impurities are obliquely ion-implanted is t
The method of manufacturing a semiconductor device according to claim 1, wherein the value is not more than an ⁻¹ (2 × contact opening radius−2 × first polycrystalline silicon film thickness). 3. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the first polycrystalline silicon layer is less than about 1/3 of the diameter of the contact hole.