JPH07182970A - Manufacture of electron source - Google Patents
Manufacture of electron sourceInfo
- Publication number
- JPH07182970A JPH07182970A JP34547993A JP34547993A JPH07182970A JP H07182970 A JPH07182970 A JP H07182970A JP 34547993 A JP34547993 A JP 34547993A JP 34547993 A JP34547993 A JP 34547993A JP H07182970 A JPH07182970 A JP H07182970A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- forming
- electron
- applying
- electron emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、画像形成装置等に用い
られる表面伝導型電子放出素子を用いた電子源の製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electron source using a surface conduction electron-emitting device used in an image forming apparatus or the like.
【0002】[0002]
【従来の技術】従来、電子放出素子として熱電子源と冷
陰極電子源の2種類が知られている。冷陰極電子源には
電界放出型、金属/絶縁層/金属型や表面伝導型電子放
出素子(以下SCEと記す)等が有る。2. Description of the Related Art Conventionally, two types of electron emitters, a thermoelectron source and a cold cathode electron source, are known. The cold cathode electron source includes a field emission type, a metal / insulating layer / metal type, a surface conduction type electron emitting device (hereinafter referred to as SCE), and the like.
【0003】SCEは基板上に形成された小面積の薄膜
に、膜面に平行に電流を流すことにより、電子放出が生
ずる現象を利用するものである。その典型的な構成とし
ては、絶縁性基板上に1対の素子電極を設け、該電極を
連絡するように金属酸化物薄膜を成膜し、該薄膜を予め
フォーミングと呼ばれる通電処理により局所的に破壊し
たもので、フォーミング前後の薄膜は基本的に微粒子膜
より形成されている。その構成例を図5に示す。従来、
SCEのフォーミング処理としては、DC、AC、パル
ス波が用いられ、特にパルス波の場合の波形としては、
特開平4−28139号に開示されているように、三角
波又は矩形波が用いられてきた。The SCE utilizes a phenomenon in which electron emission occurs when a current is passed through a thin film having a small area formed on a substrate in parallel with the film surface. As a typical configuration thereof, a pair of element electrodes are provided on an insulating substrate, a metal oxide thin film is formed so as to connect the electrodes, and the thin film is locally preliminarily subjected to an electric current treatment called forming. The thin film before and after forming is basically a fine particle film. An example of the configuration is shown in FIG. Conventionally,
DC, AC, and pulse waves are used for the SCE forming process. Particularly, in the case of pulse waves,
As disclosed in Japanese Patent Application Laid-Open No. 4-28139, a triangular wave or a rectangular wave has been used.
【0004】SCEはある電圧(閾値電圧)以上の素子
電圧を印加することにより急激に放出電流が増加し、一
方上記閾値電圧未満では放出電流がほとんど検出されな
い非線形素子である。SCEの放出電流は素子電圧で制
御でき、また放出電荷は素子電圧の印加時間により制御
できる。さらに、このSCEを複数個配置してなる電子
源と、該電子源より放出された電子によって可視光を発
光せしめる蛍光体とを組み合わせることにより種々の表
示装置が構成されるが、大画面の装置でも比較的容易に
製造でき、且つ表示品位に優れた自発光型表示装置であ
るため、CRTに替わる画像形成装置として期待されて
いる。The SCE is a non-linear element in which the emission current rapidly increases by applying an element voltage equal to or higher than a certain voltage (threshold voltage), while the emission current is hardly detected below the threshold voltage. The emission current of SCE can be controlled by the device voltage, and the emission charge can be controlled by the application time of the device voltage. Further, various display devices are configured by combining an electron source including a plurality of SCEs and a phosphor that emits visible light by the electrons emitted from the electron source. However, since it is a self-luminous display device that can be manufactured relatively easily and has excellent display quality, it is expected as an image forming apparatus that replaces a CRT.
【0005】[0005]
【発明が解決しようとする課題】上記従来のフォーミン
グ処理は、フォーミング電圧が小さい場合には素子に十
分な亀裂が発生せず、逆にフォーミング電圧が大きいと
素子に過大な電流が流れてしまう。従ってフォーミング
電圧の適正値は狭く、素子毎に素子抵抗にバラツキが有
る場合には、同じフォーミング電圧を印加して処理する
と、電子放出部となる亀裂部及び島構造の形状が素子毎
にばらつき、素子特性が不均一になるという問題があっ
た。In the conventional forming process described above, when the forming voltage is low, the element does not crack sufficiently, and when the forming voltage is high, an excessive current flows through the element. Therefore, the proper value of the forming voltage is narrow, and when there is variation in the element resistance for each element, the same forming voltage is applied and processed, and the shapes of the crack portion and the island structure which become the electron emitting portion vary from element to element, There is a problem that the device characteristics become non-uniform.
【0006】[0006]
【課題を解決するための手段及び作用】表面伝導型電子
放出素子を多数個配置してなる電子源の製造方法であっ
て、上記電子放出素子の電子放出部を形成するための通
電処理として、一定の電圧V0を一定期間t0 印加した
後該V0 よりも高い電圧を印加することを特徴とする電
子源の製造方法であり、上記V0 印加後に印加されるV
0 よりも高い電圧としては、一定電圧、或いは時間の増
加関数である電圧が用いられる。A method of manufacturing an electron source in which a large number of surface conduction electron-emitting devices are arranged, wherein an energization process for forming an electron-emitting portion of the electron-emitting device is as follows. A method for manufacturing an electron source, which comprises applying a constant voltage V 0 for a certain period of time t 0 and then applying a voltage higher than the V 0, wherein V applied after V 0 is applied.
As the voltage higher than 0 , a constant voltage or a voltage that is an increasing function of time is used.
【0007】本発明では上記の如く、一定電圧V0 と該
V0 よりも高い電圧とを組み合わせて印加することによ
り、フォーミング前の素子抵抗が素子毎にばらついてい
ても、素子に過大な電流が流れたり、或いは逆に素子に
流れる電流が不十分となることを防止したものである。In the present invention, as described above, by applying the constant voltage V 0 and the voltage higher than V 0 in combination, even if the element resistance before forming varies from element to element, an excessive current flows through the element. Is prevented, or conversely, the current flowing through the element is prevented from becoming insufficient.
【0008】[0008]
(実施例1)図1は本発明第1の実施例における、フォ
ーミング電圧波形を示す。図1のフォーミング波形は、
図2に示す電子源製造工程において、電子放出部を形成
するために電極間に印加される。(Embodiment 1) FIG. 1 shows a forming voltage waveform in the first embodiment of the present invention. The forming waveform of FIG. 1 is
In the electron source manufacturing process shown in FIG. 2, a voltage is applied between the electrodes to form an electron emitting portion.
【0009】(1)絶縁性基板1を洗剤、純水及び有機
溶剤により十分に洗浄後、真空蒸着法、スパッタ法等に
より素子電極材料を堆積後、フォトリソグラフィ技術に
より絶縁性基板1の面上に素子電極5、6を形成する
(a)。(1) After the insulating substrate 1 is thoroughly washed with a detergent, pure water and an organic solvent, a device electrode material is deposited by a vacuum vapor deposition method, a sputtering method or the like, and then on the surface of the insulating substrate 1 by a photolithography technique. Element electrodes 5 and 6 are formed on the substrate (a).
【0010】(2)絶縁性基板1上に設けられた素子電
極5と素子電極6との間に有機金属溶液を塗布して放置
することにより、有機金属薄膜を形成する。尚、有機金
属溶液とは、Pd,Ru,Ag,Au,Ti,In,C
u,Cr,Fe,Zn,Sn,Ta,W,Pb等の金属
を主元素とする有機化合物の溶液である。この後、有機
金属薄膜を加熱焼成し、リフトオフ、エッチング等によ
りパターニングし、電子放出部形成用薄膜2を形成する
(b)。尚、ここでは、有機金属溶液の塗布法により説
明したが、これに限るものではなく、真空蒸着法、スパ
ッタ法、化学的気相堆積法、分散塗布法、ディッピング
法、スピンナー法等によって形成される場合もある。(2) An organometallic thin film is formed by applying an organometallic solution between the element electrodes 5 and the element electrodes 6 provided on the insulating substrate 1 and leaving them to stand. The organic metal solution means Pd, Ru, Ag, Au, Ti, In, C.
It is a solution of an organic compound containing a metal such as u, Cr, Fe, Zn, Sn, Ta, W, Pb as a main element. After that, the organometallic thin film is heated and baked, and is patterned by lift-off, etching or the like to form the electron emission portion forming thin film 2 (b). Although the organic metal solution coating method has been described here, the invention is not limited to this, and it may be formed by a vacuum vapor deposition method, a sputtering method, a chemical vapor deposition method, a dispersion coating method, a dipping method, a spinner method, or the like. There are also cases.
【0011】(3)続いて、素子電極5、6間に不図示
の電源により図1に示した電圧波形のフォーミング電圧
を印加し、電子放出部形成用薄膜2を局所的に破壊、変
形もしくは変質せしめて電子放出部3を形成する
(c)。(3) Subsequently, a forming voltage having the voltage waveform shown in FIG. 1 is applied between the device electrodes 5 and 6 by a power source (not shown) to locally destroy or deform the electron emission portion forming thin film 2. The electron emitting portion 3 is formed by being altered (c).
【0012】図1中、t1 及びt2 は電圧波形のパルス
幅とパルス間隔であり、好ましくはt1 は1μs〜10
ms、t2 は10μs〜100msとし、時間t0 は
0.5t1 〜0.95t1 、V0 は4〜10V程度、ピ
ーク電圧V1 は1.1V0 以上とし、処理時間は真空雰
囲気下で数十秒間程度で適宜設定した。In FIG. 1, t 1 and t 2 are the pulse width and pulse interval of the voltage waveform, preferably t 1 is 1 μs to 10 μs.
ms, t 2 are 10 μs to 100 ms, time t 0 is 0.5 t 1 to 0.95 t 1 , V 0 is about 4 to 10 V, peak voltage V 1 is 1.1 V 0 or more, and processing time is in a vacuum atmosphere. Was set appropriately for about several tens of seconds.
【0013】このような電圧波形を用いてフォーミング
処理を行なうことにより、一定電圧V0 によって薄膜2
が緩やかに加熱された後、V0 よりも高い電圧印加によ
り短時間で電子放出部3が形成される。従って素子抵抗
にバラツキが有っても、過負荷になることなく且つ確実
にフォーミングを行なうことができる。By performing the forming process using such a voltage waveform, the thin film 2 is formed at a constant voltage V 0 .
After being gently heated, the electron emitting portion 3 is formed in a short time by applying a voltage higher than V 0 . Therefore, even if there are variations in element resistance, forming can be performed reliably without overload.
【0014】(実施例2)図3に本発明第2の実施例に
おけるフォーミング電圧波形を示す。本実施例における
製造工程は基本的に実施例1と同じであるが、高電圧部
分が一定の電圧パルスで構成されており、実施例1と同
様の効果が得られる。(Embodiment 2) FIG. 3 shows a forming voltage waveform in the second embodiment of the present invention. The manufacturing process of this embodiment is basically the same as that of the first embodiment, but the high voltage portion is constituted by a constant voltage pulse, and the same effect as that of the first embodiment can be obtained.
【0015】(実施例3)図4に本発明第3の実施例に
おけるフォーミング電圧波形を示す。本実施例における
製造工程は基本的に実施例1と同一であるが、高電圧パ
ルスが直線的に増加する電圧パルスによって構成されて
おり、実施例1と同様の効果が得られる。(Embodiment 3) FIG. 4 shows a forming voltage waveform in a third embodiment of the present invention. The manufacturing process of this embodiment is basically the same as that of the first embodiment, but the high-voltage pulse is composed of voltage pulses that increase linearly, and the same effect as that of the first embodiment can be obtained.
【0016】[0016]
【発明の効果】以上説明したように、一定電圧とそれよ
りも高い電圧とを組み合わせてフォーミング処理するこ
とにより、素子間に抵抗のばらつきが有った場合も、過
不足なく処理を行なうことができ、素子特性が均一な電
子源を製造することができる。As described above, by performing a forming process by combining a constant voltage and a voltage higher than the constant voltage, even if there is a variation in resistance between elements, the process can be performed without excess or deficiency. It is possible to manufacture an electron source having uniform device characteristics.
【図1】本発明第1の実施例におけるフォーミング電圧
波形を示す図である。FIG. 1 is a diagram showing a forming voltage waveform according to a first embodiment of the present invention.
【図2】本発明第1の実施例における電子源の製造方法
の説明図である。FIG. 2 is an explanatory diagram of a method of manufacturing an electron source according to the first embodiment of the present invention.
【図3】本発明第2の実施例におけるフォーミング電圧
波形を示す図である。FIG. 3 is a diagram showing a forming voltage waveform in the second embodiment of the present invention.
【図4】本発明第3の実施例におけるフォーミング電圧
波形を示す図である。FIG. 4 is a diagram showing a forming voltage waveform in a third embodiment of the present invention.
【図5】本発明にかかるSCEの構成を示す図である。FIG. 5 is a diagram showing a configuration of an SCE according to the present invention.
1 絶縁性基板 2 電子放出部形成用薄膜 3 電子放出部 4 電子放出部を含む薄膜 5、6、素子電極 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Electron emission part forming thin film 3 Electron emission part 4 Thin film including an electron emission part 5, 6, element electrode
Claims (3)
てなる電子源の製造方法であって、上記電子放出素子の
電子放出部を形成するための通電処理として、一定の電
圧V0 を一定期間t0 印加した後該V0 よりも高い電圧
を印加することを特徴とする電子源の製造方法。1. A method of manufacturing an electron source comprising a large number of surface conduction electron-emitting devices arranged, wherein a constant voltage V 0 is applied as an energizing process for forming an electron-emitting portion of the electron-emitting device. A method of manufacturing an electron source, characterized in that a voltage higher than V 0 is applied after applying for a certain period of time t 0 .
一定期間印加することを特徴とする請求項1記載の電子
源の製造方法。Wherein after V 0 applied, method of manufacturing an electron source according to claim 1, wherein applying a certain period higher fixed voltage than V 0.
間の増加関数であることを特徴とする請求項1記載の電
子源の製造方法。3. The method of manufacturing an electron source according to claim 1, wherein the voltage applied to the thin film after applying V 0 is an increasing function of time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34547993A JP2850090B2 (en) | 1993-12-22 | 1993-12-22 | Method of manufacturing electron-emitting device and electron source |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34547993A JP2850090B2 (en) | 1993-12-22 | 1993-12-22 | Method of manufacturing electron-emitting device and electron source |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07182970A true JPH07182970A (en) | 1995-07-21 |
JP2850090B2 JP2850090B2 (en) | 1999-01-27 |
Family
ID=18376872
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34547993A Expired - Fee Related JP2850090B2 (en) | 1993-12-22 | 1993-12-22 | Method of manufacturing electron-emitting device and electron source |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2850090B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3518854B2 (en) | 1999-02-24 | 2004-04-12 | キヤノン株式会社 | Method for manufacturing electron source and image forming apparatus, and apparatus for manufacturing them |
-
1993
- 1993-12-22 JP JP34547993A patent/JP2850090B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2850090B2 (en) | 1999-01-27 |
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