JPH07181913A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent latch-up of a driver by placing a voltage for contrast adjustment in an open state until a start and supplying it to the device. CONSTITUTION:An mXn-dot liquid crystal display 1 is driven with 1/L (n>=L>=n/2) duty, and the voltage for contrast adjustment is provided separately from a display power source. The current from a system power source is switch- controlled depending a load state and a Z state of the time constant of a transformer, and a resistance and a capacitor to supply a specific voltage, and the switch function is constituted by transistors(TR) Q1 and Q2, a resistance R1, a capacitor C, and a transformer T. Here, delay is give so that Td>LXTLCK, where TLCK is a line synchronization time right after the start and Td is the time from the start to the start of the power source for contrast adjustment of the liquid crystal display. Further, the voltage for contrast adjustment is placed in the open state until the start and supplied to the liquid crystal display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display control device used as a liquid crystal panel display.

[0002]

2. Description of the Related Art An information processing apparatus capable of operating a battery shown in FIG. 11 creates a logic control voltage, a liquid crystal voltage, etc. by a DC-DC converter based on a single voltage obtained from the battery, Supplied to the control block. The configuration of the power supply unit is the same even if the battery and the AC adapter can be used mutually.

The signal relationship at the time of turning on the power supply of the information processing apparatus is mainly that when the logic control voltage (generally + 5V) is rising, the reset signal for determining the initial operation of the logic section is the logic section. Are supplied to the logic control signal and the logic control signal rises, the reset signal is released after a predetermined time, and the logic unit operates. This predetermined time is determined from the stabilization time of the clock oscillation unit used for the logic and the number of clocks required to determine the internal processing unit after the clock is stabilized. In this reset period, the segment clock (SCK), line clock (LCK), and frame clock (FCK) as signals for controlling the liquid crystal display (LCD) may not be issued. At this time, L
+5 at the same timing as the logic control voltage on the CD side
When V (V _DD ) is supplied, an AC signal cannot be derived in the LCD, so a DC voltage application phenomenon occurs in the cell of the LCD.

[0004]

However, in the design according to the conventional example, the display power source is often started after the logic control power source has risen or immediately after the reset is released. _The rise of _EE becomes steep. At the same time, the driver IC in the LCD is driven by the signal supplied to the LCD of the display body. However, since the driver itself does not have the initial function due to the rise of V _CC of the logic control power supply, the internal register is undefined. Therefore, the common driver may turn on a plurality of lines at the same time, and the number of the plurality of simultaneous turns on increases depending on the wiring between the cold cathodes used as the backlight of the LCD. Under this condition, when V _EE of the display power supply is supplied, the inrush current in one common driver becomes excessive, causing the common driver to latch up. This latch-up phenomenon is caused by the power source of V _EE , V
_This will damage the power supply of the _CC and damage the driver and damage the LCD due to the driver's heat generation.

[0005]

[Means and Actions for Solving the Problem] A liquid crystal which drives a liquid crystal display of m × n dots at a duty of 1 / L (n ≧ L ≧ n / 2) and has a voltage for contrast adjustment separately from a power supply for display. In the display device, in the liquid crystal display control device that supplies power and voltage for the display of the liquid crystal display, the line synchronization time immediately after the start is T _LCK , and the time from the start to the start of the power supply for contrast adjustment of the liquid crystal display is T _{If d} , then T _d ＞
The liquid crystal display control device for delaying L × T _LCK , wherein the liquid crystal display device is supplied as an open state until a voltage for contrast adjustment is started. By providing a display control circuit, the display power supply is not applied when the inside of the driver is indeterminate, and the inrush current when the display power supply is applied is reduced, thus protecting the LCD cells from direct current application and latching up the driver. Is to prevent.

According to the present invention, m × n (m ≧ 640, n
≧ 400) dot liquid crystal display, 1 / L
A liquid crystal display device that is driven at a duty (n ≧ L ≧ n / 2) and has a contrast adjustment voltage separately from a display power supply, and a liquid crystal display control device that supplies the display power supply and voltage for the liquid crystal display. When the line synchronization time immediately after the information processing device is started is T _LCK , when the display power supply start of the liquid crystal display is started and when the delay time from the reset release of the information processing device start is T _d , T _d > L The liquid crystal display control device, which keeps the condition of × T _LCK and delays the rise time of the display power source to be T _d or more, wherein the contrast adjustment voltage starts to start. Up to the point where the liquid crystal display control circuit is supplied to the liquid crystal display device as an open state, Avoid application of the display power source at the time of indeterminate bar is, and, by reducing the inrush current during the display power is applied, it is to prevent the latch-up of the driver.

According to the present invention, a liquid crystal display of m × n dots is driven at a duty of 1 / L (n ≧ L ≧ n / 2), and a backlight unit for supplying display illumination from behind is integrally formed. In the liquid crystal display device, a liquid crystal display control circuit that supplies power for display of the liquid crystal display, voltage for the liquid crystal display, and power for the backlight unit is T _LCK immediately after the start, By providing a liquid crystal display control circuit characterized by the fact that T _d > L × T _LCK , where T _d is the time until the start of the power supply for the light section, the power supply for the backlight section is switched on when the driver is uncertain. By not starting the display, it is difficult to visually recognize the horizontal lines, etc. when the display is indefinite that occurs immediately after the power is turned on, and the display immediately after the power is turned on. It is to prevent the quality deterioration of the surface.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The information processing equipment capable of battery operation shown in FIG. 2 is based on a single voltage (system power supply) obtained from a battery, and has a logic control voltage V _CC and a liquid crystal voltage V.
_{EE and the} like are created by the DC-DC converters DC1 and DC2, and are used as control blocks for the logic unit LU and the liquid crystal unit LCDU, respectively, and the printer control unit PU and other control unit EU.
Is supplied with another voltage from the DC-DC converters DC3 and DC4. The structure of the power supply unit is the same even if the battery and the AC adapter can be used mutually.

The signal relationship at the time of turning on the power supply of the information processing apparatus is such that when the logic control voltage (generally +5 V) rises, the reset signal for determining the initial operation of the logic unit LU is After the logic control signal is supplied to the unit LU and rises, the reset signal is released after a predetermined time, and the logic unit LU operates. The predetermined time is determined from the stabilization time of the clock oscillator used in the logic unit LU and the number of clocks required to determine the internal processing unit after the clock is stabilized. In this reset period, the segment clock (SCK), the line clock (LCK), and the frame clock (FCK) as signals for controlling the liquid crystal display (LCD) of the liquid crystal unit LCDU may not be issued. At this time, if +5 V (V _DD ) is supplied to the LCD side at the same timing as the logic control voltage, an AC signal cannot be derived in the LCD, and a DC voltage application phenomenon occurs in the LCD cell. LC
Since it is related to the life of D, the liquid crystal unit LCDU having the DC protection circuit DPC as shown in FIG. 3 is used in the liquid crystal unit LCDC. In the figure, GDU is an AC signal generating unit / dividing unit. DPC is a direct current application protection unit. DU
Is an LCD voltage generator. The LCD is a display body.

FIG. 1 shows a power supply circuit for LCD display, which has a dedicated control voltage (V _adj ) for adjusting the contrast of the LCD.
Using V _adj is advantageous for changing the value of the variable resistor (V _R ) for contrast adjustment, and uses V _adj for the display power supply (V _EE ) of the LCD and GND or V _DD. It can be implemented by inserting V _R between them. Figure 3
In the operation of, when the signal is not supplied to the LCD, when the AC signal is not generated, V _REF that determines the voltage applied to the display LCD is opened from V _adj to display L
The voltages V _{1 to} V ₅ applied to the CD have almost the same potential, which is an operation principle that can protect the direct current application to the display body LCD.

The V _EE power supply circuit for the LCD of the information processing apparatus using the display LCD having this structure is started by the display LC.
It only has to be delayed from V _{CC of} D.

FIG. 1 shows a DC-DC converter 2 shown in FIG.
The power supply circuit for LCD display, which has another voltage for contrast adjustment and also protects DC application, will be described in detail. This circuit is a DC-DC converter, which is generally called the RCC system, and it switches the current from the system power supply depending on the load state and the Z state of the time constant of the transformer T and the resistors R and C. And supplies a predetermined voltage.
1, Q2, resistor R1, capacitor C, and transformer T. It is the current supplied by V _CC that essentially drives the transistor Q2 switch, which is determined by resistor R2. The load characteristic of the display power supply is determined by the base current of the transistor Q2.

D1 is a diode. C2 is a capacitor. D2 is a diode. ZD is a Zener diode, which returns to the transistor Q2. VR is a variable resistor, and the voltage generated by the resistance division is displayed on the display body LC as V _adj via the transistor Q3 as a switch.
Supplied to D. The switch operation of this Q3 is a transistor Q that operates using the output from a resistor Rd, a diode Dd, and a capacitor Cd that form a circuit DC that inputs a reset signal and delays it for T _d > L × T _LCK time.
4 and Q5 switch operation. Where T
_LCK is the line synchronization time, 1 / L is the duty, and _Td is the time from start to power supply start.

The power supply sequence of this circuit and the whole is shown in FIG.
The timing chart of FIG. The present embodiment relates to a system in which the reset signal is'H 'level to start the system.

After the system power supply is turned on S1, the voltage S2 of V _CC is determined with a delay of a delay time determined by the configuration of the V _CC power supply. The reset signal S3 differs depending on the circuit used, but when a voltage detection type reset IC is used,
The state is indefinite until V _CC reaches 0.7 V, and 0.
It becomes'L 'level when it is more than 7V. Further reset I
The'L 'level period of the output of C is determined by the external capacitor capacity. After a lapse of time determined by the above conditions, the reset signal C3 becomes the “H” level, and the system is activated. This activation causes the LCD signal to be generated and supplied to the LCD when the logic state is determined such that the LCD signal is generated. The cycle of the line clock LCKS6 and the frame clock FCKS7 immediately after the reset is released is in the initial state in the case of the logic that makes the frequency division variable, and the predetermined cycle is the predetermined frequency division value in the register that determines the frequency division. After writing. The determination of the delay time in the present invention is calculated from the cycle of the line clock LCK immediately after reset release. 1 / in LCD
At the L duty, the common side is selected one for the common side output line L in the steady state. However, immediately after applying V _CC ,
Since the register in the driver is not initialized, if the number of driver ICs for the output line L is k, then 1
To L / k numbers are selected unspecified. On the other hand, the frame clock FCKS7 supplied from the system side outputs'H 'at a rate of 1 / L, and tries to achieve 1 / L duty in a steady state. That is, the line clock LCKS
Immediately after 6 is applied, if V _adj S5 is applied to the LCD, a maximum of L / k commons are selected as a driver and an inrush current flows into the driver, which leads to latch-up. FCK
Based on the relationship with S7, the start of V _adj is L × T _LCK (T _LCK
Is longer than the time immediately after the reset is released) and the voltage is released, the common driver DU becomes 0 to 1
The LCD can be improved by selecting individual ones, the latch-up phenomenon does not occur, and it works the same as the DC protection circuit.
DC protection for the cell. In this embodiment, the time constant due to the resistance Rd and the capacitor Cd of the delay circuit DC is set to T
Set according to the condition of d. In this configuration, the transistor Q
The resistance Rd and the capacitor C are set so that the time required for the potential of the point TP to reach the voltage for starting 5 exceeds Td.
Determine d. The diode Dd is used to release the electric charge stored in the capacitor Cd after the power supply is turned off and always stabilize the state when the power supply is on. As shown by the voltage waveform S4 at the point TP, the voltage rises gently (V = 5 {1
Since the voltage waveform is a function of −exp (−t / CR)}, the current flowing into the base of the transistor Q5 is gentle, and the rising edge of the waveform S5 of V _adj is also gentle.
The current of V _EE that flows into the LCD flows at the time of startup in order to store charges in the liquid crystal material between the electrodes of each cell of the LCD. If V _adj is gentle, the potential difference between the cell electrodes in the LCD also gradually increases, so that no rush current flows. Therefore, it is possible to prevent the latch up of the driver IC.

FIG. 5 shows an example of an implementation circuit using a soft control signal obtained by a program of the information processing device instead of the delay from the reset signal. The operation of this circuit is such that the polarity of the S8LCDDSP shown in FIG. 4 is effectively "L", and the polarity of the S8LCDDSP is "L".
The timing of _{turning on} is achieved by taking at least L × T _LCK ( _TLCK is the time immediately after reset release)
U executes the program of the memory M, and sets the LCD DSP to "L" when the above-mentioned time elapses with the timer TM.

Another example shown in FIG. 6 is GN rather than a display power supply supplied to an LCD smoothed and produced from an AC power supply.
In this system, a DC voltage having a large potential difference from D is dropped by a three-terminal regulator or the like to be stabilized.

FIG. 7 shows an example of the implementation circuit in the power supply configuration of FIG. 6, and FIG. 8 shows the timing in this embodiment circuit. In this example, the reset release is at the'H 'level. The resistor R4, the resistor R3, and the transistor Q1 are circuits that invert the reset circuit, and are unnecessary when the reset release is “L”. The delay is composed of a resistor Rd and a capacitor Cd,
This is achieved by delaying the time until the potential level of 73 becomes'L '. This delay time is determined by the time constants of Rd and Cd, and the time after reset release until the voltage for turning on the transistor Q2 becomes 73 is L × T.
_It should be bigger than _LCK . The transistor Q2 switches the transistor Q3.
Is saturated and the voltage obtained from the dividing resistor VR becomes V _adj and is output. V _adj has transistor Q3 off
During this period, the voltage is released, the direct current application to the LCD cell is protected, and the transistor Q3 is turned on by L × T.
_Since it is delayed by more than _LCK , it can prevent the latch up of the driver IC.

FIG. 9 shows an example of an implementation circuit using a soft control signal obtained by a program of the information processing device instead of the delay from the reset signal. The operation of this circuit is that the polarity of the LCD DSP shown in FIG. 8 is effectively operated with the polarity "L", and the timing for setting the polarity of the LCD DSP to "L" is L × T _LCK (T _LCK is the time immediately after reset release). ) Achieve by taking the above.

Since V _EE and V _adj are applied with the timing of latching up the driver removed, it is possible to protect the direct current application, prevent the latch up of the driver, and reduce the inrush current at startup because the potential is gentle. it can.

The information processing equipment capable of operating a battery shown in FIG. 2 is based on a single voltage (system power supply) obtained from the battery, and the logic control voltage V _CC , the liquid crystal power supply V _EE, etc. It is created by the DC converters DC1 and DC2, and is used as a control block for the logic unit LU and the liquid crystal unit LCDU, respectively, and the printer control unit PU and other control unit E
Another voltage is supplied to U from the DC-DC converters DC3 and DC4. The structure of the power supply unit is the same even if the battery and the AC adapter can be used mutually.

The signal relationship at the time of turning on the power supply of the information processing apparatus is such that when the logic control voltage (generally +5 V) rises, the reset signal for determining the initial operation of the logic unit LU is After the logic control signal is supplied to the unit LU and rises, the reset signal is released after a predetermined time, and the logic unit LU operates. The predetermined time is determined from the stabilization time of the clock oscillator used in the logic unit LU and the number of clocks required to determine the internal processing unit after the clock is stabilized. In this reset period, the segment clock (SCK), the line clock (LCK), and the frame clock (FCK) as signals for controlling the liquid crystal display (LCD) of the liquid crystal unit LCDU may not be issued. At this time, if +5 V (V _DD ) is supplied to the LCD side at the same timing as the logic control voltage, an AC signal cannot be derived in the LCD, and a DC voltage application phenomenon occurs in the LCD cell. LC
Since it is related to the life of D, the liquid crystal unit LCDU having the DC protection circuit DPC as shown in FIG. 3 is used in the liquid crystal unit LCDC. In the figure, GDU is an AC signal generating unit / dividing unit. DDC is a direct current application protection unit. DU
Is an LCD voltage generator. The LCD is a display body.

FIG. 10 shows a configuration in which a dedicated control voltage (V _adj ) is used to adjust the contrast of the LCD.
_{The adj} is used for the variable resistor (V
_This is an advantageous configuration for changing the value of _R ), and can be implemented by inserting V _R between the display power source (V _EE ) of the LCD and GND or V _DD . In the operation of FIG. 3, while the signal is not supplied to the LCD, the voltage V _REF applied to the display body LCD is changed by opening V _REF from V _adj which determines the voltage applied to the display body LCD when the AC signal is not generated. ₁
~V ₅ is almost the same potential, and has a principle of operation can protect the direct current application to the display element LCD.

The V _EE power supply circuit for the LCD of the information processing apparatus using the display LCD according to this configuration is started by the display LC.
It only has to be delayed from V _{CC of} D.

FIG. 10 shows in detail a power supply circuit for LCD display which has a voltage for contrast adjustment of the DC-DC converter 2 shown in FIG. 2 and also protects DC application. This circuit is a DC-DC converter, which is generally called the RCC system, and it switches the current from the system power supply depending on the load state and the Z state of the time constant of the transformer T and the resistors R and C. Then, a predetermined voltage is supplied, and its switching action is constituted by transistors Q1 and Q2, a resistor R1, a capacitor C, and a transformer T. It is the current supplied by V _CC that essentially drives the transistor Q2 switch, which is determined by resistor R2. The load characteristics of the display power supply are
It is determined by the base current of the transistor Q2. Further, input a reset signal to the input of the resistor R2,
The output from the resistor Rd, the diode Dd, and the capacitor Cd that form the circuit DC that delays this is used.

D1 is a diode. C2 is a capacitor. D2 is a diode. ZD is a Zener diode, which returns to the transistor Q2. VR is a variable resistor, and the voltage generated by the resistance division is displayed on the display body LC as V _adj via the transistor Q3 as a switch.
Supplied to D. This switching operation of Q3 is performed by resistors R3 and R that divide the voltage between the voltage generated by VR and the reset voltage.
4 is determined by the bias potential between the base and emitter of Q3. When the bias potential between the base-emitter of Q3 is equal to or lower than the saturation voltage of Q3 (about 0.7V), Q3 is in the switch-off state and V _adj is open-circuited. When the bias voltage is equal to or higher than the saturation voltage, Q3 is in the switch-on state. V _adj is VR
It becomes the voltage created by the resistance division. In this example of the circuit, the voltage applied to R4 is used as the reset signal, but V _CC and GND may be used as long as the bias potential between the base and emitter of Q3 can be set to a predetermined condition as described above.

A power supply sequence of this circuit and the whole is shown in FIG.
The timing chart of FIG. The present embodiment relates to a system in which the reset signal is'H 'level to start the system.

After the system power supply is turned on S1, the voltage S2 of V _CC is determined with a delay of the delay time determined by the configuration of the V _CC power supply. The reset signal S3 differs depending on the circuit used, but when a voltage detection type reset IC is used,
The state is indefinite until V _CC reaches 0.7 V, and 0.
It becomes'L 'level when it is more than 7V. Further reset I
The'L 'level period of the output of C is determined by the external capacitor capacity. After a lapse of time determined by the above conditions, the reset signal C3 becomes the “H” level, and the system is activated. This activation causes the LCD signal to be generated and supplied to the LCD when the logic state is determined such that the LCD signal is generated. The cycle of the line clock LCKS6 and the frame clock FCKS7 immediately after the reset is released is in the initial state in the case of the logic that makes the frequency division variable, and the predetermined cycle is the predetermined frequency division value in the register that determines the frequency division. After writing. The determination of the delay time in the present invention is calculated from the cycle of the line clock LCK immediately after reset release. 1 / in LCD
At the L duty, the common side is selected one for the common side output line L in the steady state. However, immediately after applying V _CC ,
Since the register in the driver is not initialized, if the number of driver ICs for the output line L is k, then 1
To L / k numbers are selected unspecified. On the other hand, the frame clock FCKS7 supplied from the system side outputs'H 'at a rate of 1 / L, and tries to achieve 1 / L duty in a steady state. That is, the line clock LCKS
Immediately after 6 is applied, if V _EE S5 is applied to the LCD, a maximum of L / k commons are selected as a driver and an inrush current flows into the driver, leading to latch-up. FCKS
From the relationship with 7, when delaying the start of V _EE by more than L × T _LCK (T _LCK is the time immediately after reset release), the common driver DU can be selected from 0 to 1 and a latch-up phenomenon occurs. Disappear. In this embodiment, the time constant of the resistor Rd and the capacitor Cd of the delay circuit DC is set in accordance with the condition of Td. In this configuration, the resistor Rd and the capacitor Cd are determined so that the time required for the potential at the point TP to reach the voltage that activates the transistor Q2 exceeds Td. The diode Dd is
It is used to release the electric charge stored in the capacitor Cd and always stabilize the state when the power is on. Point TP
As shown by the voltage waveform S4 of, the voltage rises gently (V =
5 {1-exp (-t / CR)} function), the current flowing into the base of the transistor Q2 becomes gentle, and the rising edge of the waveform S5 of V _EE becomes gentle. The current of the waveform S5 of V _EE that flows into the LCD flows at the time of startup in order to accumulate charges in the liquid crystal material between the electrodes of the LCD cells. If the waveform S5 of V _EE is gentle, V _adj is equal to the transistor Q3, the resistor R3, and the resistor R4.
As a result, the voltage is released while the transistor Q3 is off to protect the direct current applied to the LCD cell, and when the transistor Q3 is turned on, it follows V _EE. Therefore, the waveform S8 of V _adj also becomes gentle, and Since the potential difference between the cell electrodes also gradually increases, no rush current flows. Therefore, it is possible to prevent the latch up of the driver IC.

Another example shown in FIG. 6 is GN rather than a display power supply supplied to an LCD smoothed and produced from an AC power supply.
In this system, a DC voltage having a large potential difference from D is dropped by a three-terminal regulator or the like to be stabilized.

FIG. 12 shows an example of the implementation circuit in the power supply configuration of FIG. 6, and FIG. 13 shows the timing in this embodiment circuit. In this example, the reset release is at the'H 'level.
The resistor R4, the resistor R3, and the transistor Q1 are circuits that invert the reset circuit, and are unnecessary when the reset release is “L”. The delay is composed of a resistor Rd and a capacitor Cd, and is achieved by delaying the time until the potential level of 73 is set to “L”. This delay time is determined by the time constants of Rd and Cd, and the time after reset release until the voltage for turning on the transistor Q2 becomes 73 is L ×.
It should be larger than T _LCK . The transistor Q2 is for switching the transistor Q3.
3 is saturated, and the voltage of the negative power supply is supplied to the regulator RG as it is. Until the transistor Q3 is saturated, the collector voltage of the transistor Q3 gradually goes to the voltage of the negative power supply. In the regulator RG, a potential difference from GND necessary for stable output of V _EE appears in the collector of the transistor Q3. The output goes out gently until it goes out. When the potential difference between the collector of the transistor Q3 and GND exceeds the required potential difference with GND, the regulator RG
Outputs V _EE . Since V _adj is made up of V _EE and GND, if the waveform of V _EE is gentle, V _adj will have a voltage open while transistor Q4 is off due to transistor Q3, resistor R7, and resistor R8, and the direct current of the LCD cell When the transistor Q4 is turned on and protects the applied voltage, and follows V _EE , the waveform of V _adj also becomes gentle,
Since the potential difference between the cell electrodes in the LCD also gradually increases, no inrush current flows. Therefore, it is possible to prevent the latch up of the driver IC.

Since V _EE and V _adj are applied with the timing for latching up the driver off, it is possible to protect the direct current application, prevent the driver from latching up, and reduce the inrush current at startup because the potential is gentle. it can.

The information processing equipment capable of battery operation shown in FIG. 14 uses the single voltage (system power supply) obtained from the battery to set the logic control voltage V _CC to DC-D.
The liquid crystal voltage V _EE is created by the DC-DC converter DC2 in the logic unit LU created by the C converter DC1, and the liquid crystal backlight voltage is created by the inverter from the voltage created by the DC-DC converter DC3. , DC-DC for the control block of the liquid crystal unit LCDU, the printer control unit PU, and the other control unit EU.
Other voltages are supplied from the converters DC4 and DCn.
The structure of the power supply unit is the same even if the battery and the AC adapter can be used mutually.

The signal relationship at the time of turning on the power supply of the information processing apparatus is such that when the logic control voltage (generally +5 V) is rising, the reset signal for determining the initial operation of the logic unit LU is After the logic control signal is supplied to the unit LU and rises, the reset signal is released after a predetermined time, and the logic unit LU operates. The predetermined time is determined from the stabilization time of the clock oscillator used in the logic unit LU and the number of clocks required to determine the internal processing unit after the clock is stabilized. During this reset period, the segment clock (SCK), line clock (LCK), and frame clock (FCK) as signals for controlling the liquid crystal display (LCD) of the liquid crystal unit LCDU may not be emitted. At this time, if +5 V (V _DD ) is supplied to the LCD side at the same timing as the logic control voltage, an AC signal cannot be derived in the LCD, and a DC voltage application phenomenon occurs in the LCD cell. LC
Since it is related to the life of D, the liquid crystal unit LCDU having the DC protection circuit DPC as shown in FIG. 3 is used in the liquid crystal unit LCDC. In the figure, GDU is an AC signal generating unit / dividing unit. DDC is a direct current application protection unit. DU
Is an LCD voltage generator. The LCD is a display body.

FIG. 15 shows a configuration in which a dedicated control voltage (V _adj ) is used to adjust the contrast of the LCD.
_{The adj} is used for the variable resistor (V
_This is an advantageous configuration for changing the value of _R ), and can be implemented by inserting V _R between the display power source (V _EE ) of the LCD and GND or V _DD . In the operation of FIG. 3, while the signal is not supplied to the LCD, the voltage V _REF applied to the display body LCD is changed by opening V _REF from V _adj which determines the voltage applied to the display body LCD when the AC signal is not generated. ₁
~V ₅ is almost the same potential, and has a principle of operation can protect the direct current application to the display element LCD.

The V _EE power supply circuit for the LCD of the information processing apparatus using the display LCD according to this configuration is started by the display LC.
It only has to be delayed from V _{CC of} D.

The signal relationship in the present invention will be described with reference to the timing chart of FIG. The present embodiment relates to a system in which the reset signal is'H 'level to start the system.

After the system power supply is turned on S1, the voltage S2 of V _CC is determined with a delay of the delay time determined by the configuration of the V _CC power supply. The reset signal S3 differs depending on the circuit used, but when a voltage detection type reset IC is used,
The state is indefinite until V _CC reaches 0.7 V, and 0.
It becomes'L 'level when it is more than 7V. Further reset I
The'L 'level period of the output of C is determined by the external capacitor capacity. After a lapse of time determined by the above conditions, the reset signal C3 becomes the “H” level, and the system is activated. This activation causes the LCD signal to be generated and supplied to the LCD when the logic state is determined such that the LCD signal is generated. The cycle of the line clock LCKS6 and the frame clock FCKS7 immediately after the reset is released is in the initial state in the case of the logic that makes the frequency division variable, and the predetermined cycle is the predetermined frequency division value in the register that determines the frequency division. After writing. The determination of the delay time in the present invention is calculated from the cycle of the line clock LCK immediately after reset release. 1 / in LCD
At the L duty, the common side is selected one for the common side output line L in the steady state. However, immediately after applying V _CC ,
Since the register in the driver is not initialized, if the number of driver ICs for the output line L is k, then 1
To L / k numbers are selected unspecified. On the other hand, the frame clock FCKS7 supplied from the system side outputs'H 'at a rate of 1 / L, and tries to achieve 1 / L duty in a steady state. That is, the line clock LCKS
Immediately after 6 is applied, if V _EE S5 is applied to the LCD, a maximum of L / k commons are selected as a driver, and the display data is undefined, so that an unnecessary horizontal line occurs. This time,
When the backlight is turned on, this horizontal line becomes clear and the display quality appears to deteriorate immediately after the power is turned on. Also,
When the signal used for the driver in the LCD is indefinite, L
When the high voltage used for the backlight used for the CD is applied, the initial data of the driver easily becomes'H ', and the number of the horizontal lines further increases.

In the present invention, the timing of the high voltage applied to the S4 backlight is defined as the line synchronization time immediately after the start is T _LCK , and the time from the start to the start of the power supply for the backlight unit of the liquid crystal display is T _d . When doing, T _d > L
By setting × T _LCK , it is possible to prevent deterioration of the display product immediately after the power is turned on.

The diagram shown in FIG. 17 shows a general circuit configuration of an inverter. AC is input by switching the input DC voltage between Q3 and Q4 transistors alternately.
It is configured such that it is converted to a voltage and boosted to a high voltage by T1.

FIG. 1 shows a circuit diagram of the first embodiment of the present invention. The present embodiment is achieved by delaying the DC voltage input to the inverter so that the condition of T _d > L × T _LCK is satisfied, and the delay circuit D of FIG.
The time constant of the resistance Rd of C and the capacitor Cd is set according to the condition of _Td . In this configuration, the resistance Rd and the capacitor Cd are set so that the time required for the potential at the point TP to reach the voltage that activates the transistor Q2 exceeds T _d.
To decide. The diode Dd is used to release the electric charge stored in the capacitor Cd after the power supply is turned off and always stabilize the state when the power supply is on.

FIG. 18 shows the above timing.

FIG. 19 shows a circuit diagram of another embodiment of the present invention. In this embodiment, in the inverter shown in FIG. 17, the inverter start control signal is T _d > L × T
It is supplied so as to meet the _LCK conditions, and (a)
Is a configuration in the case of supplying the start control signal with a delay from the reset signal, as in the embodiment.
(B) is a case where the control signal is directly supplied from the logic control unit as a signal, and at this time, the application timing of the signal can be soft-controlled as a program in the information processing apparatus.

[0043]

As described above, the negative signal start of the LCD is delayed by more than L × T _LCK from the reset signal of the information processing device, and V _adj changes from the voltage release to the post-start voltage of the negative power source. Since the supply starts, the inrush current at the time of applying the negative power supply can be further reduced. (1) The latch-up phenomenon of the LCD driver can be prevented. (2) Since the latch-up is prevented, the quality of the LCD is not deteriorated. (3) Since the inrush current is reduced, the negative power supply circuit is not damaged. (4) DC application can be protected.

As described above, in order to delay the start of the backlight of the LCD by more than L × T _LCK from the reset signal of the information processing device and to reduce the number of'H 'level of the driver in the LCD. , The visibility of the horizontal line is reduced after the power is turned on, and the display quality is not deteriorated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment.

FIG. 2 is a diagram showing an entire power supply.

FIG. 3 is a circuit diagram of a liquid crystal unit LCD.

FIG. 4 is a timing chart.

FIG. 5 is a diagram showing an example of an implementation circuit diagram (second embodiment) by a soft control signal in the first embodiment.

FIG. 6 is a diagram showing a third embodiment according to the present invention.

7 is a detailed view of LCDU2 shown in FIG.

FIG. 8 is a timing chart.

FIG. 9 is a diagram showing an example of an implementation circuit diagram (fourth embodiment) based on a soft control signal in the third embodiment.

FIG. 10 is a circuit diagram showing an example.

FIG. 11 is a timing chart.

12 is a detailed view of LCDU2 shown in FIG.

FIG. 13 is a timing chart.

FIG. 14 is a circuit diagram showing an example.

FIG. 15 is a diagram showing an entire power supply.

FIG. 16 is a circuit diagram of a liquid crystal power supply.

FIG. 17 is a timing chart.

FIG. 18 is a general circuit diagram of an inverter.

FIG. 19 is a timing chart in the first embodiment.

FIG. 20 is a diagram showing another embodiment.

FIG. 21 is a diagram showing a conventional example.

[Explanation of symbols]

DC delay circuit V _adj control voltage

Claims (3)

[Claims] 1. A 1 × m × n dot liquid crystal display
A liquid crystal display device driven with L (n ≧ L ≧ n / 2) duty and having a contrast adjustment voltage separately from a display power supply, wherein the liquid crystal display controller supplies the display power supply and voltage for the liquid crystal display. In the above, when the line synchronization time immediately after the start is T _LCK , and the time from the start to the start of the contrast adjustment power supply of the liquid crystal display is T _d , the liquid crystal is delayed such that T _d > L × T _LCK. The display control device, wherein the liquid crystal display control device is supplied to the liquid crystal display device in an open state until a voltage for contrast adjustment is started. 2. A 1 × m × n dot liquid crystal display
A liquid crystal display device driven with L (n ≧ L ≧ n / 2) duty and having a contrast adjustment voltage separately from a display power supply, wherein the liquid crystal display controller supplies the display power supply and voltage for the liquid crystal display. _Where T _LCK is the line synchronization time immediately after the start and T _d is the time from the start to the start of the display power supply of the liquid crystal display, and T _d > L × T _LCK and the rise time of the display power supply is T _d In the liquid crystal display control device that delays as described above, the contrast adjustment voltage is supplied to the liquid crystal display device in an open state until the display voltage starts to start. The liquid crystal display control device. 3. A liquid crystal display of m × n dots
In a liquid crystal display device integrally configured with a backlight unit which is driven with an L (n ≧ L ≧ n / 2) duty and supplies display illumination from behind, a display power supply, voltage, and backlight for the liquid crystal display. in the liquid crystal display controller for supplying power for the light section, when T _LCK a line synchronization time immediately after starting, the time from the start to the backlight unit for the power supply starting initiation of the liquid crystal display and T _d, T _d> Liquid crystal display control device characterized by L × T _LCK .