JP2004334093A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably prevent such a phenomenon that a display devoid of meaning which is not intended (waste display) appears at an instant when a power source is supplied. <P>SOLUTION: The display device is provided with a drive part, a display part and a control part. The drive part has a power source terminal for memory, a memory for storing an information signal in the state that the power feeding of the power source terminal is held and a power source terminal for outputting display signal and, by using an electric power received via the power source terminal for outputting display signal, outputs the information signal stored in the memory as a display signal. The display part receives the display signal and displays the contents according to the display signal. After starting the power feeding to the power source terminal for memory, the control part writes the information signal of performing a desired display on the display part into the memory and, thereafter, the power is fed to the power source terminal for outputting display signal. That is, before the drive part outputs the display signal, the information signal of performing a desired display on the display part is written into the memory. As a result, such a phenomenon that a waste display appears at an instant when a power source is supplied is reliably prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technique for preventing a phenomenon in which an unintended and meaningless display appears momentarily when power is turned on in a display device.
[0002]
[Prior art]
Display devices are classified into an LED system, a liquid crystal system, an electroluminescence system, a plasma display system, a CRT (Cathode Ray Tube) system, and the like.
In general, a display device has a display monitor and a driver IC for driving the display monitor. Usually, the driver IC is designed so that the display panel is set to the non-display state immediately after the power is turned on. However, when the power supply is turned on again immediately after the power supply of the driver IC is turned off or when the rise of the power supply voltage is not steep immediately after the power supply is turned on, an unintended unnecessary display (hereinafter referred to as dust display) may appear. This is because the RAM inside the driver IC is not cleared or the RAM has an arbitrary value. The dust display continues until display information is received from the outside or a command to turn off all displays is input to the driver IC.
[0003]
Patent Document 1 is known as a conventional technique for preventing this dust display. In Patent Literature 1, the display device is set to be turned on in conjunction with turning on the power of peripheral devices such as a host device. In addition, a technique for preventing dust display caused by a difference in rise time of each device when the power is turned on is disclosed.
[Patent Document 1]
JP-A-2001-109450 (Section 5-8, FIGS. 1 to 6)
[0004]
[Problems to be solved by the invention]
In Patent Literature 1, an operation is performed in which received data is sequentially interpreted when a specific condition is satisfied, or when a customer display is not selected, the VRAM area is kept clear. Therefore, since the state immediately after the power is turned on and before the VRAM area is cleared is not considered, dust display may appear before the VRAM area is cleared.
[0005]
Usually, the period during which the dust display appears is momentary (less than one second). However, even if the dust display appears even for a moment, there is a possibility that the user may feel uncomfortable or worry about malfunction. Therefore, it has been desired to reliably prevent dust display.
An object of the present invention is to provide a technique for reliably preventing a phenomenon in which dust display appears momentarily when power is turned on.
[0006]
[Means for Solving the Problems]
According to a first aspect of the invention, a display device includes a driving unit, a display unit, and a control unit. The drive unit has a memory power supply terminal, a memory that stores an information signal when the memory power supply terminal is powered, and a display signal output power supply terminal, and receives power received via the display signal output power supply terminal. To output the information signal stored in the memory as a display signal. The display unit receives the display signal and displays the content according to the display signal. After starting the power supply to the power supply terminal for the memory, the control unit writes an information signal for causing the display unit to perform a desired display in the memory, and then supplies the power to the power supply terminal for the display signal output.
[0007]
According to a second aspect of the present invention, in the first aspect, the control section includes a power supply circuit capable of switching whether to supply power to the display signal output power supply terminal, and supplies power to the memory power supply terminal. At the start, power supply to the power supply circuit is stopped, an information signal is written to the memory, and then the power supply circuit is supplied with power. "
[0008]
According to a third aspect of the invention, there is provided a display device having the following features. First, the control unit includes a microcontroller having an output port, and a voltage stabilizing circuit for setting the output voltage of the output port to a predetermined voltage and supplying power to the display signal output power supply terminal. Second, the microcontroller does not output a voltage from the output port when power supply to the memory power supply terminal is started, but writes an information signal to the memory and then outputs a voltage from the output port.
[0009]
According to a fourth aspect of the present invention, in the invention according to the first aspect, "the input side is connected to the memory power supply terminal and the output side is connected to the display signal output power supply terminal. The control unit is provided with a delay circuit that delays by a predetermined time longer than the writing time of the information signal to the memory and outputs from the output side ”.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Configuration of this embodiment>
FIG. 1 is a block diagram illustrating a circuit configuration of the display device of the present embodiment. In the present embodiment, as an example, an example in which the inventions of claims 1 and 3 are applied to a liquid crystal display device of an electronic camera will be described.
[0011]
As shown in the figure, the liquid crystal display device 10A includes an operation unit 14, a power switch 18, a replaceable battery 22, a regulator 26, diodes 30, 34, a DC-DC converter 38, a reset IC 42, , A microcontroller 46 (hereinafter abbreviated as a microcomputer), a regulator 50, an LCD driver 54, and a liquid crystal panel 58. Note that GND in the figure is a ground line (voltage 0 V). A connection node between the diodes 30 and 34 and the reset IC 42 is referred to as a node A.
[0012]
The operation unit 14 has operation switches (not shown) for the user to change settings of the electronic camera.
The regulator 26 (three-terminal regulator) sets the voltage received from the battery 22 to 4.5 V and outputs the same.
The DC-DC converter 38 has a CTL terminal for controlling the timing of outputting a voltage. When a high-level voltage is received at the CTL terminal, the DC-DC converter 38 outputs a voltage received from the battery 22 of 5.0 V.
[0013]
The microcomputer 46 performs system control of the entire electronic camera, such as automatic focus adjustment, automatic exposure control, and display of shooting conditions. The microcomputer 46 has GND, SO, SCK, VCC, RESET, PORT01, PORT02, PORT03, PORT03, PORT04, and PORT05 as terminals.
When both the regulator 26 and the DC-DC converter 38 output voltages, the VCC terminal (power supply terminal) receives the higher one of them. That is, when both output voltages, the VCC terminal receives a voltage obtained by subtracting the forward voltage drop (about 0.4 V) of the diode 34 from the output voltage of the DC-DC converter 38.
PORT01 sets the operation mode of the microcomputer 46. Specifically, when the power switch 18 is turned off (cut off), the PORT 01 receives a high-level voltage from a power line (not shown), and the microcomputer 46 switches to the low power consumption mode. Thereby, consumption of the battery 22 is suppressed. When the power switch 18 is turned on (conducting), the PORT01 receives a low-level voltage, and the microcomputer 46 switches to the normal operation mode. Note that, even if the power switch 18 is turned on, if the state in which the operation unit 14 is not operated continues for a predetermined time (half-press timer time), the microcomputer 46 switches to the low power consumption mode.
[0014]
Further, the microcomputer 46 transmits a control command and display data to the LCD driver 54. Specifically, the microcomputer 46 declares the start of communication to the LCD driver 54 by setting the output voltage of the PORT 04 to a low level. After the PORT 04 is set to the low level, the microcomputer 46 inputs a command and display data to the LCD driver 54 from the SO terminal in accordance with the clock signal output from the SCK terminal.
[0015]
Further, the microcomputer 46 controls, based on the output voltage of the PORT 03 (input voltage to the regulator 50), whether or not to supply power to a VLCD terminal of the LCD driver 54 described later. Specifically, when no voltage is output from the PORT 03 (the output is at a low level), the output voltage of the regulator 50, that is, the input voltage of the VLCD terminal becomes 0V. When the output voltage of the PORT03 is at a high level, the output voltage of the regulator 50 becomes 4.0V.
[0016]
The reset IC 42 inputs a low-level voltage to the RESET terminal of the microcomputer 46 when the voltage of the node A decreases to a predetermined value. As a result, the microcomputer 46 shifts to the reset state before the supply voltage to the VCC terminal becomes equal to or lower than the operation guarantee voltage of the microcomputer 46. Therefore, malfunction of the microcomputer 46 is prevented. Further, after the battery 22 is loaded, the voltage of the node A rises to the operation guarantee voltage of the microcomputer 46, and after the oscillation stabilization time by the oscillator (not shown) of the microcomputer 46 elapses, the reset IC 42 outputs the high-level voltage to the RESET terminal. Enter As a result, the microcomputer 46 switches from the non-operation state to the operation state.
[0017]
FIG. 2 is a block diagram showing the inside of the LCD driver 54. The LCD driver 54 includes a serial I / O interface 62 shown in FIG. 2 in addition to the SEG terminal, COM terminal, VCC terminal, VLCD terminal, CS terminal, SCK terminal, SI terminal, and GND terminal shown in FIG. It has a RAM 66 and a driver unit 70.
The display RAM 66 is supplied with a voltage from the VCC terminal, and stores display data received from the microcomputer 46 via the I / O interface 62. The display RAM 66 is in a state where data can be written only when a low level voltage is applied to the CS terminal. When no power is supplied from the VCC terminal, the display RAM 66 does not operate.
[0018]
The driver unit 70 is supplied with a voltage from the VLCD terminal and reads the display data written in the display RAM 66. The driver unit 70 generates a signal voltage for displaying the read display data on the liquid crystal panel 58 by a voltage supplied from a VLCD terminal. The driver unit 70 inputs the generated signal voltage to the liquid crystal panel 58 from the COM terminal and the SEG terminal. Note that the amplitudes of the output voltages of the COM terminal and the SEG terminal are defined by the input voltage of the VLCD terminal. When there is no power supply from the VLCD terminal, the driver unit 70 does not operate.
Since the VCC terminal of the microcomputer 46 and the VCC terminal of the LCD driver 54 are commonly supplied with power, the microcomputer 46 starts driving in synchronization with the supply of power to the VCC terminal of the LCD driver 54.
[0019]
<Description of the operation of the present embodiment>
FIG. 3 shows voltage waveforms at various parts of the liquid crystal display device 10A immediately after the battery 22 is loaded in an electronic camera body (not shown). FIG. 4 is a flowchart showing the operation from the loading of the battery 22 to the transition to the low power consumption mode. Hereinafter, the operation of the liquid crystal display device 10A of the present embodiment will be described according to the step numbers shown in FIG. 4 using the times t1 to t6 shown in FIG.
[0020]
[Step S1]
First, at time t1, the battery 22 is loaded into the electronic camera body. The output voltage of the battery 22 gradually rises due to the capacity connected to the battery 22 and the like. Further, as the battery 22 is turned on, the output voltage of the regulator 26 rises, and the voltage of the node A rises.
[0021]
Next, at time t2, the voltage of the node A reaches the reset voltage of the reset IC. This reset voltage is higher than the operation guarantee voltage of the microcomputer 46, and at this time, the oscillation of the oscillator of the microcomputer 46 is already stable. Therefore, at time t2, the reset IC 42 inputs a high-level voltage to the RESET terminal, and switches the microcomputer 46 to the operating state. Thereby, the microcomputer 46 clears the internal memory, initializes the resources to be used, and then starts the operation as the normal operation mode.
[0022]
[Step S2]
Next, at time t3, the output voltage of the battery 22 rises until the output voltage of the regulator 26 becomes 4.5V. Therefore, the voltage of the node A is stabilized at the output voltage of the regulator 26.
Next, at time t4, the microcomputer 46 switches the output voltage of the PORT02 to a high level, and inputs a high-level voltage to the CTL terminal of the DC-DC converter 38. As a result, the output voltage of the DC-DC converter 38 rises. The output voltage of the DC-DC converter 38 is used to drive each unit of the electronic camera via a wiring (not shown).
[0023]
Next, at time t5, the output voltage of the DC-DC converter 38 becomes higher than the output voltage of the regulator 26. Therefore, the voltage of the node A starts to increase again due to the output voltage of the DC-DC converter 38. Therefore, the input voltage to the VCC terminal of the microcomputer 46 is switched from via the regulator 26 to via the DC-DC converter 38. At this timing, the input voltage to the VLCD terminal of the LCD driver 54 is 0 V, so that nothing is displayed on the liquid crystal panel 58.
[0024]
[Step S3]
Thereafter, the output of the DC-DC converter 38 completely rises, and the voltage of the voltage node A stabilizes at 5.0V. Thereafter, the microcomputer 46 sends a reset command to the LCD driver 54 to instruct clearing of the display RAM 66. As a result, the display RAM 66 is cleared (this is equivalent to writing display data corresponding to no display into the display RAM 66).
In place of the reset command, display data for performing a desired display or display data corresponding to the beginning of information to be displayed may be input to the display RAM 66 via the serial I / O interface 62. Good.
[0025]
[Step S4]
Next, at time t6, the microcomputer 46 switches the output voltage of the PORT03 to a high level (inputs a high-level voltage to the regulator 50). As a result, the power supply to the VLCD terminal of the LCD driver 54 is started, and the display on the liquid crystal panel 58 is started according to the data stored in the display RAM 66. At this time, since the display RAM 66 is cleared by transmitting the reset command in step S3, nothing is displayed.
In step S3, when display data for displaying a desired display or display data corresponding to the first information to be displayed is input to the display RAM 66 instead of the reset command, the content of the input display data is displayed on the liquid crystal display. Displayed on panel 58.
[0026]
[Step S5]
The microcomputer 46 detects the state of the power switch 18 in order to determine the information to be displayed on the liquid crystal panel 58. If the power switch 18 is on (conducting), the process proceeds to step S6, and if it is off (open), the process proceeds to step S14.
[0027]
[Step S6]
The microcomputer 46 decodes predetermined display data to be displayed when the power switch 18 is on, in a format to be transmitted to the LCD driver 54.
[0028]
[Step S7]
The microcomputer 46 inputs the display data decoded in step S6 to the display RAM 66 via the serial I / O interface 62. By transmitting the display data, the LCD driver 54 causes the liquid crystal panel 58 to start a desired display.
[0029]
[Step S8]
The microcomputer 46 determines the state of the power switch 18. If the power switch 18 is on, the process proceeds to step S9; if it is off, the process proceeds to step S14.
[0030]
[Step S9]
The microcomputer 46 determines the state of a half-press timer (not shown). If the half-pressing timer is off, the process proceeds to step S10; otherwise, the process returns to step S8. The determination loop of steps S8 and S9 is performed as needed.
Further, when the setting of the microcomputer 46 changes during the determination loop of steps S8 and S9 due to the operation of the operation unit 14 or the like, the microcomputer 46 updates the display data transmitted to the LCD driver 54.
[0031]
[Step S10]
The microcomputer 46 decodes predetermined display data to be displayed when the half-press timer is off in a format to be transmitted to the LCD driver 54.
[0032]
[Step S11]
The microcomputer 46 inputs the display data decoded in step S10 to the display RAM 66 via the serial I / O interface 62. By transmitting the display data, the LCD driver 54 causes the liquid crystal panel 58 to perform a desired display.
[0033]
[Step S12]
The microcomputer 46 switches the output voltage of the PORT02 to a low level, and turns off the DC-DC converter 38. Thus, the input voltage to the VCC terminal of the microcomputer 46 is switched via the regulator 26.
[0034]
[Step S13]
The microcomputer 46 shifts from the normal operation mode in which photography is possible to the low power consumption mode in which photography is not possible. Thereafter, power is supplied to the VCC terminal of the microcomputer 46 and the VCC terminal of the LCD driver 54 via the regulator 26, so that the display on the liquid crystal panel 58 is maintained. In the low power consumption mode, the microcomputer 46 causes the liquid crystal panel 58 to display minimum information such as the number of recordable images.
[0035]
[Step S14]
The microcomputer 46 decodes predetermined display data to be displayed when the power switch 18 is off in a format to be transmitted to the LCD driver 54.
[0036]
[Step S15]
The microcomputer 46 inputs the display data decoded in step S14 to the display RAM 66 via the serial I / O interface 62. By transmitting the display data, the LCD driver 54 causes the liquid crystal panel 58 to perform a desired display. Thereafter, the process proceeds to step S12, and shifts to the low power consumption mode by the above-described operation.
[0037]
The above is the description of the operation of each step.
If the operation unit 14 is operated after shifting to the low power consumption mode in step S13, the microcomputer 46 shifts to the normal operation mode again and returns to step S5. Therefore, the processing performed only when the battery 22 is loaded is the processing of steps S1 to S4.
Further, when the mode shifts to the normal operation mode again after shifting to the low power consumption mode, the liquid crystal panel 58 is in a state of maintaining the display as described in step S13. That is, since predetermined display data is written in the display RAM 66, no dust display appears at this time.
[0038]
<Effect of this embodiment>
In the present embodiment, a reset command for clearing the display RAM 66 is transmitted to the LCD driver 54 before supplying power to the VLCD terminal which is a power supply terminal for the driver unit 70 (step S3). Therefore, when power is supplied to the VLCD terminal, that is, when the driver unit 70 causes the liquid crystal panel 58 to start displaying, the display RAM 66 has already been cleared, and no dust display appears.
[0039]
In other words, the display power supply (VLCD terminal) is not turned on immediately after the display unit power supply (VCC terminal of the LCD driver 54) is turned on and before the display RAM 66 is cleared, and the display RAM 66 is cleared. After that, the display power is turned on, so no dust display appears.
For this reason, when the battery 22 is loaded, it is possible to reliably prevent an unnecessary dust display from appearing momentarily. As a result, it is possible to prevent the user from feeling uncomfortable or worrying about failure.
[0040]
Also, as described above, if the display memory is cleared before power is supplied to the drive unit for inputting the display signal voltage to the liquid crystal panel, dust display can be performed even in an LCD driver that does not have a forced non-display function. It can be reliably prevented.
Further, since the microcomputer 46 can control whether or not to supply power to the VLCD terminal by the output of the PORT 03, the control sequence and the circuit configuration can be simplified.
[0041]
<Supplementary information of this embodiment>
[1] In the present embodiment, an example has been described in which whether the liquid crystal panel 58 is turned on or completely turned off is controlled depending on whether power is supplied to the regulator 50 or not. The present invention is not limited to such an embodiment.
For example, as shown in FIG. 5, instead of the regulator 50, the microcomputer 46 may control the CTL terminal using a regulator 90 having an output control terminal (CTL terminal). In this case, when power supply to the VCC terminal of the LCD driver 54 is started, for example, a low-level voltage is input to the CTL terminal of the regulator 90 to stop power supply to the regulator 90. Then, after transmitting a reset command for clearing the display RAM 66 to the LCD driver 54, a high-level voltage is input to the CTL terminal of the regulator 90 to cause the regulator 90 to start supplying power to the VLCD terminal. This embodiment corresponds to claim 2. In this case, the same effect as in the above-described embodiment can be obtained.
[0042]
Alternatively, as shown in FIG. 6, a delay circuit 94 operating with a delay time D may be used instead of the regulator 50. In this case, after the power supply to the VCC terminal of the LCD driver 54 is started, the delay time D is set so that the same reset command is transmitted to clear the display RAM 66 and then the power supply to the VLCD terminal is started. That is, the delay time D is made sufficiently longer than the time required for clearing the display RAM 66. This embodiment corresponds to claim 4. In this case, the same effect as in the above-described embodiment can be obtained.
[0043]
[2] An example in which the present invention is applied to a liquid crystal display device of an electronic camera has been described. The present invention is not limited to such an embodiment. The technology for preventing dust display of the present invention can be applied to other display devices such as a plasma display system. Further, the present invention can be applied to other devices in which dust display due to battery chatter is a problem.
[0044]
[3] Finally, the correspondence between the claims and the present embodiment will be described. Note that the correspondence shown below is an interpretation for reference, and does not limit the present invention.
The memory power supply terminal described in the claims corresponds to the VCC terminal of the LCD driver 54.
The information signal described in the claims corresponds to display data that the microcomputer 46 inputs to the display RAM 66.
[0045]
The memory described in the claims corresponds to the display RAM 66.
The display signal output power supply terminal described in the claims corresponds to the VLCD terminal of the LCD driver 54.
The display signal described in the claims corresponds to “a signal voltage generated from the display data read by the driver unit 70 and input to the liquid crystal panel 58 (from the COM terminal and the SEG terminal)”.
[0046]
The driving unit described in the claims corresponds to the LCD driver 54.
The display unit described in the claims corresponds to the liquid crystal panel 58.
The “information signal for desired display” described in the claims corresponds to “reset command, display data for desired display, display data corresponding to the beginning of information to be displayed” described in step S3. .
[0047]
The control unit described in the claims corresponds to the microcomputer 46 and the regulator 50.
The power supply circuit described in the claims corresponds to the regulator 90 in FIG.
The microcontroller described in the claims corresponds to the microcomputer 46.
The voltage stabilizing circuit described in the claims corresponds to the regulator 50 in FIG.
The output port described in the claims corresponds to PORT03 of the microcomputer 46.
The “predetermined time longer than the writing time” in the claims corresponds to the delay time D.
[0048]
【The invention's effect】
In the present invention, before supplying power to the display signal output power supply terminal, that is, before the driving unit outputs the display signal, an information signal for causing the display unit to perform a desired display is written in the memory. Therefore, it is possible to reliably prevent the dust display from appearing when the power is turned on.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment.
FIG. 2 is a block diagram showing the inside of the LCD driver of FIG. 1;
FIG. 3 is a timing chart showing voltage waveforms at various parts immediately after loading of a battery.
FIG. 4 is a flowchart for explaining the operation of the liquid crystal display device of the present embodiment.
FIG. 5 is a block diagram showing a configuration of an embodiment using a regulator having an output control terminal instead of the regulator 50;
FIG. 6 is a block diagram showing a configuration of an embodiment using a delay circuit instead of the regulator 50;
[Explanation of symbols]
10A, 10B, 10C Liquid crystal display device 14 Operation switch 18 Power switch 22 Battery 26 Regulator 30, 34 Diode 38 DC-DC converter 42 Reset IC
46 Microcontroller 50 Regulator 54 LCD driver 58 Liquid crystal panel 62 Serial I / O interface 66 Display RAM
70 Driver unit 90 Regulator 94 Delay circuit

Claims (4)

A power supply terminal for memory, a memory for storing an information signal in a state where the power supply terminal for memory is supplied, and a power supply terminal for display signal output, using power received through the power supply terminal for display signal output. A driving unit that outputs the information signal stored in the memory as a display signal,
A display unit that receives the display signal and displays contents corresponding to the display signal;
A control unit for supplying power to the display signal output power supply terminal after writing the information signal for causing the display unit to perform a desired display to the memory after starting power supply to the memory power supply terminal. Characteristic display device. The display device according to claim 1,
The control unit includes a power supply circuit capable of switching whether to supply power to the display signal output power supply terminal, and when the power supply to the memory power supply terminal is started, the power supply of the power supply circuit is stopped, A display device, wherein after the information signal is written to the memory, power is supplied to the power supply circuit. The display device according to claim 1,
The control unit includes a microcontroller having an output port, and a voltage stabilizing circuit that supplies an output voltage of the output port to a predetermined voltage and supplies power to the display signal output power supply terminal.
The microcontroller does not output a voltage from the output port at the time of starting power supply to the memory power supply terminal, writes the information signal to the memory, and then outputs a voltage from the output port. apparatus. The display device according to claim 1,
An input side is connected to the memory power supply terminal and an output side is connected to the display signal output power supply terminal, and the power received at the input side is a predetermined time longer than a time for writing the information signal to the memory. The display device, wherein the control unit includes a delay circuit for delaying the output from the output side.

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