KR100915232B1 - A circuit for generating an on/off timing for a backlight - Google Patents

Abstract

The backlight on / off timing generating circuit of the present invention receives a signal that can distinguish a frame of a liquid crystal display device, and normal display state signal for generating a high level signal after delaying a predetermined number of frames when a pulse occurs normally. And a generation unit and an AND unit configured to generate a backlight ON / OFF timing signal by performing an AND operation on the signal output from the normal display state signal generator and the backlight switch signal. The normal display state signal generator is provided as many as the number of frames to be delayed by subtracting 1, and includes a D-flip flop connected in series with each other and a D-flip flop connected at the rear of the serially connected D-flip flops. And a logic sum element configured to perform an OR operation on the output terminal signal and the signal capable of distinguishing the frame, and output the common terminal to the clock terminal of each of the D flip-flops.

In the backlight on / off timing generation circuit of the present invention configured as described above, the backlight on / off operation is performed by performing an OR operation on a signal capable of distinguishing a frame generated after the initial setup of the liquid crystal display device or various voltage signals and a backlight switch signal. By generating the off timing signal, it is possible to control the backlight to be correctly turned on as soon as the initial setup time of the system equipped with the liquid crystal display is completed, without having to arbitrarily define the initial setup time.

Description

Backlight ON / OFF timing generating circuit {A CIRCUIT FOR GENERATING AN ON / OFF TIMING FOR A BACKLIGHT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a circuit for generating a backlight on / off timing that can mask anomalous display phenomenon during an initial driving setup time of a liquid crystal display.

Recently, in the field of display devices such as personal computers and televisions, large screens, light weights, and thinners are required. In order to satisfy such demands, a liquid crystal display (LCD) is used instead of a cathode-ray tube (CRT). Flat panel displays, such as liquid crystal displays, have been developed and put into practical use in the fields of display devices, liquid crystal televisions, and the like of desktop computers.

When a liquid crystal display is used in combination as a display device such as a computer or a television, when a user operates a backlight switch or the like to supply power to the entire system, an abnormal display phenomenon may occur when the screen is abnormally displayed during the initial driving setup time. This happens. Since the abnormal display phenomenon in the liquid crystal display device should not be seen by the user, it is configured to be displayed to the user after a certain time delay. To this end, a system such as a computer or a television equipped with a liquid crystal display device provides the inverter of the liquid crystal display device with a backlight lighting timing which is delayed by a predetermined time rather than the timing of the image signal. Fig. 1 compares the image signal timing with the backlight lighting timing. As shown in Fig. 1, the backlight lighting timing occurs after a predetermined time Td delay from the timing of the image signal. By doing so, the abnormal display phenomenon inevitably occurring in the liquid crystal display during the time Td is not seen by the user.

A problem with this conventional system timing is that the definition of the delay time Td is unclear. That is, the magnitude of the delayed time Td is a value that is arbitrarily determined by the system designer. In contrast, in the liquid crystal display, the initial setup time may be larger than the delay time Td. However, if the delay time Td is too large, the normal screen may be displayed on the liquid crystal display after pressing the backlight switch. It may take a long time until the user feels frustrated.

The present invention is to solve the conventional problems under the technical background as described above, and generates a signal indicating that the initial setup is completed in the liquid crystal display, by using this signal to control the lighting of the backlight after a minimum delay time It is an object of the present invention to provide a backlight on / off timing generating circuit.

The backlight on / off timing generation circuit of the present invention for achieving the above object,

A normal display state signal generator which receives a signal capable of distinguishing a frame of the liquid crystal display, and generates a high level signal after delaying a predetermined number of frames when a pulse occurs normally;

And a logic product configured to generate a backlight on / off timing signal by performing an AND operation on the signal output from the normal display state signal generator and the backlight switch signal.

Here, the normal display state signal generator

A D-flip-flop provided with the number of frames to be delayed minus one and connected in series with each other;

And a logic sum element configured to perform an OR operation on an output terminal signal of a rearmost connected D-flip flop and a signal capable of distinguishing the frame from the serially connected D-flip flops, and output the common operation to the clock terminals of the respective D-flip flops.

In the backlight on / off timing generation circuit of the present invention configured as described above, the backlight on / off operation is performed by performing an OR operation on a signal capable of distinguishing a frame generated after the initial setup of the liquid crystal display device or various voltage signals and a backlight switch signal. By generating the off timing signal, it is possible to control the backlight to be correctly turned on as soon as the initial setup time of the system equipped with the liquid crystal display is completed, without having to arbitrarily define the initial setup time.

The objects, technical configurations, and effects thereof of the present invention described above will become more apparent from the following description of the embodiments.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

Before describing the backlight on / off timing generating circuit according to the embodiment of the present invention, the preferred lighting timing of the backlight according to the present invention will be described with reference to FIGS. 2A and 2B.

As shown in FIG. 2A, an LCD module generation signal is generated in the present invention, and this signal is made of a predetermined signal used in the liquid crystal display device and indicates whether the display state is normal in the liquid crystal display device. That is, when the LCD module generation signal is at a high level, the initial setup is completed and the image data RGB data is normally output. The existing B / L lighting signal indicates a state in which the user turns on / off the backlight through a backlight switch operation. Therefore, as shown in FIG. 2B, the present invention controls the backlight to be turned on only in the T2 and T6 sections in which the liquid crystal display is in a normal display state and the user turns on the backlight switch. That is, in the present invention, a signal obtained by logically multiplying the LCD module generation signal and the existing backlight lighting signal is used as a backlight on / off signal. In this case, it is possible to control the backlight to be turned on precisely when the initial setup is completed and the image data and the synchronization signal are supplied from the system to the liquid crystal display.

Hereinafter, a backlight on / off timing generation circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, the backlight on / off timing generation circuit according to the first embodiment of the present invention will be described with reference to FIGS. 3 and 4.

3 illustrates a backlight on / off timing generating circuit according to a first embodiment of the present invention, and FIG. 4 illustrates waveforms of signals used in each circuit of FIG. 3.

As shown in FIG. 3, the backlight on / off timing generating circuit according to the first embodiment of the present invention includes a logic sum element 31, an input terminal D, a clock terminal CLK, an output terminal Q, and an inversion. It consists of two D-flip flops 32 and 33 and an AND element 34 each having an output stage / Q.

More specifically, the vertical synchronization signal Vsync is input to the two inputs of the logical sum element 31, while the output terminal Q signal of the D-flip-flop 33 is input. In the present embodiment, the vertical synchronization signal Vsync is used, but the technical scope of the present invention is not limited thereto, and a signal capable of distinguishing a frame used in the liquid crystal display, for example, a data enable (DE) signal and a vertical signal. One suitable among the signals such as the start signal STV may be selected.

The output signal of the logical sum element 31 is commonly provided to the clock terminals CLK of the respective D-flip flops 32 and 33. In addition, an inverted output terminal (/ Q) signal of the D-flip flop 33 is provided to an input terminal D of the D-flip flop 32, and an output terminal Q signal of the D-flip flop 32. Is provided at the input terminal D of the D flip-flop 33. The output terminal Q signal of the D-flip flop 33 is simultaneously provided to an input terminal of the logical sum element 31 and an input terminal of the logical AND element 34, and the logical AND element 34 is a switch signal of a backlight. (ON / OFF) is also input. The output signal of the AND product 34 is used as a backlight on / off timing signal BL_ON / OFF.

Next, an operation of the backlight on / off timing generation circuit according to the first embodiment of the present invention configured as described above will be described with reference to the waveform of FIG. 4.

First, during the initial setup time of the liquid crystal display, as shown in FIG. 4, the vertical synchronization signal Vsync maintains a low level, and each of the D flip-flops 32 and 33 has an output terminal. The signal Q maintains a low level and the inverted output stage signal / Q maintains a high level. Therefore, at the input terminal of the logical sum element 31, both the vertical synchronization signal Vsync and the other input terminal signals are at a low level. In this state, the vertical synchronizing signal Vsync is provided from the system to the liquid crystal display, and its waveform is shown in FIG. 4. The vertical sync signal Vsync has a pulse waveform. When the first pulse of the vertical synchronization signal Vsync is input, the output of the logical sum element 31 also becomes a high level due to the high level of the vertical synchronization signal Vsync. Therefore, since the output signal of the logical sum element 31 is used as the clock terminal signal of each of the D-flip flops 32 and 33, the respective D-flip flops 32 and 33 are used to change the state of the clock terminal CLK. The input terminal D is transmitted to the output terminal Q. More specifically, at the output terminal Q of the D-flop flop 32, a high level of the input terminal D, i.e., the inverted output terminal (/ Q) signal of the D-flop flop 33, is maintained. At the output terminal Q of the flip-flop 33, the low level, which is the signal of the input terminal Q, is maintained. In this state, when the second pulse of the vertical synchronization signal Vsync is input, the logic sum element 31 outputs a high level again, which causes the state at the clock stage CLK of each of the D-flip flops 32 and 33. Change occurs. Therefore, in each of the D flip-flops 32 and 33, the signal of the input terminal D is transmitted to the output terminal Q. That is, the high level maintained at the output terminal Q of the D-flip flop 32 is transmitted to the output terminal Q through the input terminal D of the D-flip flop 33, and the D-flip flop The inverting output terminal / Q of 33 changes to low level. The waveform of the OUT signal shown in FIG. 4 is the waveform of the output terminal Q signal of the D-flip flop 33. The high level of the output terminal Q of the D-flip flop 33 is provided to the AND device 34 and the AND device 31. Since one input of the OR element 31 is high level, the OR element 31 continues to output a high level irrespective of the vertical synchronization signal Vsync, and thus, each of the D-flip flops 32 and 33 Since the clock stage CLK signal does not change state later, the D-flip-flops 32 and 33 maintain their current state. The AND device 34 performs an AND operation on the output terminal signal OUT of the D-flip flop 33 and the backlight switch signal ON / OFF controlled by a user, and is illustrated in FIG. 4. As described above, the high level is output only when the two signals OUT and ON / OFF are high level. The signal output from the AND product 34 is provided to the liquid crystal display as a backlight on / off timing signal BL_ON / OFF.

As a result, the two D-flip-flops 32 and 33 output the high level from the second frame after delaying the first frame after the pulse of the vertical synchronization signal Vsync is normally generated. Signal that the state has started. The delay of one frame is caused by the time required for one frame to initialize the driver IC in the liquid crystal display. In the first embodiment, the number of frames to be delayed is adjusted by adjusting the number of the D-flip flops. Can be controlled.

In the first embodiment of the present invention described above, a signal indicating a normal display state of a liquid crystal display is generated by using a vertical synchronization signal for dividing a frame, and the result is obtained by logically multiplying the signal with a backlight switch signal operated by a user. By using the signal as a signal for controlling the lighting timing of the backlight, it is possible to control the backlight to be correctly turned on as soon as the initial set-up time of the system is completed without having to arbitrarily define the existing initial set-up time.

Next, a backlight on / off timing generation circuit according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6.

FIG. 5 illustrates a backlight on / off timing generating circuit according to a second embodiment of the present invention, and FIG. 6 illustrates waveforms of signals used in the circuit of FIG. 5.

In the backlight on / off timing generation circuit according to the second embodiment of the present invention, the gate turn-on voltage VON for turning on the thin film transistor of the liquid crystal display is used to generate the backlight on / off timing. Although the gate turn-on voltage VON is used to generate the backlight on / off timing in the second embodiment of the present invention, the technical scope of the present invention is not limited thereto, such as the gate turn-off voltage, the gamma reference voltage, and the like. After the setup of the liquid crystal display is completed, all signals generating a fixed voltage may be used. In FIG. 5, VON is a gate turn-on voltage and ON / OFF is a backlight switch signal by a user.

As shown in FIG. 5, the backlight on / off timing generation circuit according to the second embodiment of the present invention includes four transistors Q1 to Q4. Here, the two transistors Q2 and Q4 are npn-type bipolar transistors, and the two transistors Q1 and Q3 are pnp-type bipolar transistors, but the technical scope of the present invention is not limited thereto. It can also be configured with other transistors.

The backlight switch signal ON / OFF is input to the base of the transistor Q2 through resistors R8 and R9, the emitter of the transistor Q2 is connected to the ground potential, and the collector is a resistor R6, R7. Is connected to the base of the transistor Q1. A resistor R5, which acts as an internal resistor, is connected between the emitter and the base of the transistor Q1, and a power supply voltage VDD is connected to the emitter. The collector of transistor Q1 is connected to the emitter of transistor Q3. The emitter of the transistor Q4 is connected to the ground potential, and the gate turn-on voltage VON is connected to the base via the diode D and the resistors R1, R2, R4, and R13. The capacitor C and the resistor R3 are for removing noise. Meanwhile, the collector of the transistor Q4 is connected to the base of the transistor Q3 via resistors R10 and R12, and the resistor R11 operates as an internal resistance between the emitter and the base of the transistor Q3. This is connected. The collector voltage of the transistor Q3 is provided as a backlight on / off timing signal BL_ON / OFF.

Next, an operation of the backlight on / off timing generation circuit according to the second embodiment of the present invention configured as described above will be described with reference to the waveforms of the signals shown in FIG. 6.

First, in a system including a liquid crystal display, when a user operates a backlight switch (for example, it may be assumed to work simultaneously with a power switch of a computer), the backlight switch signal (ON / OFF) is turned on. The initial setup of the system and the liquid crystal display is performed. At this time, the backlight switch signal ON / OFF is high level, but the gate turn-on voltage VON is low level because the initial setup has not yet been completed. Accordingly, the transistor Q2 is turned on by the high level backlight switch signal ON / OFF, and the ground potential is input to the base of the transistor Q1 by turning on the transistor Q2. Since the transistor Q1 is of the pnp type, the transistor Q1 is turned on by the ground potential, and thus the power supply voltage VDD is input to the emitter of the transistor Q3. However, the gate turn-on voltage VON is not normally generated at this stage because the initial setup has not been completed yet. That is, the gate turn-on voltage VON is in a low level state, and accordingly, the transistor Q4 is turned off, and the transistor Q3 whose on / off is controlled by the transistor Q4 is also turned off. It is in a state. Since the transistor Q3 is turned off, the backlight on / off timing signal BL_ON / OFF maintains a low level.

When the initial setup of the liquid crystal display is completed as time passes, the gate turn-on voltage VON is normally generated, and as shown in FIG. 6, the gate turn-on voltage VON of 20 to 30 volts is output. When the gate turn-on voltage VON is input to the base of the transistor Q4, the transistor Q4 is turned on and a ground potential is input to the base of the transistor Q3. Since the transistor Q3 is of the pnp type, it is turned on by the ground potential input to the base. The power supply voltage VDD input through the transistor Q1 by the turn-on of the transistor Q3 is provided as a backlight on / off timing signal BL_ON / OFF. Referring to the waveform of FIG. 6, it can be seen that the backlight on / off timing signal BL_ON / OFF becomes high when both the gate turn-on voltage VON and the backlight switch signal ON / OFF are high level.

When the backlight on / off timing generation circuit according to the second embodiment of the present invention is used, the backlight is obtained by using a result of substantially ANDing the gate turn-on voltage and the backlight switch signal generated when the initial setup of the liquid crystal display is completed. By generating the on / off timing signal BL_ON / OFF, the backlight can be controlled to be turned on accurately as soon as the initial setup time of the system is completed, without having to arbitrarily define the existing initial setup time.

As described above, the backlight on / off timing generating circuit of the present invention performs an OR operation on a signal capable of distinguishing a frame generated after the initial setup of the liquid crystal display device or various voltage signals and a backlight switch signal. By generating a backlight on / off timing signal, it is possible to control the backlight to be correctly turned on as soon as the initial setup time of the system equipped with the liquid crystal display is completed, without having to arbitrarily define the initial setup time.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a comparison of timing of image signals and backlight lighting timing in a liquid crystal display according to the related art.

2A and 2B are diagrams for explaining preferred lighting timing of a backlight in the liquid crystal display according to the present invention.

3 illustrates a backlight on / off timing generation circuit according to a first embodiment of the present invention.

4 shows waveforms of signals used in the circuit of FIG.

5 is a diagram illustrating a backlight on / off timing generation circuit according to a second embodiment of the present invention.

6 shows waveforms of signals used in the circuit of FIG.

(Explanation of symbols for the main parts of the drawing)

31: logical sum element 32, 33: flip-flop

34: logical product

Claims (7)

A normal display state signal generator which receives a signal capable of distinguishing a frame of the liquid crystal display, and generates a high level signal after delaying a predetermined number of frames when a pulse occurs normally; A logic product for generating a backlight on and off timing signal by performing an AND operation on the signal output from the normal display state signal generator and the backlight switch signal; The normal display state signal generator A D-flip-flop provided with the number of frames to be delayed minus one and connected in series with each other; And a logic sum element configured to perform a logical OR operation on an output terminal signal of a rearmost connected D-flip flop and a signal capable of distinguishing the frame among the series-connected D-flip flops, and output the common signal to a clock terminal of each D-flip flop. Backlight on and off timing generator circuit. delete The method of claim 1, The inverted output terminal signal of the most recently connected D-flip flop among the respective D-flip flops is connected to be provided to the input terminal of the most recently connected D-flip flop. Backlight on and off timing generator circuit. The method of claim 1, The signal that can distinguish the frame is a vertical synchronization signal Backlight on and off timing generator circuit. A first switching device configured to receive a backlight switch signal and provide a ground potential when the backlight switch signal is at a high level; A second switching element that is turned on when a ground potential is provided in the first switching element and outputs a power supply voltage by turning on; A third switching element that is turned on by a signal generating a fixed voltage after the initial setup of the liquid crystal display is completed and provides a ground potential when the liquid crystal display is turned on; And, A fourth switching element which is turned on when a ground potential is provided in the third switching element, and outputs a power supply voltage output from the second switching element as a backlight on and off timing signal by turning on; Backlight on and off timing generator circuit. The method of claim 5, The first and third switching elements are npn type bipolar transistors, and the second and fourth switching elements are pnp type bipolar transistors. Backlight on and off timing generator circuit. The method of claim 5, After the initial setup of the liquid crystal display is completed, a signal for generating a fixed voltage is a gate turn-on voltage. Backlight on and off timing generator circuit.