KR100905337B1 - Gate drive integrated chip and the method of initialling thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving integrated circuit and a method for initializing the same in a liquid crystal display device without a gate printed circuit board. The present invention relates to a gate driving integrated circuit including a shift register and scanning a gate line by an output signal of the shift register. And a frame counting unit for counting the number of frames in synchronization with the first scan start signal, a delay unit for delaying and outputting the first scan start signal by a predetermined time, and an output signal and a scan disable signal of the delay unit. A logic operation unit configured to generate a second scan start signal by performing a logic operation, a clock signal for operation control, and generate and supply the first scan start signal to the frame counting unit, and count the frames counted by the frame counting unit. A controller configured to generate the scan disable signal according to a number; and start the clock signal and the second scan Receiving a call characterized by comprising a shift register for outputting a scanning gate signal line. Therefore, the present invention replaces the output enable signal related to the gate driving and initialization of the liquid crystal display device so that initialization can be performed by adjusting the timing of the scan start signal and the clock signal. There is an effect that can prevent.

Shift register, counter, scan start signal, initialization

Description

Gate drive integrated circuit and the method of initialization thereof

1 is a block diagram schematically showing a general fisheyeless liquid crystal display device.

2 is a waveform diagram illustrating a control signal applied to FIG. 1.

3 is a block diagram illustrating a gate driving integrated circuit according to the present invention.

4 is a waveform diagram illustrating a control signal applied to FIG. 3.

5 is a flowchart for explaining a method for initializing a gate driving integrated circuit according to the present invention;

* Code descriptions for the main parts of the drawings

100; Frame counting unit 120: delay unit

140: logical operation unit 160: control unit

180: shift register section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving integrated circuit and a method of initializing the same. In particular, in a liquid crystal display device in which a gate printed circuit board is removed, an output enable signal is not used by adjusting an output timing of a scan start signal and a clock signal. The present invention relates to a gate driving integrated circuit capable of initializing a gate driving integrated circuit and a method of initializing the same.

FIG. 1 is a block diagram schematically illustrating a typical PCBless liquid crystal display, and as illustrated in FIG. 1, a plurality of gate line scan signals are applied to the liquid crystal display panel 10 and the liquid crystal display panel 10. The gate driver IC 12, the plurality of source driver ICs 14 for applying a data signal to the liquid crystal display panel 10, the gate driver ICs 12, and the plurality of source driver ICs 14 are various. And a source printed circuit board 16 to which a power supply voltage and a control signal are applied.

The plurality of gate driver ICs 12 are mounted on a liquid crystal display device in a tape carrier package (TCP) or chip on glass (COG) method, and the plurality of gate driver ICs arranged in a line are connected to each other through the interconnection wires. And various control signals.

As shown in part A of FIG. 1, one gate driving IC includes various power supply voltages (DVDD, V _gl , V _gh , V _com , GND) and control signals (STV, CPV, OE) from the previous gate driving IC. Get supplied. Here, DVDD is the digital power supply voltage, V _gl is the gate driving voltage of the "low" level, V _gh is the gate driving voltage of the "high" level, V _com is the common voltage, GND is the ground voltage, STV (vertical) Start signal), CPV denotes a vertical clock signal, and OE denotes an output enable signal.

In the liquid crystal display device having the above-described printed circuit board removed, as a method for initializing the shift register of the gate driving IC, as shown in the waveform diagram of FIG. 2, the output enable signal OE is at least one. The register of the gate driving integrated circuit is initialized to "0" in the unknown state in the T1 section which is maintained at the logic level "high" state and then transitions to the logic level "low".

In this method, the gate driving circuit without the gate printed circuit board increases the number of signal lines to be wired on the liquid crystal display panel side, which is disadvantageous in the design of the wiring, which also disadvantages the design of other signal lines.

Accordingly, in order to solve the problem, the present invention replaces the output enable signal related to the gate driving and initialization of the liquid crystal display device so that initialization can be performed by adjusting the timing of the scan start signal and the clock signal. An object of the present invention is to provide a driving integrated circuit and a method for initializing the same, which can prevent a current rush caused by instability.

Another object of the present invention is to provide a gate driving integrated circuit and an initialization method thereof, which can reduce a panel wiring area by simplifying a control signal required for a liquid crystal display.

In the gate driving integrated circuit of the present invention for achieving the above object includes a shift register, the gate driving integrated circuit for scanning the gate line by the output signal of the shift register,

A frame counting unit counting the number of frames in synchronization with the first scan start signal;

A delay unit configured to delay the first scan start signal by a predetermined time and output the delayed signal;

A logic operation unit configured to receive the output signal of the delay unit and the scan disable signal and perform a logic operation to generate a second scan start signal;

A controller configured to generate a clock signal for operation control, generate the first scan start signal, supply the first scan start signal, and generate the scan disable signal according to the number of frames counted by the frame count unit; And

And a shift register unit configured to receive the clock signal and the second scan start signal and output a gate line scanning signal.

In the initialization method of a gate driving integrated circuit according to the present invention for achieving the above object, in the initialization method of a gate driving integrated circuit comprising a shift register,

Counting the number of frames;

Determining whether the counted frame number is smaller than a preset value;

Generating a scan disable signal of a first level when the counted frame number is smaller than a preset value as a result of the determining step;

Generating a scan disable signal of a second level when the counted frame number is not smaller than a preset value as a result of the determining step;

Initializing the shift register when the scan disable signal is at a first level; And

And when the scan disable signal is at the second level, enabling the scan start signal and supplying the scan start signal to the shift register.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a gate driving integrated circuit according to an exemplary embodiment of the present invention. As shown, a frame counting unit 100 that counts the number of frames x in synchronization with the first scan start signal STV_orgin and A delay unit 120 for delaying the first scan start signal STV_orgin by a predetermined time and outputting the output signal and the scan disable signal stvd of the delay unit 120 and performing a logic operation to perform a second scan start signal. A logic operation unit 140 for generating STV_real, a clock signal CPV for operation control, a first scan start signal STV_orgin, and supplied to the frame counting unit 100, and a frame counting unit The controller 160 generates a scan disable signal STVD according to the number of frames counted at 100, and receives a clock signal CPV and a second scan start signal STV_real to output a gate line scanning signal. The shift register unit 180 is configured.

The frame counting unit 100 is preferably configured to generate an output of 10 bits when using an XGA-class graphics board having a resolution of 1024 × 768.

The logic operation unit 140 inverts the inverter disables the scan disable signal STVD and outputs the AND gate, and the AND gate performs an AND operation on the output signal of the delay unit 120 and the output signal of the inverter INV. (AND).

4 is a waveform diagram illustrating a control signal applied to FIG. 3. Here, T2 is the clock signal CPV generated in at least one frame or more, and T3 is the second scan start signal STV_real when the scan disable signal STVD is at a logic level "high". T4 denotes a timing interval to be maintained, and T4 denotes a timing interval for keeping the scan disable signal STVD at a logic level 'high' state when the counted frame number is smaller than the preset value x, and FC denotes a counter count, respectively. .

The operation of the gate driving integrated circuit according to the present invention configured as described above will be described with reference to the flowchart of FIG. 5.

First, the frame counting unit 100 counts the number of frames (S10).

The frame counting unit 100 counts the number of frames in synchronization with the first scan start signal STV_orgin provided by the controller 160, and transmits the result to the controller 160.

When the tenth step S10 is completed, the controller 160 compares the size of the frame number counted by the frame counting unit 100 with the preset value x, and the counted frame number is the preset value x. It is determined whether it is smaller than (S12). Where x is any integer.

As a result of the determination in the twelfth step S12, when the counted frame number is smaller than the preset value x, the controller 160 generates a scan disable signal STVD having a logic level “high”, and the logic operation unit Provided to 140 (S14). In this case, the delay unit 120 is in a state in which the first scan start signal STV_orgin is delayed for a predetermined time and output.

As in the fourteenth step S14, when the scan disable signal STVD is at the logic level “high”, the logic operation unit 140 may be set to the logic level “low” regardless of the state of the first scan start signal STV_orgin. The second scan start signal STV_real is generated and provided to the shift register unit 180. In this case, the clock signal CPV generated by the controller 160 is continuously supplied to the shift register unit 180.

Then, the shift register unit 180 is initialized during the x−1 th frame period by the second scan start signal STV_real and the clock signal CPV of the logic level “low” (S18).

Preferably, in the embodiment of the present invention, since the preset value x is set to 4, the shift register unit 180 is initialized during the period of the third frame.

On the other hand, as a result of the determination in the twelfth step S12, when the counted frame number is not smaller than the preset value x, the controller 160 generates a scan disable signal STVD having a logic level “low”, This is provided to the logical operation unit 140 (S16). At this time, the delay unit 120 is in a state in which the first scan start signal STV_orgin is delayed for a predetermined time and output.

As in the sixteenth step S16, when the scan disable signal STVD is at a logic level “low,” the logical operation unit 140 logically combines the scan disable signal STVD and the first scan start signal STV_orgin. The second scan start signal STV_real of the logic level “high” is generated and provided to the shift register unit 180 (S16). In this case, the clock signal CPV generated by the controller 160 is continuously supplied to the shift register unit 180.

Then, the shift register unit 180 generates and outputs a gate line scanning signal from the time point at which the x-th frame is started by the second scan start signal STV_real and the clock signal CPV of the logic level “high” (S20). ).

Preferably, in the embodiment of the present invention, since the preset value x is set to 4, the shift register unit 180 generates and outputs a scanning signal from a time point at which the fourth frame starts.

While specific embodiments of the present invention have been described and illustrated above, it will be apparent that the present invention may be modified and practiced by those skilled in the art. Such modified embodiments should not be understood individually from the technical spirit or the prospect of the present invention, but should fall within the claims appended to the present invention.

As described above, the present invention replaces the output enable signal related to the gate driving and initialization of the liquid crystal display device so that initialization can be performed by adjusting the timing of the scan start signal and the clock signal. There is an effect that can prevent the current rush caused by.

In addition, the present invention has another effect of simplifying the control signal required for the liquid crystal display device, thereby reducing the panel wiring area and efficiently using the limited pattern forming space. For example, by minimizing the voltage drop by reducing the resistance by increasing the width of the gate low voltage line, it is possible to prevent blocking due to the voltage drop to increase the screen quality.

Claims (6)

A gate driving integrated circuit comprising a shift register and scanning a gate line by an output signal of the shift register, A frame counting unit counting the number of frames in synchronization with the first scan start signal; A delay unit for delaying and outputting the first scan start signal to synchronize with the scan disable signal; A logic operation unit configured to receive the output signal of the delay unit and the scan disable signal and perform a logic operation to generate a second scan start signal; A controller for generating a clock signal for operation control, generating the first scan start signal, supplying the first scan start signal, and generating the scan disable signal according to the number of frames counted by the frame count unit; And And a shift register unit configured to receive the clock signal and the second scan start signal and output a gate line scanning signal.  The method of claim 1, And the logic operation unit comprises an inverter for inverting the scan disable signal, and an AND gate for performing an AND operation on the output signal of the delay unit and the output signal of the inverter. The method of claim 1, And the control unit generates a scan disable signal having a logic level " high " when the number of frames counted by the frame counting unit is less than four. An initialization method of a gate driving integrated circuit including a shift register Counting the number of frames; Determining whether the counted frame number is smaller than a preset value; Generating a scan disable signal of a first level when the counted frame number is smaller than a preset value as a result of the determining step; Generating a scan disable signal of a second level when the counted frame number is not smaller than a preset value as a result of the determining step; Initializing the shift register when the scan disable signal is at a first level; And Enabling the scan start signal and supplying the scan start signal to the shift register when the scan disable signal is at the second level. The method of claim 4, wherein And the determining step determines whether the counted frame number is less than four. The method of claim 4, wherein And said first level is a logic level " high " and said second level is a logic level " low ".

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