CN109637478B - Display device and driving method - Google Patents
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- CN109637478B CN109637478B CN201910026806.0A CN201910026806A CN109637478B CN 109637478 B CN109637478 B CN 109637478B CN 201910026806 A CN201910026806 A CN 201910026806A CN 109637478 B CN109637478 B CN 109637478B
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- 239000004973 liquid crystal related substance Substances 0.000 description 3
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The invention provides a display device, which comprises a data processor and a static controller, wherein the data processor judges whether a display panel displays a static picture in at least one row area, and outputs a static trigger signal when judging that the static picture is displayed and a grid driver scans a grid line corresponding to at least one row area, and simultaneously a source driver outputs a low level; the static controller receives the output control signal output by the timing controller, and outputs a static control signal to the gate driver according to the received static trigger signal, so that the gate driver outputs a low level, or outputs a maintaining control signal which is the same as the output control signal to the gate driver according to the condition that the static trigger signal is not received, so that the gate driver normally outputs the gate signal. The invention also provides a driving method of the display device. The display device and the driving method can reduce the power consumption of the display device and prolong the service life of the display device.
Description
Technical Field
The present invention relates to the field of liquid crystal display technologies, and in particular, to a display device and a driving method thereof.
Background
Because Liquid Crystal Displays (LCDs) have the characteristics of low radiation, light volume, small weight, low power consumption and the like, they gradually replace the conventional Cathode Ray Tube (CRT) displays and are widely used in the fields of desktop computers, notebook computers, Personal Digital Assistants (PDAs), mobile phones, televisions and the like.
Currently, the driving method of the liquid crystal display is: the gate driver scans line by line and sequentially turns on the thin film transistor switches of the display panel along the gate lines from left to right, and the source driver sequentially turns on the thin film transistors along the source lines from top to bottom to charge the pixel capacitors of the display panel. Fig. 1 is a schematic diagram of a gate driver of a conventional lcd receiving signals. As shown in fig. 1, the gate driver receives a start signal stv (start vertical), a shift signal cpv (clock Pulse vertical), and an Output control signal OE1(Output Enable) Output from the timing controller. The output control signal OE1 is a periodic signal, and the gate controller can make the gate signal low or high according to the level of the output control signal OE 1. In addition, when the conventional display panel displays a static image in a region, the display panel receives the source signal output by the source driver and the voltage on the source signal remains unchanged, i.e., the voltage on the source signal does not change for each frame until the static image is switched to a dynamic image.
However, as the display technology is developed more and more, the requirement for power consumption is higher and higher, and thus a display device and a driving method are required to further reduce the power consumption of the display device.
Disclosure of Invention
In view of the above, the present invention is directed to a display device, which solves the problem of reducing power consumption of the display device.
Specifically, the embodiment of the invention provides a display device, which comprises a data processor and a static controller. The data processor judges whether at least one row area of the display panel displays a static picture according to an image data signal received by the source electrode driver, and when the data processor judges that the static picture is displayed and the grid electrode driver scans the grid electrode row corresponding to the at least one row area, the data processor outputs a static trigger signal and the source electrode driver outputs a low level; the static controller is connected with the time schedule controller, the data processor and the grid driver and used for receiving an output control signal output by the time schedule controller and outputting a static control signal to the grid driver according to the received static trigger signal output by the data processor so that the grid signal output by the grid driver becomes low level, or outputting a maintaining control signal which is the same as the output control signal to the grid driver according to the static trigger signal output by the data processor, so that the grid driver normally outputs the grid signal.
Further, in the process that the gate signal output by the gate driver changes to the low level, the gate signal is normally output at an interval of a refresh time, and the source driver outputs the source signal corresponding to the static picture at the same time.
Further, during the process of outputting the static trigger signal by the data processor, the static trigger signal is suspended to be output at intervals of the refresh time.
Further, the static controller comprises a first control module and a second control module; the first control module comprises a first input end, a second input end, a third input end and a first output end, the first input end receives an output control signal, the second input end receives a reference direct-current voltage, the third input end is used for receiving the static trigger signal, the second control module comprises a fourth input end, a fifth input end and a second output end, the fourth input end receives the output control signal, the fifth input end is connected with the first output end, and the second output end is connected with the gate driver; when the third input end of the first control module receives the static trigger signal, the first control module selectively receives the output control signal on the first input end, and the first output end outputs an intermediate signal with a level opposite to that of the output control signal; when the third input end of the first control module does not receive the static trigger signal, the first control module selectively receives the reference direct-current voltage on the second input end, and the first output end outputs the reference direct-current voltage.
Further, the first control module includes a first switching element and a second switching element; the first switch element comprises a first control end, a first path end and a second path end, the first control end of the first switch element is used for receiving the output control signal, and the second path end of the first switch element is grounded; the second switch element comprises a second control end, a third path end and a fourth path end, the second control end of the second switch element is connected with the first control end of the first switch element, the third path end of the second switch element receives a first power supply voltage, and the fourth path end of the second switch element is connected with the first path end of the first switch element; the first output end of the first control module is connected with the fourth path end of the second switch element and is also used for receiving the reference direct-current voltage; the second control module comprises a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element and an eighth switching element; the third switching element comprises a third control end, a fifth path end and a sixth path end, the third control end of the third switching element is connected with the fifth input end of the second control module, and the fifth path end of the third switching element receives the second power supply voltage; the fourth switching element comprises a fourth control end, a seventh path end and an eighth path end, the fourth control end of the fourth switching element is connected with the fifth input end of the second control module, the seventh path end of the fourth switching element receives the second power supply voltage, and the eighth path end of the fourth switching element is connected with the sixth path end of the third switching element; the fifth switch element comprises a fifth control end, a ninth path end and a tenth path end, the fifth control end of the fifth switch element is connected with the sixth path end of the third switch element, the ninth path end of the fifth switch element receives the second power supply voltage, and the tenth path end of the fifth switch element is connected with the second output end of the second control module; the sixth switching element comprises a sixth control end, an eleventh path end and a tenth path end, the sixth control end of the sixth switching element is connected with the fourth control end of the fourth switching element, and the tenth path end of the sixth switching element is grounded; the seventh switching element comprises a seventh control end, a tenth path end and a tenth path end, the seventh control end of the seventh switching element is connected with the third control end of the third switching element, the tenth path end of the seventh switching element is connected with the sixth path end of the third switching element, and the tenth path end of the seventh switching element is connected with the eleventh path end of the sixth switching element; the eighth switching element comprises an eighth control end, a fifteenth end and a sixteenth end, the eighth control end of the eighth switching element is connected with the sixth end of the third switching element, the fifteenth end of the eighth switching element is connected with the tenth end of the fifth switching element, and the sixteenth end of the eighth switching element is grounded.
Further, the first switch element, the sixth switch element, the seventh switch element and the eighth switch element are all NMOS transistors, and the second switch element, the third switch element, the fourth switch element and the fifth switch element are all PMOS transistors.
Further, the voltage value of the first power supply voltage is smaller than the voltage value of the second power supply voltage.
The embodiment of the invention also provides a driving method of a display device, which comprises the steps of judging whether at least one row area of a display panel displays a static picture according to an image data signal received by a source electrode driver, outputting a static trigger signal when the static picture is judged to be displayed and a grid electrode driver scans a grid electrode row corresponding to the at least one row area, and outputting a low level by the source electrode driver; receiving an output control signal output by the timing controller, and outputting a static control signal to the gate driver according to the received static trigger signal, so that the gate signal output by the gate driver becomes a low level, or outputting a maintaining control signal which is the same as the output control signal to the gate driver according to the condition that the static trigger signal is not received, so that the gate driver normally outputs the gate signal.
Further, the step of changing the gate signal output by the gate driver to a low level further includes: and normally outputting a grid signal at an interval of a refreshing time, and simultaneously outputting a source signal corresponding to the static picture by the source driver.
Further, the step of outputting a static control signal to the gate driver according to the received static trigger signal includes: and outputting an intermediate signal with a level opposite to that of the output control signal, and outputting a static control signal according to the intermediate signal and the output control signal.
According to the display device and the driving method provided by the embodiment of the invention, a static picture is displayed in at least one row area of the display panel, when the gate driver scans the corresponding gate row, the data processor outputs a static trigger signal, the static controller outputs a static control signal to the gate driver according to the static trigger signal, so that the gate signal output by the gate driver is changed into a low level, and meanwhile, the source driver can stop outputting the source signal to output the low level, so that the power consumption of the display device is reduced, and the service life of the display device is prolonged.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a gate driver of a conventional lcd receiving signals.
Fig. 2 is a schematic connection diagram of a display device according to a first embodiment of the invention.
Fig. 3 is a schematic connection diagram of a static controller of a display device according to a second embodiment of the invention.
Fig. 4 is a schematic connection diagram of a static controller of a display device according to a third embodiment of the invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the intended purpose, the following detailed description of the embodiments, methods, steps, structures, features and effects of the display device and the driving method according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the invention has been described in connection with specific embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.
First embodiment
Fig. 2 is a schematic connection diagram of a display device according to a first embodiment of the invention. The display device of the present embodiment includes a data processor 100, a static controller 200, a timing controller 300, a gate driver 500, a source driver 400, and a display panel 600.
The data processor 100 is connected to the source driver 400 and the static controller 200, and configured to determine whether the display panel 600 displays a static picture in at least one row area according to an image data signal received by the source driver 400, and when it is determined that the display panel 600 has at least one row area displaying a static picture and the gate driver 500 scans a gate row corresponding to the row area, the data processor 100 outputs a static trigger signal VA to the static controller 200, and the source driver 400 outputs a low level.
The static controller 200 is connected to the timing controller 300, the data processor 100 and the gate driver 500, and is configured to receive the output control signal OE1 output by the timing controller 300, and output a static control signal VB to the gate driver 500 according to the static trigger signal VA output by the data processor 100, so that the gate signal output by the gate driver 500 becomes a low level, or output a sustain control signal VC, which is the same as the output control signal OE1, to the gate driver 500 according to the static trigger signal VA output by the data processor 100 not being received, so that the gate driver 500 normally outputs the gate signal.
In an embodiment, in the process that the gate signal output by the gate driver 500 changes to the low level, the gate signal may be normally output at an interval of a refresh time, and the source driver 400 outputs the source signal corresponding to the static image at the same time. In one embodiment, during the process of outputting the static trigger signal VA by the data processor 100, the output of the static trigger signal VA is suspended at an interval refresh time.
In one embodiment, the static trigger signal VA may be high.
In one embodiment, the static control signal VB may be low.
Specifically, the data processor 100 may determine whether the image data signals corresponding to at least one row area on the display panel 600 are overlapped according to the image data signals received by the source driver 400, and if the image data signals are overlapped, determine that at least one row area of the display panel 600 displays a static picture, otherwise, determine that the image data signals are a dynamic picture. The following description will be made by taking an example of the row region corresponding to the nth row to the N + M th row of gate lines of the gate driver 500, where N and M are positive integers.
When the gate driver 500 scans any gate line corresponding to the line region of the static image, for example, the gate line in the nth line, the data processor 100 correspondingly outputs the static trigger signal VA, and the static controller 200 outputs the static control signal VB to the gate driver 500 according to the received static trigger signal VA, so that the gate signal output by the gate driver 500 to the gate line in the nth line changes to a low level. Wherein the static trigger signal VA may be high level, etc. Wherein the static control signal VB can be set to a low level accordingly according to the gate driver 500, and so on. Accordingly, when the tft on the nth row of the display panel 600 is in an off state, the corresponding source driver 400 cannot charge the pixel capacitor on the nth row of the display panel 600 through the off tft, and the pixel capacitor continues to maintain the voltage of the previous frame, and correspondingly displays the image of the previous frame. Since the row area displays a static picture, an image displayed in a frame on the row area is also an image to be displayed in the frame, and the voltage on the pixel capacitor in the nth row is also exactly the voltage required for displaying the image in the frame. Meanwhile, the source driver 400 may output a low level in response to stopping outputting the source signal, thereby reducing power consumption of the display device, for example, in an embodiment, the data processor 100 may output the static trigger signal VA, and the source driver 400 may be controlled to output a low level by the timing controller 300, or in another embodiment, the source driver 400 may receive the static trigger signal VA output by the data processor 100 and output a low level accordingly.
In order to prevent the distortion of the display image caused by excessive leakage of the pixel capacitors for a long time, the gate driver 500 may output the gate signal normally at an interval of a refresh time while the gate signal output by the gate driver changes to a low level, and the source driver 400 outputs the source signal corresponding to the still image, so that the pixel capacitors in the nth row are always the corresponding voltage of the still image. The gate driver 500 outputs the gate signal normally at an interval of a refresh time, which may be that the data processor 100 suspends outputting the static trigger signal VA at an interval of the refresh time in the process of outputting the static trigger signal VA, so that the gate driver 500 outputs the gate signal normally at an interval of the refresh time and continues to output the low level after normally outputting the gate signal for a period of time.
When the gate driver 500 scans any other gate row except the row area where the static picture is located, for example, the gate row of the (N + M + 1) th row, the data processor 100 does not output the static trigger signal VA accordingly, the static controller 200 outputs the sustain control signal VC, which is the same as the output control signal OE1, to the gate driver 500 according to the static trigger signal VA not being received, so that the gate row of the (N + M + 1) th row of the gate driver 500 normally outputs the gate signal, and thus the thin film transistors on the (N + M + 1) th row of the display panel 600 are in the on state, and the source driver 400 can charge the pixel capacitors on the (N + M + 1) th row of the display panel 600 through the on thin film transistors, so that the row area corresponding to the (N + M + 1) th row displays the corresponding dynamic picture.
In the display device of this embodiment, when the display panel 600 displays a static image in at least one row region, and the gate driver 500 scans the corresponding gate row, the data processor 100 outputs the static trigger signal VA, and the static controller 200 outputs the static control signal VB to the gate driver 500 according to the static trigger signal VA, so that the gate signal output by the gate driver 500 becomes a low level, and the source driver 400 can stop outputting the source signal and output the low level, thereby reducing the power consumption of the display device and prolonging the service life of the display device.
Second embodiment
Fig. 3 is a schematic connection diagram of a static controller of a display device according to a second embodiment of the invention. This embodiment is substantially the same as the first embodiment except that: the static controller 200 includes a first control module 210 and a second control module 220; the first control module 210 includes a first input terminal 211, a second input terminal 212, a third input terminal 213 and a first output terminal 214, the first input terminal 211 receives an output control signal OE1, the second input terminal 212 receives a reference dc voltage V1, the third input terminal 213 is configured to receive a static trigger signal VA, the second control module 220 includes a fourth input terminal 221, a fifth input terminal 222 and a second output terminal 223, the fourth input terminal 221 receives the output control signal OE1, the fifth input terminal 222 is connected to the first output terminal 214, and the second output terminal 223 is connected to the gate driver 500;
when the third input terminal 213 of the first control module 210 receives the static trigger signal VA, the first control module 210 selectively receives the output control signal OE1 on the first input terminal 211, and the first output terminal 214 outputs the intermediate signal VD having a level opposite to that of the output control signal OE 1; when the third input terminal 213 of the first control module 210 does not receive the static trigger signal VA, the first control module 210 selectively receives the reference dc voltage V1 at the second input terminal 212, and the first output terminal 214 outputs the reference dc voltage V1.
Specifically, when the gate driver 500 scans any gate line corresponding to the line region of the static image, for example, the nth row of gate lines, the data processor 100 correspondingly outputs the static trigger signal VA; the first control module 210 in the static controller 200 receives the static trigger signal VA according to the third input terminal 213 thereof, the internal circuit selectively receives the output control signal OE1 on the first input terminal 211 of the first control module 210 and converts the output control signal OE1 into the intermediate signal VD with the opposite level, and the first output terminal 214 of the first control module 210 outputs the intermediate signal VD to the fifth input terminal 222 of the second control module 220. And the fourth input terminal 221 of the second control module 220 receives the output control signal OE1, so that the second output terminal 223 of the second control module 220 can output the corresponding static control signal VB to the gate controller, so that the gate signal output by the gate driver 500 to the nth row of gate lines becomes low. Wherein the static trigger signal VA may be high level, etc. Wherein the static control signal VB can be set to a low level accordingly according to the gate driver 500, and so on. Accordingly, when the tft on the nth row of the display panel 600 is in an off state, the corresponding source driver 400 cannot charge the pixel capacitor on the nth row of the display panel 600 through the off tft, and the pixel capacitor continues to maintain the voltage of the previous frame, and correspondingly displays the image of the previous frame. Since the row area displays a static picture, an image displayed in a frame on the row area is also an image to be displayed in the frame, and the voltage on the pixel capacitor in the nth row is also exactly the voltage required for displaying the image in the frame. Meanwhile, the source driver 400 may output a low level in response to stopping outputting the source signal, thereby reducing power consumption of the display device, for example, in an embodiment, the data processor 100 may output the static trigger signal VA, and the source driver 400 may be controlled to output a low level by the timing controller 300, or in another embodiment, the source driver 400 may receive the static trigger signal VA output by the data processor 100 and output a low level accordingly.
When the gate driver 500 scans any other gate row outside the row region of the static image, for example, the gate row of the (N + M + 1) th row, the data processor 100 does not output the static trigger signal VA accordingly, the first control module 210 in the static controller 200 selects to receive the reference dc voltage V1 on the second input terminal 212 of the first control module 210 according to that the third input terminal 213 does not receive the static trigger signal VA, and outputs the reference dc voltage V1 at the first output terminal 214 of the first control module 210. The reference dc voltage V1 may be a high level voltage, or may be another voltage. The fourth input terminal 221 of the second control module 220 receives the output control signal OE1, so that the second output terminal 223 of the second control module 220 can output the same sustain control signal VC as the output control signal OE1 to the gate controller, so that the gate line of the (N + M + 1) th row of the gate driver 500 normally outputs the gate signal, and thus the tft of the (N + M + 1) th row of the display panel 600 is in an on state, and the source driver 400 can charge the pixel capacitor of the (N + M + 1) th row of the display panel 600 through the turned-on tft, so that the row area corresponding to the (N + M + 1) th row displays the corresponding dynamic image.
In the display device of this embodiment, the static controller 200 includes the first control module 210 and the second control module 220, when at least one row region of the display panel 600 displays a static picture and the gate driver 500 scans a corresponding gate row, the data processor 100 outputs the static trigger signal VA, the static controller 200 outputs the static control signal VB to the gate driver 500 according to the static trigger signal VA, so that the gate signal output by the gate driver 500 becomes a low level, and the source driver 400 can stop outputting the source signal and output the low level, thereby reducing the power consumption of the display device and prolonging the service life thereof.
Third embodiment
Fig. 4 is a schematic connection diagram of a static controller of a display device according to a third embodiment of the invention. This embodiment is substantially the same as the second embodiment except that: the first control module 210 includes a first switching element T1 and a second switching element T2, and the second control module 220 includes a third switching element T3, a fourth switching element T4, a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, and an eighth switching element T8.
The first switch element T1 includes a first control terminal, a first pass terminal and a second pass terminal, the first control terminal of the first switch element T1 is configured to receive the output control signal OE1, and the second pass terminal of the first switch element T1 is grounded. The second switching element T2 includes a second control terminal, a third path terminal and a fourth path terminal, the second control terminal of the second switching element T2 is connected to the first control terminal of the first switching element T1, the third path terminal of the second switching element T2 receives the first power voltage Vcc1, and the fourth path terminal of the second switching element T2 is connected to the first path terminal of the first switching element T1. The first output terminal 214 of the first control module 210 is connected to the fourth pass terminal of the second switching element T2, and is further configured to receive the reference dc voltage V1.
The third switching element T3 includes a third control terminal, a fifth terminal and a sixth terminal, the third control terminal of the third switching element T3 is connected to the fifth input terminal 222 of the second control module 220, and the fifth terminal of the third switching element T3 receives the second power voltage Vcc 2. The fourth switching element T4 includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element T4 is connected to the fifth input terminal 222 of the second control module 220, the seventh path terminal of the fourth switching element T4 receives the second power voltage Vcc2, and the eighth path terminal of the fourth switching element T4 is connected to the sixth path terminal of the third switching element T3. The fifth switching element T5 includes a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element T5 is connected to the sixth path terminal of the third switching element T3, the ninth path terminal of the fifth switching element T5 receives the second power voltage Vcc2, and the tenth path terminal of the fifth switching element T5 is connected to the second output terminal 223 of the second control module 220. The sixth switching element T6 includes a sixth control terminal, an eleventh path terminal and a tenth path terminal, the sixth control terminal of the sixth switching element T6 is connected to the fourth control terminal of the fourth switching element T4, and the tenth path terminal of the sixth switching element T6 is grounded. The seventh switching element T7 includes a seventh control terminal, a tenth switching terminal and a tenth switching terminal, the seventh control terminal of the seventh switching element T7 is connected to the third control terminal of the third switching element T3, the tenth switching terminal of the seventh switching element T7 is connected to the sixth switching terminal of the third switching element T3, and the tenth switching terminal of the seventh switching element T7 is connected to the eleventh switching terminal of the sixth switching element T6. The eighth switching element T8 includes an eighth control terminal, a fifteenth path terminal and a sixteenth path terminal, the eighth control terminal of the eighth switching element T8 is connected to the sixth path terminal of the third switching element T3, the fifteenth path terminal of the eighth switching element T8 is connected to the tenth path terminal of the fifth switching element T5, and the sixteenth path terminal of the eighth switching element T8 is grounded.
In an embodiment, the first switching element T1, the sixth switching element T6, the seventh switching element T7 and the eighth switching element T8 may all be NMOS transistors, in other embodiments, other types of transistors such as NPN transistors and the like may also be used, the second switching element T2, the third switching element T3, the fourth switching element T4 and the fifth switching element T5 are PMOS transistors, and in other embodiments, other types of transistors such as PNP transistors and the like may also be used.
In one embodiment, the voltage value of the first power supply voltage Vcc1 may be less than the voltage value of the second power supply voltage Vcc 2.
Hereinafter, the description will be given taking an example in which the static control signal VB is at a low level, the reference dc voltage V1 is at a high level, the first switching element T1, the sixth switching element T6, the seventh switching element T7, and the eighth switching element T8 are all NMOS transistors, and the second switching element T2, the third switching element T3, the fourth switching element T4, and the fifth switching element T5 are all PMOS transistors.
Specifically, when the gate driver 500 scans any gate row corresponding to the row area of the static image, for example, the nth row of gate rows, the data processor 100 correspondingly outputs the static trigger signal VA, for example, a high level, the first control module 210 in the static controller 200 receives the static trigger signal VA according to the third input terminal 213 thereof, and the internal circuit selectively receives the output control signal OE1 on the first input terminal 211 of the first control module 210.
When the output control signal OE1 is at a high level, the first control terminal of the first switch element T1 receives the output control signal OE1 as a high level, so that the first switch element T1 is turned on. The second control terminal of the second switch element T2 is connected to the first control terminal of the first switch element T1 and is correspondingly high, so that the second switch element T2 is turned off. And, the first output terminal 214 of the first control module 210 is connected to the first path terminal of the first switching element T1, so that the first output terminal 214 of the first control module 210 can be connected to the second path terminal of the first switching element T1 through the first switching element T1 in a conducting state, and the second path terminal of the first switching element T1 is grounded, so that the first output terminal 214 of the first control module 210 is grounded, i.e. the intermediate signal VD is at a low level. The fifth input terminal 222 of the second control module 220 is connected to the first output terminal 214 of the first control module 210, and the third control terminal of the third switching element T3 and the seventh control terminal of the seventh switching element T7 are both connected to the fifth input terminal 222 of the second control module 220, so that the third control terminal of the third switching element T3 and the seventh control terminal of the seventh switching element T7 are at a low level; meanwhile, the fourth input terminal 221 of the second control module 220 receives the output control signal OE1 and is at a high level, the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are both connected to the fourth input terminal 221 of the second control module 220, and then the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are at a high level. Accordingly, the sixth switching element T6 and the seventh switching element T7 of the seventh switching element T7 are in an off state, the sixth pass terminal of the third switching element T3 cannot be grounded through the seventh switching element T7 and the sixth switching element T6 in this order, and the third switching element T3 of the third switching element T3 and the fourth switching element T4 is in an on state, the sixth pass terminal of the third switching element T3 can be connected to the fifth pass terminal of the third switching element T3 through the on third switching element T3, and the fifth pass terminal of the third switching element T3 is connected to the second power supply voltage Vcc2, and the sixth pass terminal of the third switching element T3 is connected to the second power supply voltage Vcc2 at a high level. The fifth control terminal of the fifth switch element T5 and the eighth control terminal of the eighth switch element T8 are both connected to the sixth pass terminal of the third switch element T3 to be at a high level, so that the fifth switch element T5 is in an off state and the eighth switch element T8 is in an on state, the second output terminal 223 of the second control module 220 is connected to the sixteenth pass terminal of the eighth switch element T8 through the on eighth switch element T8, the sixteenth pass terminal of the eighth switch element T8 is connected to the ground, and the static control signal VB output by the second output terminal 223 of the second control module 220 is at a low level.
When the output control signal OE1 is at a low level, the first control terminal of the first switch element T1 receives the output control signal OE1 as a low level, so that the first switch element T1 is turned off. The second control terminal of the second switch element T2 is connected to the first control terminal of the first switch element T1 and is correspondingly high, so that the second switch element T2 is turned on. And, the first output terminal 214 of the first control module 210 is connected to the first path terminal of the first switch element T1, so that the first output terminal 214 of the first control module 210 can be connected to the third path terminal of the second switch element T2 through the second switch element T2 in an on state, and the third path terminal of the second switch element T2 receives the first power voltage Vcc1, and then the first output terminal 214 of the first control module 210 receives the first power voltage Vcc1, that is, the intermediate signal VD is at a high level. The fifth input terminal 222 of the second control module 220 is connected to the first output terminal 214 of the first control module 210, and the third control terminal of the third switching element T3 and the seventh control terminal of the seventh switching element T7 are both connected to the fifth input terminal 222 of the second control module 220, so that the third control terminal of the third switching element T3 and the seventh control terminal of the seventh switching element T7 are at a high level; meanwhile, the fourth input terminal 221 of the second control module 220 receives the output control signal OE1 and is at a low level, and the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are both connected to the fourth input terminal 221 of the second control module 220, so that the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are at a low level. Accordingly, if the sixth switching element T6 and the sixth switching element T6 of the seventh switching element T7 are in the off state, the sixth pass terminal of the third switching element T3 cannot be grounded through the seventh switching element T7 and the sixth switching element T6 in sequence, and the fourth switching element T4 of the third switching element T3 and the fourth switching element T4 is in the on state, the sixth pass terminal of the third switching element T3 may be connected to the seventh pass terminal of the fourth switching element T4 through the turned-on fourth switching element T4, and the seventh pass terminal of the fourth switching element T4 is connected to the second power supply voltage Vcc2, and the sixth pass terminal of the third switching element T3 is connected to the second power supply voltage Vcc2 at the high level. The fifth control terminal of the fifth switch element T5 and the eighth control terminal of the eighth switch element T8 are both connected to the sixth pass terminal of the third switch element T3 to be at a high level, so that the fifth switch element T5 is in an off state and the eighth switch element T8 is in an on state, the second output terminal 223 of the second control module 220 is connected to the sixteenth pass terminal of the eighth switch element T8 through the on eighth switch element T8, the sixteenth pass terminal of the eighth switch element T8 is connected to the ground, and the static control signal VB output by the second output terminal 223 of the second control module 220 is at a low level.
Accordingly, the first control block 210 in the static controller 200 receives the static trigger signal VA according to the third input terminal 213 thereof, the internal circuit selects to receive the output control signal OE1 at the first input terminal 211 of the first control block 210, the first output terminal 214 of the first control block 210 outputs the intermediate signal VD with the level opposite to that of the output control signal OE1, and the second output terminal 223 of the second control block 220 outputs the static control signal VB with the low level. Wherein the voltage value of the first power supply voltage Vcc1 may be less than the voltage value of the second power supply voltage Vcc2 to reduce power consumption. Accordingly, when the tft on the nth row of the display panel 600 is in an off state, the corresponding source driver 400 cannot charge the pixel capacitor on the nth row of the display panel 600 through the off tft, and the pixel capacitor continues to maintain the voltage of the previous frame, and correspondingly displays the image of the previous frame. Since the row area displays a static picture, an image displayed in a frame on the row area is also an image to be displayed in the frame, and the voltage on the pixel capacitor in the nth row is also exactly the voltage required for displaying the image in the frame. Meanwhile, the source driver 400 may output a low level in response to stopping outputting the source signal, thereby reducing power consumption of the display device, for example, in an embodiment, the data processor 100 may output the static trigger signal VA, and the source driver 400 may be controlled to output a low level by the timing controller 300, or in another embodiment, the source driver 400 may receive the static trigger signal VA output by the data processor 100 and output a low level accordingly.
When the gate driver 500 scans any other gate row outside the row region of the static image, for example, the gate row of the (N + M + 1) th row, the data processor 100 does not output the static trigger signal VA accordingly, and the first control module 210 in the static controller 200 selects to receive the reference dc voltage V1 at the second input terminal 212 of the first control module 210 according to that the third input terminal 213 does not receive the static trigger signal VA, for example, at a high level, and makes the first output terminal 214 of the first control module 210 receive the reference dc voltage V1 at a high level. The voltage value of the reference dc voltage V1 may be the same as the voltage value of the first power supply voltage Vcc 1. The fifth input terminal 222 of the second control module 220 is connected to the first output terminal 214 of the first control module 210, and the third control terminal of the third switching element T3 and the seventh control terminal of the seventh switching element T7 are both connected to the fifth input terminal 222 of the second control module 220, so that the third control terminal of the third switching element T3 and the seventh control terminal of the seventh switching element T7 are at a high level.
Meanwhile, when the output control signal OE1 is at a high level, the fourth input terminal 221 of the second control module 220 receives the output control signal OE1 as a high level, the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are both connected to the fourth input terminal 221 of the second control module 220, and the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are at a high level. Accordingly, when the sixth switching element T6 and the sixth switching element T6 of the seventh switching element T7 are both in the on state, the sixth path terminal of the third switching element T3 can be grounded to the low level through the seventh switching element T7 and the sixth switching element T6 in this order. The fifth control terminal of the fifth switch element T5 and the eighth control terminal of the eighth switch element T8 are both connected to the sixth pass terminal of the third switch element T3 to be at a low level, so that the fifth switch element T5 is in an on state and the eighth switch element T8 is in an off state, the second output terminal 223 of the second control module 220 is connected to the ninth pass terminal of the fifth switch element T5 through the on fifth switch element T5, and the ninth pass terminal of the fifth switch element T5 receives the second power voltage Vcc2, so that the sustain control signal VC output by the second output terminal 223 of the second control module 220 is at a high level.
When the output control signal OE1 is at a low level, the fourth input terminal 221 of the second control module 220 receives the output control signal OE1 as a low level, the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are both connected to the fourth input terminal 221 of the second control module 220, and the fourth control terminal of the fourth switching element T4 and the sixth control terminal of the sixth switching element T6 are at a low level. Accordingly, if the sixth switching element T6 and the sixth switching element T6 of the seventh switching element T7 are in the off state, the sixth pass terminal of the third switching element T3 cannot be grounded through the seventh switching element T7 and the sixth switching element T6 in sequence, and the fourth switching element T4 of the third switching element T3 and the fourth switching element T4 is in the on state, the sixth pass terminal of the third switching element T3 may be connected to the seventh pass terminal of the fourth switching element T4 through the turned-on fourth switching element T4, and the seventh pass terminal of the fourth switching element T4 is connected to the second power supply voltage Vcc2, and the sixth pass terminal of the third switching element T3 is connected to the second power supply voltage Vcc2 at the high level. The fifth control terminal of the fifth switch element T5 and the eighth control terminal of the eighth switch element T8 are both connected to the sixth pass terminal of the third switch element T3 to be at a high level, so that the fifth switch element T5 is in an off state and the eighth switch element T8 is in an on state, the second output terminal 223 of the second control module 220 is connected to the sixteenth pass terminal of the eighth switch element T8 through the on eighth switch element T8, the sixteenth pass terminal of the eighth switch element T8 is connected to the ground, and the sustain control signal VC output by the second output terminal 223 of the second control module 220 is at a low level.
Accordingly, the first control module 210 in the static controller 200 selectively receives the reference dc voltage V1 at the second input 212 of the first control module 210 according to the condition that the third input 213 does not receive the static trigger signal VA, the first output 214 of the first control module 210 outputs the reference dc voltage V1, and the second output 223 of the second control module 220 outputs the sustain control signal VC identical to the output control signal OE1 to the gate driver 500. The voltage value of the first power voltage Vcc1 may be smaller than the voltage value of the second power voltage Vcc2 to reduce power consumption, so that any other gate row outside the row region where the static image of the gate driver 500 is located, for example, the gate row of the (N + M + 1) th row, outputs the gate signal normally, so that the thin film transistor on the (N + M + 1) th row of the display panel 600 is in an on state, and the source driver 400 may charge the pixel capacitor on the (N + M + 1) th row of the display panel 600 through the on thin film transistor, so that the row region corresponding to the (N + M + 1) th row displays the corresponding dynamic image.
In the display device of this embodiment, the static controller 200 includes the first control module 210 and the second control module 220 including a plurality of switching elements, when at least one row region of the display panel 600 displays a static picture, when the gate driver 500 scans a corresponding gate row, the data processor 100 outputs the static trigger signal VA, the static controller 200 outputs the static control signal VB to the gate driver 500 according to the static trigger signal VA, so that the gate signal output by the gate driver 500 becomes a low level, and meanwhile, the source driver 400 can stop outputting the source signal and output the low level, thereby reducing the power consumption of the display device and prolonging the service life thereof.
Fourth embodiment
The present embodiment provides a driving method of a display device, including:
s1, determining whether the display panel 600 displays a static image in at least one row region according to the image data signal received by the source driver 400, and outputting a static trigger signal VA when it is determined that the static image is displayed and the gate driver 500 scans the gate lines corresponding to the at least one row region, and the source driver 400 outputs a low level at the same time;
s2, receives the output control signal OE1 outputted from the timing controller 300, and outputs the static control signal VB to the gate driver 500 according to the received static trigger signal VA, so that the gate signal outputted from the gate driver 500 becomes low level, or outputs the same sustain control signal VC as the output control signal OE1 to the gate driver 500 according to the non-reception of the static trigger signal VA, so that the gate driver 500 normally outputs the gate signal.
In one embodiment, the step of changing the gate signal output by the gate driver 500 to a low level further includes: the gate signal is normally output at an interval of a refresh time, and the source driver 400 outputs the source signal corresponding to the still picture at the same time.
In one embodiment, during the process of outputting the static trigger signal VA, the output of the static trigger signal VA may be suspended at intervals of a refresh time.
In one embodiment, the static trigger signal VA may be high.
In one embodiment, the static control signal VB may be low.
Specifically, the driving method of the present embodiment may refer to the detailed implementation of the first to third embodiments. In this embodiment, it is determined whether the image data signals corresponding to at least one row area on the display panel 600 are repeated according to the image data signals received by the source driver 400, and if so, it is determined that at least one row area of the display panel 600 displays a static picture, otherwise, it is a dynamic picture. The following description will be made by taking an example of the row region corresponding to the nth row to the N + M th row of gate lines of the gate driver 500, where N and M are positive integers.
When the gate driver 500 scans any gate line corresponding to the line region of the static picture, for example, the nth row of gate lines, the static trigger signal VA is correspondingly output, and the static control signal VB is output to the gate driver 500 according to the received static trigger signal VA, so that the gate signals output by the gate driver 500 to the nth row of gate lines are changed into a low level. Wherein the static trigger signal VA may be high level, etc. Wherein the static control signal VB can be set to a low level accordingly according to the gate driver 500, and so on. Accordingly, when the tft on the nth row of the display panel 600 is in an off state, the corresponding source driver 400 cannot charge the pixel capacitor on the nth row of the display panel 600 through the off tft, and the pixel capacitor continues to maintain the voltage of the previous frame, and correspondingly displays the image of the previous frame. Since the row area displays a static picture, an image displayed in a frame on the row area is also an image to be displayed in the frame, and the voltage on the pixel capacitor in the nth row is also exactly the voltage required for displaying the image in the frame. Meanwhile, the source driver 400 may output a low level in response to stopping outputting the source signal, thereby reducing power consumption of the display device, for example, in an embodiment, the source driver 400 may be controlled to output a low level by the timing controller 300 while outputting the static trigger signal VA, or in another embodiment, the source driver 400 may receive the static trigger signal VA and output a low level accordingly.
In order to prevent the distortion of the display image caused by excessive leakage of the pixel capacitors for a long time, the gate driver 500 may output the gate signal normally at an interval of a refresh time while the gate signal output by the gate driver changes to a low level, and the source driver 400 outputs the source signal corresponding to the still image, so that the pixel capacitors in the nth row are always the corresponding voltage of the still image. The gate driver 500 outputs the gate signal normally at an interval of a refresh time, where the interval of the refresh time may be in a process of outputting the static trigger signal VA, and the interval of the refresh time suspends outputting the static trigger signal VA, so that the gate driver 500 may output the gate signal normally at an interval of a refresh time and continues outputting the low level after normally outputting the gate signal for a period of time.
When the gate driver 500 scans any other gate row except the row region where the static picture is located, for example, the gate row of the (N + M + 1) th row, the static trigger signal VA is not output correspondingly, and the sustain control signal VC identical to the output control signal OE1 is output to the gate driver 500 according to the static trigger signal VA not being received, so that the gate row of the (N + M + 1) th row of the gate driver 500 outputs the gate signal normally, and thus the thin film transistors on the (N + M + 1) th row of the display panel 600 are in an open state, and the source driver 400 can charge the pixel capacitors on the (N + M + 1) th row of the display panel 600 through the opened thin film transistors correspondingly, so that the row region corresponding to the (N + M + 1) th row displays the corresponding dynamic picture.
In one embodiment, the step of outputting the static control signal VB to the gate driver 500 according to the received static trigger signal VA includes: an intermediate signal VD having a level opposite to that of the output control signal OE1 is output, and a static control signal VB is output based on the intermediate signal VD and the output control signal OE 1.
In one embodiment, the step of outputting the same asserted control signal VC as the output control signal OE1 to the gate driver 500 according to the absence of the static trigger signal VA comprises: the reference dc voltage V1 is output, and the sustain control signal VC is output according to the reference dc voltage V1 and the output control signal OE 1.
In the driving method of the display device of this embodiment, a static picture is displayed in at least one row region of the display panel 600, the gate driver 500 outputs the static trigger signal VA when scanning the corresponding gate row, and outputs the static control signal VB to the gate driver 500 according to the static trigger signal VA, so that the gate signal output by the gate driver 500 becomes a low level, and the source driver 400 can stop outputting the source signal and output the low level, thereby reducing the power consumption of the display device and prolonging the service life thereof.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A display device is characterized by comprising
The data processor (100), the said data processor (100) is according to the image data signal that the source driver (400) receives, judge whether the display panel (600) displays the static picture in at least one area of line, and when judging that displays the static picture and the gate driver (500) will scan the gate line that the area of said at least one line corresponds to, the said data processor (100) outputs the static trigger signal, the said source driver (400) outputs the low level at the same time;
the static controller (200) is connected with the timing controller (300), the data processor (100) and the gate driver (500), and is used for receiving an output control signal output by the timing controller (300), outputting a static control signal to the gate driver (500) according to a static trigger signal output by the data processor (100), and enabling a gate signal output by the gate driver (500) to be changed into a low level, or outputting a maintaining control signal which is the same as the output control signal to the gate driver (500) according to a static trigger signal not received by the data processor (100), and enabling the gate driver (500) to normally output the gate signal;
wherein the static controller (200) comprises a first control module (210) and a second control module (220); the first control module (210) comprises a first input end (211), a second input end (212), a third input end (213) and a first output end (214), the first input end (211) receives an output control signal, the second input end (212) receives a reference direct-current voltage, the third input end (213) is used for receiving the static trigger signal, the second control module (220) comprises a fourth input end (221), a fifth input end (222) and a second output end (223), the fourth input end (221) receives the output control signal, the fifth input end (222) is connected with the first output end (214), and the second output end (223) is connected with the gate driver (500);
when the third input terminal (213) of the first control module (210) receives the static trigger signal, the first control module (210) selects to receive the output control signal on the first input terminal (211), and the first output terminal (214) outputs an intermediate signal with a level opposite to that of the output control signal; when the third input terminal (213) of the first control module (210) does not receive the static trigger signal, the first control module (210) selects to receive the reference dc voltage on the second input terminal (212), and the first output terminal (214) outputs the reference dc voltage.
2. The display device according to claim 1, wherein the gate driver (500) outputs the gate signal normally at a refresh time interval while the gate signal is changed to the low level, and the source driver (400) outputs the source signal corresponding to the still picture.
3. The display device according to claim 2, wherein the data processor (100) suspends outputting the static trigger signal at intervals of the refresh time during outputting the static trigger signal.
4. The display device according to claim 1, wherein the first control module (210) comprises a first switching element and a second switching element;
the first switch element comprises a first control end, a first path end and a second path end, the first control end of the first switch element is used for receiving the output control signal, and the second path end of the first switch element is grounded;
the second switch element comprises a second control end, a third path end and a fourth path end, the second control end of the second switch element is connected with the first control end of the first switch element, the third path end of the second switch element receives a first power supply voltage, and the fourth path end of the second switch element is connected with the first path end of the first switch element;
a first output terminal (214) of the first control module (210) is connected to the fourth pass terminal of the second switching element, and is further configured to receive the reference dc voltage;
the second control module (220) comprises a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element and an eighth switching element;
the third switching element comprises a third control terminal, a fifth path terminal and a sixth path terminal, the third control terminal of the third switching element is connected with a fifth input terminal (222) of the second control module (220), and the fifth path terminal of the third switching element receives the second power supply voltage;
the fourth switching element comprises a fourth control end, a seventh path end and an eighth path end, the fourth control end of the fourth switching element is connected with a fifth input end (222) of the second control module (220), the seventh path end of the fourth switching element receives the second power supply voltage, and the eighth path end of the fourth switching element is connected with the sixth path end of the third switching element;
the fifth switch element comprises a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switch element is connected with the sixth path terminal of the third switch element, the ninth path terminal of the fifth switch element receives the second power voltage, and the tenth path terminal of the fifth switch element is connected with the second output terminal (223) of the second control module (220);
the sixth switching element comprises a sixth control end, an eleventh path end and a tenth path end, the sixth control end of the sixth switching element is connected with the fourth control end of the fourth switching element, and the tenth path end of the sixth switching element is grounded;
the seventh switching element comprises a seventh control end, a tenth path end and a tenth path end, the seventh control end of the seventh switching element is connected with the third control end of the third switching element, the tenth path end of the seventh switching element is connected with the sixth path end of the third switching element, and the tenth path end of the seventh switching element is connected with the eleventh path end of the sixth switching element;
the eighth switching element comprises an eighth control end, a fifteenth end and a sixteenth end, the eighth control end of the eighth switching element is connected with the sixth end of the third switching element, the fifteenth end of the eighth switching element is connected with the tenth end of the fifth switching element, and the sixteenth end of the eighth switching element is grounded.
5. The display device according to claim 4, wherein the first switching element, the sixth switching element, the seventh switching element, and an eighth switching element are all NMOS transistors, and wherein the second switching element, the third switching element, the fourth switching element, and the fifth switching element are all PMOS transistors.
6. The display device according to claim 5, wherein a voltage value of the first power supply voltage is smaller than a voltage value of the second power supply voltage.
7. A method of driving a display device, comprising:
according to an image data signal received by a source driver (400), judging whether a display panel (600) displays a static picture in at least one row area, and outputting a static trigger signal when the static picture is judged to be displayed and a gate driver (500) scans a gate row corresponding to the at least one row area, and simultaneously outputting a low level by the source driver (400);
receiving a reference direct current voltage, receiving an output control signal output by a timing controller (300), generating an intermediate signal with a level opposite to that of the output control signal according to the received static trigger signal, outputting a static control signal to the gate driver (500) according to the intermediate signal, so that the gate signal output by the gate driver (500) becomes a low level, or generating the reference direct current voltage according to the non-reception of the static trigger signal, outputting a maintaining control signal identical to the output control signal to the gate driver (500) according to the reference direct current voltage, and enabling the gate driver (500) to normally output the gate signal.
8. The driving method according to claim 7, wherein the step of changing the gate signal outputted from the gate driver (500) to a low level further comprises: the grid signal is normally output at an interval of a refreshing time, and the source driver (400) outputs the source signal corresponding to the static picture at the same time.
9. The driving method according to claim 7, wherein the step of outputting a static control signal to the gate driver (500) according to the received static trigger signal comprises: and outputting an intermediate signal with a level opposite to that of the output control signal, and outputting a static control signal according to the intermediate signal and the output control signal.
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
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