JPH099174A - Switching type power supply device - Google Patents

Abstract

PURPOSE: To easily attain reduction of power loss and noise elimination in the standby state of a switching power supply device in a computer system having a display device. CONSTITUTION: In the switching power supply device where a DC voltage is switched on/off by a switching transistor(TR) 7 and power is supplied to a master circuit 30 and a sub circuit 34 via an output transformer 5, when the main circuit 30 is normally driven, the switching TR 7 is turned on/off by a frequency the same as that of a horizontal synchronizing signal. In the standby state, the switching TR 7 is turned on/off by a frequency lower than that of the horizontal synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching type power supply device for a display device of a computer system, a television receiver (TV) having a remote control function.

[0002]

2. Description of the Related Art Computers such as personal computers
System display (monitor or display)
RCC (ringing choke converter) type switching regulator, which is one type of switching type power supply device, is used as the power supply device. This RCC type switching regulator has a feature that the circuit configuration is relatively simple. However, this RCC type switching regulator has a drawback that the on / off frequency of the switching element fluctuates significantly when the input voltage or the load changes while the output voltage is controlled to a constant value.

[0003]

By the way, the computer
In order to reduce unnecessary power consumption of the computer, if the time during which the computer is not used continues for a certain time or longer, the display device that consumes a relatively large amount of power is turned off, and the CPU that consumes a relatively small amount of power (central processing). The power supply of control circuit parts such as a device), a RAM (random access memory), a keyboard, etc. is kept on. The power saving control as described above is executed in the computer, whereby R
When the load on the CC type switching regulator decreases,
The on / off frequency of the switching element becomes extremely high, the switching loss of the switching element increases, and the efficiency at light load deteriorates. Also, when the load changes while using the display device, the on / off frequency of the switching element of the RCC type switching regulator changes, and noise on the display screen due to the on / off of the switching element becomes a problem. . Although the problem of the display device of the computer has been described, the same problem occurs in the television receiver having the remote control device.

Therefore, an object of the present invention is to provide a switching type power supply device which can improve efficiency under light load and can easily remove noise components under normal load.

[0005]

The present invention for achieving the above object will be described with reference to the reference numerals of the drawings of the embodiments. A horizontal synchronizing signal generating circuit 2 for forming a display device will be described.
A power supply device for supplying power to a main circuit 30 including 9a and a sub-circuit 34 that consumes less power than the main circuit 30, and is provided between one end 3 and the other end 4 of the DC power supply 2. A series circuit of a primary winding 6 of a connected transformer 5 and a switching element 7 having a control terminal, a first output winding 8 electromagnetically coupled to the primary winding 6, and the primary winding A second output winding 9 electromagnetically coupled to 6, a first rectifying and smoothing circuit 26 connected between the first output winding 8 and the main circuit 30, and a second output winding. Line 9 and the subcircuit 34
A second rectifying / smoothing circuit 33, control means 34 and 42 for selectively obtaining a driving state and a non-driving state of the main circuit 30, and the first rectifying / smoothing circuit 26.
Is connected to the voltage control signal forming circuit 50 and the horizontal synchronizing signal generating circuit 29a, and the horizontal synchronizing signal generating circuit 29a When a horizontal sync signal is generated from the first pulse train, a first pulse train having the same frequency as the horizontal sync signal and having a pulse width for controlling the output voltage of the first rectifying / smoothing circuit 26 to a predetermined value is generated. The switching element 7 is turned on / off by the first pulse train and has a frequency lower than that of the horizontal synchronizing signal when the horizontal synchronizing signal is not generated from the horizontal synchronizing signal generating circuit 29a. A second pulse train having a pulse width for controlling the output voltage of the first rectifying / smoothing circuit 26 to the predetermined value is formed.
And a pulse generation circuit 13 for controlling the switching element 7 to be turned on / off by the pulse train of FIG. It is preferable that the pulse generating circuit 13 is composed of a sawtooth wave generating circuit 56, a reference signal generating means 57, and a comparator 55 as described in claim 2. Further, as described in claim 3, the sub circuit 34 can be a control circuit including a microcomputer. Further, as described in claim 4, the sub circuit may be a remote control circuit of the television receiver.

[0006]

In the inventions of the claims, when the switching frequency is lowered when substantially only the sub circuit 34 is driven, the number of times of switching per unit time is reduced, the switching loss is reduced, and the efficiency is improved. Get higher Further, if the frequency is lowered when the sub-circuit 34 alone is under a light load (load with small power consumption), when a predetermined output voltage is obtained, the pulse width for turning on the switching element is higher than that when the frequency is high. It becomes possible to spread the pulse, and the pulse can be generated stably. In addition,
When the main circuit 30 is driven, the switching element 7 is turned on / off at the same high frequency as the horizontal synchronizing signal, so that the loss of the transformer is reduced and the size of the transformer can be reduced. Further, in the invention of each claim, when the main circuit 30 is driven, the switching element 7 is turned on / off at the same frequency as the horizontal synchronizing signal. Therefore, the frequency of the noise component generated due to ON / OFF of the switching element 7 becomes substantially constant, and this noise can be easily removed. As a result, noise on the display screen of the display device can be significantly suppressed. According to the invention of claim 2, the first
And the second pulse train can be easily obtained.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a power supply unit for a cathode ray tube (CRT) display device (display) of a computer system according to an embodiment of the present invention will be described.

In FIG. 1, a primary winding of a transformer 5 is provided between an output terminal of a DC power supply 2 composed of a rectifying and smoothing circuit connected to a pair of AC power supply terminals 1, that is, a DC power supply terminal 3 and a ground terminal 4. A series circuit of 6 and a transistor 7 as a switching element is connected. Transformer 5 is 1
It has first, second and third output windings 8, 9 and 10 as secondary windings electromagnetically coupled to the secondary winding 6. A first rectifying and smoothing circuit 26 including a diode 24 and a capacitor 25 is connected to the first output winding 8. The first rectifying / smoothing circuit 26 outputs, for example, 160V to the first output terminal 27. A DC / DC converter is provided at the first output terminal 27.
A main circuit 30 including a printer 28 and a horizontal deflection circuit 29 is connected. The main circuit 30 is a display device of a computer system, and includes a DC / DC converter 28 and a horizontal deflection circuit 2.
Although various circuits other than 9 are also included, they are omitted here. The DC / DC converter 28 forms a DC voltage required by the horizontal deflection circuit 29. Horizontal deflection circuit 2
Reference numeral 9 includes a horizontal synchronizing signal generating circuit 29a for generating a horizontal synchronizing pulse, that is, a horizontal synchronizing signal necessary for displaying by a cathode ray tube of the display device, a horizontal deflection voltage generating circuit (not shown), and the like.

A second rectifying / smoothing circuit 33 including a diode 31 and a capacitor 32 is connected to the second output winding 9. A second output terminal 54 connected to the second rectifying / smoothing circuit 33 has a CPU (central processing unit), a RAM (random access memory), a ROM (read only memory) in a computer system. ) And a microprocessor or microcomputer,
And a sub-circuit 34 including a keyboard and the like is connected. The power consumption of the sub circuit 34 is significantly smaller than that of the main circuit 30. Therefore, even if the power supply to the sub circuit 34 is continued during the standby period when the computer system is not substantially used, the power loss due to this is small. However, since the main circuit 30 consumes a large amount of power, it is desirable to put the main circuit 30 into a non-driving state when the computer system is not substantially used.

To achieve this end, the subcircuit 34 is
A means for determining whether or not the keyboard has been operated for a fixed time (for example, 5 minutes) or not, and a power saving command signal (power save) when the keyboard has not been operated for a fixed time or longer. Command signal) to the output terminal 42. In this embodiment, the power saving command signal is automatically generated, but instead of this, the power saving command signal can be manually formed by the operation of the keyboard or the switch and can be given to the terminal 42. The terminal 42 is connected to the horizontal deflection circuit 29, and the horizontal deflection circuit 2
A switch (not shown) for selectively driving 9 with a power saving command signal is turned on / off. In addition, the terminal 42 is DC
-It may be connected to the DC converter 28 and selectively turned on / off by a power saving command signal.

The third output winding 10 is for obtaining the power supply voltage of the PWM pulse generating circuit 13 and the driving circuit 15, and here, the capacitor 18 is provided via the diode 17.
Is connected. The voltage of the capacitor 18 is supplied to the PWM pulse generation circuit 13 and the drive circuit 15 via the constant voltage circuit 19a. In addition, 19 is a starting resistance,
It is connected between the power supply terminal 3 and the capacitor 18.

First, second and third output windings 8, 9, 1
The polarity of 0 is such that the diodes 24, 31, 17 are kept off while the transistor 7 connected in series to the primary winding 6 is on, and the diode 2 is on while the transistor 7 is off.
It is set so that 4, 31, 17 are turned on. Therefore, the power supply device of this embodiment is a flyback type or reverse type switching regulator.

In order to control the voltage of the first output terminal 27 at a constant level, a voltage control signal forming circuit 50 is connected to the output terminal 27. The voltage control signal forming circuit 50 is connected to the output terminal 27 for transmitting the voltage control signal formed here. The light emitting diode 12 is connected to the output terminal of the voltage control signal forming circuit 50 via a resistor 51. The PWM pulse generation circuit 13 also includes a phototransistor 14 optically coupled to the light emitting diode 12. Therefore, the PWM pulse generation circuit 13 generates PWM pulses having different pulse widths according to the amount of light emitted from the light emitting diode 12. The pulse generated from the PWM generation circuit 13 is given to the base of the transistor 7 via the drive circuit 15.

In this embodiment, the horizontal synchronizing signal line 16 derived from the horizontal deflection circuit 29 is connected to the PWM pulse generating circuit 13. The horizontal synchronizing signal line 16 gives the horizontal synchronizing signal extracted in a state of being insulated and separated by the transformer to the PWM pulse generating circuit 13. The PWM pulse generation circuit 13 has the same frequency as the horizontal synchronization signal when the horizontal synchronization signal is supplied from the line 16.
When the pulse train is generated and the horizontal synchronizing signal is not generated, the second pulse train is generated at a frequency lower than the frequency of the horizontal synchronizing signal. The horizontal deflection circuit 29 is
It is formed so as to selectively generate horizontal synchronizing signals of a plurality of types of frequency signals such as kHz, 38 kHz, and 48 kHz. The deflection voltage in the horizontal deflection circuit 29 is a DC / DC converter depending on the change in the frequency of the horizontal synchronizing signal.
The value is switched to a different value based on the data 30.

The voltage control signal forming circuit 50 for controlling the phototransistor 14 of FIG. 1 in accordance with the change of the voltage of the output terminal 27 has an output voltage detecting resistor 4 as shown in FIG.
5, 46, a reference voltage source zener diode 47, an error amplification transistor 48, and a resistor 49. The voltage detection resistors 45 and 46 are connected between the output terminal 27 and the ground terminal 28, and this voltage division point is connected to the base of the error amplification transistor 48. Zener diode 4
7 is connected between the output terminals 27 and 28 via the resistor 49, and supplies the reference voltage obtained here to the emitter of the transistor 48. In this embodiment, the higher the output voltage, the lower the collector potential of the error amplification transistor 48.
The anode of the light emitting diode 12 optically coupled to the phototransistor 14 is connected to the output terminal 27 via the current limiting resistor 51, and the cathode is connected to the collector of the error amplifying transistor 48.

As shown in FIG. 3, the PWM pulse generation circuit 13 of FIG. 1 is roughly divided into a comparator, that is, a voltage comparator 55.
And an off-width determining circuit 56 including a sawtooth wave generating means,
It has an ON width control circuit 57 including a reference signal generating means and a reference voltage source 58, forms a PWM pulse, and sends it to the drive circuit 15. Explaining each part in more detail, the off-width determining circuit 56 includes a capacitor C1 and a first, a second, and a third.
And a fourth resistor R1, R2, R3, R4, transistors Q10, Q11 and three diodes D1, D2, D3. The sawtooth wave generating capacitor C1 is connected between the power supply terminal 59 and the ground via a transistor Q11 and a diode D1. The first resistor R1 is connected in parallel with the capacitor C1 to form a discharge circuit. The upper end of the capacitor C1 is connected to the negative input terminal of the comparator 55. The base of the transistor Q11 is connected to the reference voltage source 58 via the resistor R3, and is also connected to the output terminal of the comparator 55 via the circuit composed of the resistor R2 and the diode D2. The resistor R2 and the diode D2 have a function of controlling the transistor Q11 to be off when the output of the comparator 55 becomes a low level and stopping the charging of the capacitor C1. The positive input terminal of the comparator 55 is connected to the reference voltage source 58 via the resistor R3, and also the comparator 55 via the resistor R2 and the diode D2.
It is also connected to the output terminal of. Transistor Q10 is connected in parallel with capacitor C1 via resistor R4 to switch the discharge time constant of capacitor C1. The base of the transistor Q10 is connected to the horizontal synchronizing signal line 16. The resistance R4 is set to a value much smaller than the resistance R1.

The ON width control circuit 57, which can also be referred to as reference signal generating means, includes a capacitor C2, a transistor Q12, a transistor Q13, a NOT circuit (inverter) 60, and a charge for controlling the output voltage. It is composed of a phototransistor 14 as a control element. In addition,
The phototransistor 14 functions as a means for adjusting the voltage level of the reference signal.

The upper end of the capacitor C2 is connected to the power supply terminal 59 via the phototransistor 14, and the lower end is connected to the ground. In order to relate the voltage V _{C2 of the} capacitor C2 to the comparator 55, a transistor Q12 is connected between the positive input terminal of the comparator 55 and the ground, and the base of the transistor Q12 is connected to the upper end of the capacitor C2. There is. Also, the discharge of the capacitor C2 is compared with the comparator 5
A transistor Q13 is connected in parallel to the capacitor C2 as a discharge control element to relate it to the output of the transistor 5, and the output terminal of the comparator 55 is connected to the base of the transistor Q13 via the NOT circuit 60.

Next, the operation of the circuit of FIG. 3 will be described with reference to the waveform chart of FIG. In FIG. 4, (A) shows the horizontal synchronizing signal, (B) shows both input voltages V1 and V2 of the comparator 55, (C) shows the voltage of the capacitor C2, and (D) shows the output of the comparator 55. Indicates. First, in the period from t1 to t2,
A reference voltage Vr (about 6.3 V) is obtained from a reference voltage source 58 composed of a Zener diode or the like, and this is supplied to a positive input terminal of a comparator composed of an operational amplifier, that is, a comparator 55. In addition, the first transistor passing through the first transistor Q11
A charging circuit for the capacitor C1 is formed. The first capacitor C1 is connected to the transistor Q11 from the reference voltage Vr.
It is charged to a value (about 5 V) obtained by subtracting the sum (V _BE + Vf) of the base-emitter voltage V _BE and the voltage V _f of the diode D1, that is, Vr- (V _BE + Vf). The voltage Vr (6.3 V) of the reference voltage source 58, that is, the voltage V1 is applied as a reference signal to the positive input terminal of the comparator 55. The maximum amplitude of the voltage V1 shown by the solid line in FIG. 4B is about 6.3V, and the maximum amplitude of the voltage V2 at the negative input terminal of the comparator 15 consisting of a sawtooth wave shown by the broken line is about 5V. The output of the comparator 55 is kept high (H). Since the difference between the two input voltages V1 and V2 is about 1.3V, malfunction due to noise can be sufficiently prevented. On the other hand, the CR time constant determined by the second capacitor C2 and the resistance of the phototransistor 14 is set sufficiently larger than the CR time constant determined by the first capacitor C1 and the resistance of this charging circuit. The voltage Vc2 of the capacitor C2 rises slowly with a slope during the ON period Ton of the transistor 7 as shown in the section t0 to t2 of FIG.
The output of the comparator 55 is at a high level during the ON period Ton,
Since the output of the NOT circuit 60 is low level and the third transistor Q13 is off, the discharging circuit of the second capacitor C2 is not formed. When the voltage Vc2 of the second capacitor C2 becomes about 0.75V, the second transistor Q12 is turned on, the voltage V1 as the reference signal of the positive input terminal of the comparator 55 decreases, and the negative input composed of a sawtooth wave. The voltage becomes lower than the terminal voltage V2, and at t2, the output of the comparator 55 changes to a low level (L). As a result, the second diode D2 is turned on, and the voltage V1 at the positive input terminal of the comparator 55 becomes {(Vr-Vf) (R2) / (R2 + R3)} + Vf during the off period Toff of the transistor 7. , Fixed to about 3V. Vf represents the forward voltage of each of the diodes D1 and D2. Also, NO
The output of the T circuit 60 is at a high level and the third transistor Q3
Is turned on, the electric charge of the second capacitor C2 is rapidly released through the transistor Q13, and the voltage Vc2 drops sharply. During the off period Toff from t2 to t3, the voltage V1 at the positive input terminal of the comparator 55, that is, the reference signal is lower than the voltage V2 at the negative input terminal, ie, the sawtooth wave, so that the first transistor Q11 and the first diode D1 are turned on. It will be in the reverse bias state and will be in the off state. For this reason,
The charging of the first capacitor C1 is stopped. As a result, when the main circuit 30 is driven, the charge of the first capacitor C1 is discharged through the resistor R1 and the first capacitor C1 is discharged.
The voltage of 1 and the voltage V2 at the negative input terminal of the comparator 55 fall with a ramp. When the horizontal synchronizing pulse shown in FIG. 4A is generated in the period of t3 to t4, the transistor Q10 is turned on and the resistor R4 is connected in parallel with the capacitor C1. Since the resistance R4 is set to a value much smaller than the resistance R1, the discharge of the capacitor C1 progresses rapidly. As a result, the voltage V2 of the capacitor C2 becomes lower than the voltage V1 of the positive input terminal of the comparator 55 at about time t3. The voltage V2 at the negative input terminal of the comparator 55 is the voltage V at the positive input terminal.
When it goes below 1, the output of the comparator 55 goes high again and the same operation is repeated. In the period from t3 to t4, the transistor Q10 is turned on and the capacitor C1 is turned on.
And the transistor Q11 is turned on to form a charging circuit for the capacitor C1. Therefore, the voltage V2 of the capacitor C1 during the period of t3 to t4 is kept at a value slightly lower than the voltage V1. Since the output pulse train of the comparator 55 is given to the transistor 7, the transistor 7 is turned on / off corresponding to the output pulse train shown in FIG. Since the horizontal synchronizing pulse (horizontal synchronizing signal) is repeatedly generated with a constant period T1 as shown in FIG. 4 (A) during the period when the main circuit 30 is operating normally, FIG. The PWM pulse repetition frequency and period are the same as the horizontal sync pulse. As a result, the frequency of the noise component due to the ON / OFF of the transistor 7 also becomes constant, and this noise component can be easily removed by a simple removal circuit. On the other hand, since the horizontal synchronizing signal is not generated in the standby period after time t5, the transistor Q10 in FIG. 3 is always kept off. Therefore, the discharge of the first capacitor C1 is performed only through the resistor R1.
The decreasing speed (gradient) of the voltage of the first capacitor C1, that is, the voltage V2 of the negative input terminal of the comparator 55 is t in FIG. 4 (B).
As shown in 6 to t7, it becomes gradual and the off period Toff
Becomes longer than when the main circuit 30 is driven,
The on / off repetition frequency of the transistor 7 is, for example, 18
As low as kHz, the loss of the transistor 7 becomes small. When the voltage of the output terminal 27 becomes higher than the desired value (120 V) in the driving period of the main circuit 30 before time t5, the resistance of the phototransistor 14 becomes small and the charging current of the second capacitor C2 becomes large. . As a result, the charging speed of the voltage Vc2 of the second capacitor C2 is increased, the second transistor Q12 is turned on within a short period from the time when the output voltage of the comparator 55 is turned to the high level, and the second transistor Q12 is turned on. As shown by the dotted line in D), the ON period Ton of the output pulse is shortened, the duty ratio is reduced, and the voltage at the output terminal 27 is returned to the desired voltage value.

When the main circuit 30 is not driven at the time of power saving after t5 and the horizontal synchronizing signal is not generated, the transistor Q10 in FIG. 3 is kept off, so that the capacitor C1 is not forcibly discharged. Therefore, the frequency of the sawtooth wave, that is, the voltage V2 becomes lower than the frequency of the horizontal synchronizing signal as shown after t5 in FIG. As a result, the frequency of the PWM pulse also decreases, and the switching transistor 7
Loss is reduced. Further, when the frequency of the PWM pulse decreases, the width of the PWM pulse can be widened when a constant output voltage is obtained, and the PWM pulse can be stably generated. Note that the transistor 7 turns on
Even if the off frequency becomes low, the current flowing through the windings 6 and 8 of the transformer 5 at this time is significantly smaller than that at the time of driving the main circuit 30, so that in the transformer 5 designed on the premise of high frequency, temperature rise or the like may occur. No problems arise.

[0021]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) Instead of detecting the output voltage from the output terminal 27, the output voltage is indirectly detected by providing a voltage detection winding on the transformer 5 or by detecting the voltage of the winding 11.
Based on this, constant voltage control can be performed. Winding 1
When 1 is also used for voltage detection, a voltage control signal forming circuit, that is, an error amplification circuit is connected to the capacitor 18,
A PWM pulse is created based on this output in the same manner as in the embodiment. (2) The transistor 7 is a field effect transistor (FE
It can be a semiconductor switch such as T). (3) The sub-circuit 34 is used as a remote control control circuit of the television receiver, and the main circuit 30 is used as the CRT of the television receiver.
Alternatively, it can be a liquid crystal display circuit. (4) The diode 24 can also be formed so as to be turned on when the transistor 7 is turned on. (5) The display device including the horizontal deflection circuit 29 can be a liquid crystal display device other than the CRT. That is, the present invention can be applied to all scanning display devices. (6) In FIG. 4, the PWM pulse of FIG. 4D is generated in synchronization with the rising edge of the horizontal sync pulse of FIG.
Instead, PWM is synchronized with the falling edge of the horizontal sync pulse.
Pulses can be generated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a switching type power supply device of an embodiment.

FIG. 2 is a circuit diagram showing in detail the voltage control signal forming circuit of FIG.

FIG. 3 is a circuit diagram showing the PWM pulse generation circuit of FIG. 1 and its output stage.

FIG. 4 is a waveform diagram showing a state of each part of the PWM pulse generation circuit.

[Explanation of symbols]

 7 Switching Transistor 13 PWM Pulse Generation Circuit 16 Horizontal Sync Signal Line 30 Main Circuit 34 Sub Circuit

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[Procedure amendment]

[Submission date] August 26, 1996

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

Next, the operation of the circuit of FIG. 3 will be described with reference to the waveform chart of FIG. In FIG. 4, (A) shows a horizontal synchronizing signal, (B) shows both input voltages V1 and V2 of the comparator 55, (C) shows the voltage of the capacitor C2, and (D) shows the output of the comparator 55. Indicates. First, in the period from t1 to t2,
A reference voltage Vr (about 6.3 V) is obtained from a reference voltage source 58 composed of a Zener diode or the like, and this is supplied to the positive input terminal of a comparator or comparator 55 composed of an operational amplifier. Further, a charging circuit for the first capacitor C1 passing through the first transistor Q11 is formed. This first
The capacitor C1 is connected to the transistor Q from the reference voltage Vr.
11 base-emitter voltage V _BE and diode D1
Is charged to a value (about 5 V) obtained by subtracting the sum (V _BE + Vf) from the voltage Vf of Vr− (V _BE + Vf).
The voltage Vr (6.3 V) of the reference voltage source 58, that is, the voltage V1 is applied as a reference signal to the positive input terminal of the comparator 55. The maximum amplitude of the voltage V1 shown by the solid line in FIG. 4B is about 6.3V, and the maximum amplitude of the voltage V2 at the negative input terminal of the comparator 15 consisting of a sawtooth wave shown by the broken line is about 5V. The output of the comparator 55 is kept high (H).
Since the difference between the two input voltages V1 and V2 is about 1.3 V, malfunction due to noise can be sufficiently prevented. On the other hand, the CR time constant determined by the second capacitor C2 and the resistance of the phototransistor 14 is set to be sufficiently larger than the CR time constant determined by the first capacitor C1 and the resistance of the charging circuit. Voltage V of capacitor C2
As shown in the section t0 to t2 in FIG. 4C, c2 has a slope and rises slowly in the on period Ton of the transistor 7. Since the output of the comparator 55 is high level, the output of the NOT circuit 60 is low level, and the third transistor Q13 is off in the on period Ton, the discharge circuit of the second capacitor C2 is not formed. When the voltage Vc2 of the second capacitor C2 becomes about 0.75V, the second transistor Q12 is turned on, the voltage V1 as the reference signal of the positive input terminal of the comparator 55 decreases, and the negative input composed of the sawtooth wave. The voltage becomes lower than the voltage V2 at the terminal, and the output of the comparator 55 changes to a low level (L) at t2. As a result, the second diode D2 is turned on, and the voltage V1 at the positive input terminal of the comparator 55 becomes {(Vr-Vf) (R2) / (R2 + R3)} + Vf during the off period Toff of the transistor 7. It is fixed at about 3V. Note that Vf represents the forward voltage of each of the diodes D1 and D2. Also, NO
The output of the T circuit 60 is at a high level, and the third transistor Q3
Is turned on, the charge of the second capacitor C2 is rapidly released through the transistor Q13, and this voltage Vc
2 drops sharply. During the off period Toff from t2 to t3, the voltage V1 at the positive input terminal of the comparator 55, that is, the reference signal is lower than the voltage V2 at the negative input terminal, that is, the sawtooth wave.
The first transistor Q11 and the first diode D1 becomes reverse biased, ing each off state. Therefore, the charging of the first capacitor C1 is stopped. As a result, when the main circuit 30 is driven, the first capacitor C
A charge of 1 is discharged through the resistor R1, and the voltage of the first capacitor C1 and the voltage V2 of the negative input terminal of the comparator 55 decrease with a slope. When the horizontal sync pulse shown in FIG. 4A is generated in the period from t3 to t4, the transistor Q10
Is turned on, and the resistor R4 is connected in parallel with the capacitor C1. Since the resistance R4 is set to a value significantly smaller than the resistance R1, the discharge of the capacitor C1 progresses rapidly. As a result, the voltage V2 of the capacitor C2 becomes lower than the voltage V1 of the positive input terminal of the comparator 55 at about time t3. When the voltage V2 at the negative input terminal of the comparator 55 becomes lower than the voltage V1 at the positive input terminal, the output of the comparator 55 becomes high level again, and the same operation is repeated. Note that t3 to t
During the four periods, the transistor Q10 is turned on to form a discharging circuit for the capacitor C1, and the transistor Q11 is turned on to form a charging circuit for the capacitor C1. Therefore, the voltage V2 of the capacitor C1 during the period from t3 to t4 is maintained at a value slightly lower than the voltage V1. Since the output pulse train of the comparator 55 is given to the transistor 7, the transistor 7 is turned on / off corresponding to the output pulse train shown in FIG. During the period when the main circuit 30 is operating normally, as shown in FIG.
Since the horizontal sync pulse (horizontal sync signal) having 1 is repeatedly generated, the repetition frequency and period of the PWM pulse in FIG. 4D are the same as the horizontal sync pulse. As a result,
The frequency of the noise component due to the ON / OFF of the transistor 7 also becomes constant, and this noise component can be easily removed by a simple removal circuit. On the other hand, since the horizontal synchronizing signal is not generated in the standby period after time t5, the transistor Q10 in FIG. 3 is always kept off. For this reason,
Since the discharge of the first capacitor C1 takes place only through the resistor R1, the voltage of the first capacitor C1 or the comparator 5
The rate (gradient) of the voltage V2 at the negative input terminal 5 of FIG. 5 becomes gentle as shown at t6 to t7 in FIG. 4B, and the off period Toff becomes longer than that when the main circuit 30 is driven.
The on / off repetition frequency of the switching transistor 7 is lowered to, for example, 18 kHz, and the loss of the transistor 7 is reduced. Main circuit 30 before time t5
During the driving period of, the voltage of the output terminal 27 is equal to the desired value (1
20V), the resistance of the phototransistor 14 decreases and the charging current of the second capacitor C2 increases. As a result, the voltage Vc of the second capacitor C2
2 becomes faster and the second transistor Q12 turns on within a short period from the time when the output voltage of the comparator 55 turns to a high level, and the output pulse as shown by the dotted line in FIG. The ON period Ton becomes shorter, the duty ratio becomes smaller, and the voltage of the output terminal 27 is returned to the desired voltage value.

Claims (4)

[Claims] 1. A main circuit (30) including a horizontal synchronizing signal generating circuit (29a) for constituting a display device, and a sub circuit (34) consuming less power than the main circuit (30).
A primary winding (6) of a transformer (5) connected between one end (3) and the other end (4) of a DC power supply (2) A series circuit with a switching element (7) having a control terminal, a first output winding (8) electromagnetically coupled to the primary winding (6), and an electromagnetic coupling to the primary winding (6). A second output winding (9), a first rectifying and smoothing circuit (26) connected between the first output winding (8) and the main circuit (30), The second rectifying and smoothing circuit (33) connected between the second output winding (9) and the sub circuit (34) and the main circuit (30) are selectively driven and non-driven. And a voltage control signal forming a voltage control signal for keeping the output voltage of the first rectifying and smoothing circuit (26) constant. Signal forming means (50), the voltage control signal forming circuit (50) and the horizontal synchronizing signal generating circuit (29a), and a horizontal synchronizing signal is generated from the horizontal synchronizing signal generating circuit (29a). Sometimes it has the same frequency as this horizontal sync signal and
Forming a first pulse train having a pulse width for controlling the output voltage of the rectifying / smoothing circuit (26) to a predetermined value, and turning on / off the switching element (7) by the first pulse train, Horizontal sync signal generator (29
When the horizontal synchronizing signal is not generated from a), it has a lower frequency than the horizontal synchronizing signal and has a pulse width for controlling the output voltage of the first rectifying and smoothing circuit (26) to the predetermined value. Forming a second pulse train,
And a pulse generation circuit (13) for ON / OFF controlling the switching element (7) by the pulse train of FIG. 2. The pulse generating circuit (13) responds to the horizontal synchronizing signal when the horizontal synchronizing signal is normally generated from the main circuit (30), and has the same frequency as the horizontal synchronizing signal. A sawtooth wave that generates a first sawtooth wave at a first frequency that has a second sawtooth wave at a second frequency lower than the frequency of the horizontal sync signal when the horizontal sync signal is not being generated. A generating circuit (56), and reference signal generating means (57) for generating a reference signal for controlling the output voltage of the first rectifying and smoothing circuit (26) to the predetermined value in response to the voltage control signal. Connected to the sawtooth wave generating circuit (56), the reference signal generating means (57) and the control terminal of the switching element (7), and when the first sawtooth wave is generated, the first sawtooth wave wave The first synchronizing signal having the same frequency as the horizontal synchronizing signal based on a comparison between the first synchronizing signal and the reference signal.
Pulse train of the second sawtooth wave is generated, and when the second sawtooth wave is generated, the second pulse train having a frequency lower than that of the horizontal synchronizing signal is generated based on the comparison between the second sawtooth wave and the reference signal. Comparator (55) for forming and supplying to the control terminal of the switching element (7)
The power supply device according to claim 1, comprising: 3. The power supply device according to claim 1, wherein the sub-circuit (34) is a control circuit including a microcomputer. 4. The sub-circuit is a remote control circuit of a television receiver.
Alternatively, the power supply device according to item 2.