JPH0717976B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0717976B2 JPH0717976B2 JP60282977A JP28297785A JPH0717976B2 JP H0717976 B2 JPH0717976 B2 JP H0717976B2 JP 60282977 A JP60282977 A JP 60282977A JP 28297785 A JP28297785 A JP 28297785A JP H0717976 B2 JPH0717976 B2 JP H0717976B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- wire
- bonding
- semiconductor device
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0104—Zirconium [Zr]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体のチップ電極と外部引出し用リードフレ
ームのインナーリード部とをワイヤボンディングした半
導体装置に関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor chip electrode and an inner lead portion of a lead frame for external extraction are wire-bonded.
一般に、トランジスタ、IC（集積回路）、LSI（大規模
集積回路）の如き半導体装置としては、例えば第３図に
示す構造のものが知られている。ダイフレーム１の上に
半導体チップであるペレット２をダイボンディングし、
このペレット２の電極とリードフレーム３とをボンディ
ングワイヤ４で電気的に接続した後、これらを樹脂５で
モールディングすることにより形成される。Generally, as a semiconductor device such as a transistor, an IC (integrated circuit), and an LSI (large-scale integrated circuit), for example, one having a structure shown in FIG. 3 is known. Die-bonding the semiconductor chip pellet 2 onto the die frame 1,
It is formed by electrically connecting the electrode of the pellet 2 and the lead frame 3 with a bonding wire 4 and then molding them with a resin 5.
上記ボンディングワイヤとして、熱圧着法あるいは超音
波併用熱圧着法によりボンディングするφ20〜100μｍ
の金、超音波法によりボンディングするφ25〜50μｍの
アルミニウム合金（Al-1.0wt.％Si,Al-1.0wt.％Mg等）
とφ100〜500μｍの高純度アルミニウム（99.99％以
上）が用いられている。As the above bonding wire, φ20 to 100 μm for bonding by thermocompression bonding or ultrasonic thermocompression bonding
Of gold, φ25 ~ 50μm aluminum alloy bonded by ultrasonic method (Al-1.0wt.% Si, Al-1.0wt.% Mg, etc.)
And high-purity aluminum (99.99% or more) with φ100 to 500 μm is used.
現在、金線は普及タイプのICやLSIに用い、アルミニウ
ム線はサーディプ型またパワートランジスタ用にと使い
わけられている。Currently, gold wire is used for popular type ICs and LSIs, and aluminum wire is used for sardip type and power transistors.
最近、集積度の増加に伴なう多ピン化の傾向によって、
金線のコストを無視することが出来なくなっている。そ
のため、ボンディングワイヤを高価な金線から比較的安
価な銅線に変更することが検討されている。Recently, due to the trend of increasing the number of pins with the increase in integration,
The cost of gold wire can no longer be ignored. Therefore, it is considered to change the bonding wire from an expensive gold wire to a relatively inexpensive copper wire.
銅線のボンディングボールは不活性雰囲気中で形成され
るが、ボール表面が酸化し、さらに金あるいはアルミニ
ウムに比べてボールが硬すぎるため、ボンディング時に
半導体チップの損傷あるいはボンディングの強度不足に
よるワイヤの剥離などが発生する場合がある。そこで、
この問題を解決し、期待される良好なボンディング性を
有する銅線の開発が望まれていた。Copper wire bonding balls are formed in an inert atmosphere, but the ball surface oxidizes, and the balls are too hard compared to gold or aluminum, so the wires are peeled off due to damage to the semiconductor chip during bonding or insufficient bonding strength. Etc. may occur. Therefore,
It has been desired to solve this problem and develop a copper wire having an expected good bonding property.
本発明はこのような問題を解決するためになされたもの
で、優れたボンディング性を有した銅ワイヤを用いた半
導体装置を提供することを目的とする。The present invention has been made to solve such a problem, and an object thereof is to provide a semiconductor device using a copper wire having excellent bonding properties.
本発明は半導体チップとの接続にワイヤボンディングを
用いた半導体装置において、前記ワイヤボンディング素
材として、マグネシウムを５〜150wt.ppm含有し、残部
が不純物として硫黄（Ｓ）を含有した銅からなる線材を
用いることを特徴とする半導体装置である。The present invention relates to a semiconductor device using wire bonding for connection to a semiconductor chip, wherein the wire bonding material is a wire material made of copper containing 5 to 150 wt.ppm of magnesium and the balance containing sulfur (S) as an impurity. A semiconductor device characterized by being used.
本発明者等はArガス等の不活性ガス中での放電あるいは
酸水素炎等により形成された銅ボールの硬化は、銅線中
に銅の不純物として固溶しているＳがボール表面に濃化
学偏析するためであることを見出した。さらに研究を進
めた結果、微量のMgの添加が、このＳの銅ボール表面で
の濃化偏析防止に有効であることを見出したのである。The inventors of the present invention have found that when a copper ball formed by discharge in an inert gas such as Ar gas or by an oxyhydrogen flame is hardened, S dissolved as a copper impurity in the copper wire is concentrated on the ball surface. It was found to be due to chemical segregation. As a result of further research, it was found that the addition of a small amount of Mg is effective in preventing the enriched segregation of S on the copper ball surface.
このマグネシウム（Mg）は微量の添加でＳの銅ボール表
面での濃化偏析を防止し、銅ボールの硬化を防止する効
果を発揮するが、あまり多いと銅中に固溶して強度が増
大し、銅ボールが硬化してボンディング後の接合強度が
低下してしまう。したがって、５〜150wt.ppmとする。
さらには、30〜90wt.ppmが好ましい。This magnesium (Mg) has the effect of preventing concentrated segregation of S on the copper ball surface by adding a trace amount and preventing the hardening of the copper ball, but if too much, it forms a solid solution in copper and the strength increases. However, the copper balls are hardened and the bonding strength after bonding is reduced. Therefore, the amount is 5 to 150 wt.ppm.
Furthermore, 30 to 90 wt.ppm is preferable.
また酸素含有量は20wt.ppm以下とすることが好ましい。
これは、酸素が20wt.ppm以上になると、銅ボールの硬化
に対して前記Mgの添加効果を低減するからである。Further, the oxygen content is preferably 20 wt.ppm or less.
This is because when the oxygen content is 20 wt.ppm or more, the effect of adding Mg on the hardening of the copper balls is reduced.
またMgに加え、さらにB,V,Ti,Zr,Cr,Hf等を加えること
もできる。B,V,Ti,Zr,Cr,Hf等の添加も同様に銅ボール
の硬化を防止することができる。しかしながら、余り大
量の添加はかえって銅ボールを硬化させてしまうため、
20wt.ppm以下が好ましい。添加する場合は、5wt.ppm以
上程度からその効果があらわれる。In addition to Mg, B, V, Ti, Zr, Cr, Hf and the like can be added. Similarly, addition of B, V, Ti, Zr, Cr, Hf, etc. can prevent the hardening of the copper balls. However, adding too much will rather harden the copper balls,
20 wt.ppm or less is preferable. When added, the effect appears from about 5 wt.ppm or higher.
残部が不純物としてＳを含有した銅であるが、Ｓと同様
に銅の不可避的不純物としてAg,Ni,Sn,Si,Te,Pb,Bi等を
除くものではない。The balance is copper containing S as an impurity, but like S, Ag, Ni, Sn, Si, Te, Pb, Bi, etc. are not excluded as inevitable impurities of copper.
以上説明したように本発明によれば、銅ボール表面にＳ
が濃化偏析するのを防止することができるため、接合強
度が高く、優れたボンディング性を有する半導体装置を
得ることができる。As described above, according to the present invention, S is formed on the surface of the copper ball.
Can be prevented from being concentrated and segregated, so that a semiconductor device having high bonding strength and excellent bonding properties can be obtained.
以下に本発明の実施例を説明する。 Examples of the present invention will be described below.
（実施例１） 純度99.99wt.％の無酸素銅にMgを添加した試料を真空溶
解により作製した。φ20mmの各鋳塊を面削し、1mmまで
冷間引抜き後、400℃で1hr焼鈍し、引抜き加工により、
φ25μｍ細線とした。次に線材を300℃で等温焼鈍を行
ない、試料とした。Example 1 A sample in which Mg was added to oxygen-free copper having a purity of 99.99 wt.% Was prepared by vacuum melting. Each ingot of φ20 mm is faced, cold drawn to 1 mm, annealed at 400 ° C for 1 hr, and drawn.
φ25 μm thin wire. Next, the wire was annealed at 300 ° C. to obtain a sample.
得られた試料をArガス中で放電により溶融してボールを
形成し、ボール断面の硬さをヌープ硬度計で測定した。
その結果を第１図に示す。第１図から明らかなように、
本発明に規定する範囲の添加で放電ボールの硬さ、比較
例の放電ボールに比べて低下していることが確認され
た。The obtained sample was melted by discharge in Ar gas to form a ball, and the hardness of the cross section of the ball was measured with a Knoop hardness meter.
The results are shown in FIG. As is clear from Fig. 1,
It was confirmed that the hardness of the discharge ball was lower than that of the discharge ball of the comparative example by the addition within the range specified in the present invention.
（実施例２） 純度99.99wt.％の無酸素銅の各種元素（99.99wt.％）を
添加して真空溶解した後、実施例１と同様な方法によっ
て試料（φ25μｍ）を作製した。各試料の組成は、第１
表に示す通りである。(Example 2) Various elements (99.99 wt.%) Of oxygen-free copper having a purity of 99.99 wt.% Were added and vacuum-melted, and then a sample (φ25 µm) was prepared by the same method as in Example 1. The composition of each sample is
As shown in the table.
硬さ測定およびプッシュ・テストの結果を同表に示す。
この表から明らかなように、本発明の実施例は優れた特
性を有していることが確認された。The results of hardness measurement and push test are shown in the same table.
As is clear from this table, it was confirmed that the examples of the present invention have excellent characteristics.
次にAESを用い、放電ボール表面からの不純物Ｓを分析
した結果を第２図に示す。比較例（純度99.99％の無酸
素銅）により形成した放電ボール表面に存在するＳ濃化
偏析は、本発明の実施例である試料１により形成した放
電ボール表面には認められなかった。他の実施例も同様
であった。Next, FIG. 2 shows the result of analysis of impurities S from the surface of the discharge ball by using AES. The S-enriched segregation existing on the surface of the discharge ball formed by the comparative example (oxygen-free copper having a purity of 99.99%) was not recognized on the surface of the discharge ball formed by sample 1 which is an example of the present invention. The other examples were similar.
第１図は硬度特性曲線図、第２図はＳピーク強度特性
図、第３図はプラスチックパッケージICを示す概略断面
図。 ２……ペレット ３……リードフレーム ４……ボンディングワイヤFIG. 1 is a hardness characteristic curve diagram, FIG. 2 is an S peak strength characteristic diagram, and FIG. 3 is a schematic sectional view showing a plastic package IC. 2 ... Pellet 3 ... Leadframe 4 ... Bonding wire
Claims (1)
グを用いた半導体装置において、前記ワイヤボンディン
グ素材として、マグネシウム（Mg）を５〜150wt.ppm含
有し、残部が不純物として硫黄（Ｓ）を含有した銅から
なる線材を用いることを特徴とする半導体装置。1. A semiconductor device using wire bonding for connection to a semiconductor chip, wherein the wire bonding material contains 5 to 150 wt.ppm of magnesium (Mg), and the balance contains sulfur (S) as an impurity. A semiconductor device using a wire made of copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282977A JPH0717976B2 (en) | 1985-12-18 | 1985-12-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282977A JPH0717976B2 (en) | 1985-12-18 | 1985-12-18 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8080525A Division JP2993660B2 (en) | 1996-03-11 | 1996-03-11 | Bonding wire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62142734A JPS62142734A (en) | 1987-06-26 |
| JPH0717976B2 true JPH0717976B2 (en) | 1995-03-01 |
Family
ID=17659592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60282977A Expired - Lifetime JPH0717976B2 (en) | 1985-12-18 | 1985-12-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0717976B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364211A (en) * | 1986-09-05 | 1988-03-22 | 古河電気工業株式会社 | Fine copper wire and manufacture thereof |
| JP2993660B2 (en) * | 1996-03-11 | 1999-12-20 | 株式会社東芝 | Bonding wire |
| JP4705078B2 (en) * | 2006-08-31 | 2011-06-22 | 新日鉄マテリアルズ株式会社 | Copper alloy bonding wire for semiconductor devices |
| JP6493047B2 (en) * | 2015-07-13 | 2019-04-03 | 日立金属株式会社 | Copper alloy material and method for producing the same |
-
1985
- 1985-12-18 JP JP60282977A patent/JPH0717976B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62142734A (en) | 1987-06-26 |
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