JPH07176754A - Thin-film transistor and display device using it - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor which reduces the influence of a parasitic capacitance and to provide a display device using it. CONSTITUTION:In a thin-film transistor 10, an insulating film 12 is formed on a glass substrate 11, and a semiconductor layer 13 is formed on it. A source electrode 14 and a drain electrode 15 are formed so as to sandwich the semiconductor layer 13, and a lightly doped source region 13a and a heavily doped source region 13b to which P-type impurities have been dispersed are formed on the source side of the semiconductor layer 13. A lightly doped drain region 13c and a heavily doped drain region 13d to which P-type impurities have been dispersed are formed on the drain side of the semiconductor layer 13, and a channel region 13e is formed in the central part. The lightly doped source region 13a is formed in such a way that its length is longer than that of the lightly doped drain region 13c, and the value of a source-side parasitic resistance is made larger than that of a drain-side parasitic resistance. A gate-gate insulating film 16 is laminated on the semiconductor layer 13, and a gate electrode 17 is laminated on the gate-gate insulating film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a display device using the thin film transistor.

[0002]

2. Description of the Related Art In general, an active matrix type liquid crystal display device has a gate line (scan electrode) 1 in the row direction as shown in FIG. 4 as an equivalent circuit for one pixel.
And a drain line (signal electrode) 2 is provided in the column direction. A data signal is input to the drain line 2 and a gate voltage is selectively applied to the gate line 1 sequentially in response to horizontal scanning.

A thin film transistor 3 as a switching element is connected to each pixel corresponding to each intersection of the gate line 1 and the drain line 2, and a pixel capacitor 4 composed of a liquid crystal capacitor and an auxiliary capacitor is provided on the source side of the thin film transistor 3. It is connected. One electrode 4a forming the pixel capacitor 4 is formed on the same TFT substrate side as the thin film transistor 3, and the other electrode 4b is formed on the common substrate side. The thin film transistor 3 has its gate electrode connected to the gate line 1 and its drain electrode connected to the drain line 2.

In such a liquid crystal display device, as shown in FIG. 4, the thin film transistor 3 has a channel resistance R _CH , a gate-source parasitic capacitance C _GS , a gate-drain parasitic capacitance C _GD , and a source side parasitic resistance R. _{It has S} and a drain side parasitic resistance R _D , and there is an overlapping capacitance C _L between the gate line 1 and the drain line 2 due to the overlapping of the gate line 1 and the drain line 2.

Further, the thin film transistor 3 generally has a parasitic resistance R _S on the source side and a parasitic resistance R on the drain side.
_D has almost the same value, and the gate-source parasitic capacitance C _GS and the gate-drain parasitic capacitance C _GD have almost the same value.

In such a liquid crystal display device, the thin film transistor 3 arranged in each pixel is turned on when the gate line 1 is selected, and the data signal voltage from the drain line 2 is applied to the pixel capacitor 4. Written in the form of electric charge. Then, while another gate line 1 is selected, the unselected thin film transistor 3 is turned off, and the pixel is driven by the written charges.

[0007]

However, in the conventional thin film transistor and the display device using the same, the thin film transistor has a parasitic resistance R _S on the source side thereof.
Since the parasitic resistance R _D on the drain side and the drain side have substantially the same value, and the parasitic capacitance C _GS between the gate and the source and the parasitic capacitance C _GD between the gate and the drain also have almost the same value, such a thin film transistor is displayed. When used as a switch element of the device, there was a problem that switching noise occurs and the image quality deteriorates.

That is, when the thin film transistor 3 is on, one electrode 4a of the liquid crystal on the side of the thin film transistor 3 is formed.
The drain line 2 and the drain line 2 have almost the same potential,
When the thin film transistor 3 is turned off, charge redistribution occurs between the pixel capacitance 4 including the liquid crystal and the auxiliary capacitance and the gate-source parasitic capacitance C _GS, which causes switching noise in which the potential of the liquid crystal deviates from the initial data potential. Occurs and the image quality deteriorates. This potential difference is caused by the thin film transistor 3
_Is almost proportional to the magnitude of the gate-source parasitic capacitance _CGS .

The parasitic capacitance of this thin film transistor is generally complicated depending on voltage and the like, and when this thin film transistor is used as a switching element of a display device, the potential shift of the liquid crystal becomes the signal voltage of the drain line 2. It occurs depending on. As a result, non-linearity between the liquid crystal transmittance and the data signal voltage is caused, and the image quality deteriorates.

Therefore, conventionally, various methods have been considered in order to reduce the switching noise.

One of the methods is to eliminate the overlap between the gate and the source of the thin film transistor and reduce the parasitic capacitance.

However, the parasitic capacitance of the thin film transistor is more than that caused by the overlap between the gate and the source.
The component due to the channel portion is large. Therefore, with this conventional method, the parasitic capacitance cannot be significantly reduced, and the switching noise cannot be sufficiently reduced.

The second method is to reduce the parasitic capacitance by reducing the size of the thin film transistor, that is, the channel length and the channel width.

However, in principle, this method can reduce the parasitic capacitance while maintaining a sufficient driving force, but there is a limit in processing accuracy of the thin film transistor, and the parasitic capacitance cannot be sufficiently reduced. .

The third method is a method of suppressing the potential shift due to charge redistribution when the thin film transistor is turned off, by increasing the auxiliary capacitance.

However, in this method, when the area is increased for the auxiliary capacitance, the aperture ratio of the liquid crystal is reduced accordingly, so that there is a limit to increase the auxiliary capacitance, and switching noise can be sufficiently reduced. Can not.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and the source side parasitic resistance of the thin film transistor is set to a value larger than the drain side parasitic resistance, so that the pixel of the display device to which the thin film transistor is applied. Provided are a thin film transistor and a display device using the thin film transistor, which can reduce redistribution of electric charge generated between a capacitor and a parasitic capacitance on a source side of a thin film transistor and reduce deviation of a potential of a liquid crystal from an initial data potential. The purpose is to do.

[0018]

A thin film transistor according to the present invention is a thin film transistor in which a semiconductor layer, a source electrode, a drain electrode and a gate electrode are formed on the semiconductor layer with a gate insulating film sandwiched between the semiconductor layer, The above-mentioned object is achieved by making the parasitic resistance larger than the parasitic resistance on the drain side.

In this case, for example, by making the length of the source region of the semiconductor layer longer than the length of the drain region of the semiconductor layer, the parasitic resistance on the source side is drained. The value may be larger than the parasitic resistance on the side, and by setting the amount of impurities in the source region of the semiconductor layer to be smaller than the amount of impurities in the drain region of the semiconductor layer as described in claim 3. The source-side parasitic resistance may be larger than the drain-side parasitic resistance.

In the display device of the present invention, the drain electrode of the thin film transistor is connected to the signal line, the source electrode of the thin film transistor is connected to the common electrode of the liquid crystal, and the gate electrode of the thin film transistor is connected to the gate line. Claim 1 as a thin film transistor
The use of the thin film transistor according to any one of claims 1 to 3 achieves the above object.

[0021]

According to the thin film transistor of the present invention, the parasitic resistance on the source side of the thin film transistor, in which the semiconductor layer, the source electrode, the drain electrode, and the gate electrode are formed on the semiconductor layer with the gate insulating film interposed therebetween, is used to reduce the parasitic resistance on the source side. The parasitic resistance on the source side can be apparently reduced, and the influence of the parasitic capacitance can be reduced.

Further, according to the display device of the present invention, a display in which the drain electrode of the thin film transistor is connected to the signal line, the source electrode of the thin film transistor is connected to the common electrode of the liquid crystal, and the gate electrode of the thin film transistor is connected to the gate line. As the thin film transistor of the device, a parasitic resistance on the source side of the thin film transistor connected to the common electrode of the liquid crystal is apparently reduced because a thin film transistor having a parasitic resistance on the source side larger than a parasitic resistance on the drain side is used. Therefore, redistribution of electric charge generated between the pixel capacitance on the liquid crystal side and the parasitic capacitance on the source side of the thin film transistor when the thin film transistor is turned off can be suppressed. As a result, noise generated due to switching of the thin film transistors can be reduced and the image quality can be improved.

[0023]

EXAMPLES The present invention will be described below based on examples.

1 and 2 are views showing an embodiment of a thin film transistor of the present invention and a display device using the thin film transistor.

FIG. 1 is a front sectional view of a thin film transistor 10 of the present invention, which is formed by stacking a thin film by vapor deposition sputtering, plasma CVD or etching.

That is, in FIG. 1, the thin film transistor 10 comprises a silicon nitride (SiN) film formed on the glass substrate 11.
Alternatively, the insulating film 12 made of silicon oxide (SiO) is formed, and the semiconductor layer 13 made of intrinsic polysilicon is formed on the insulating film 12.

A source electrode 14 is formed on the right side of the semiconductor layer 13 in FIG. 1 so as to cover the right end of the semiconductor layer 13, and a drain electrode 15 is formed on the left side of the semiconductor layer 13 in FIG. It is formed so as to cover the left end of the layer 13.

This semiconductor layer 13 has, on its source side,
The P-type impurity is divided into a low concentration region and a high concentration region and diffused by doping or the like, so that the low concentration source region 13a is formed.
(Indicated by P ⁻ in FIG. 1) and the high concentration source region 13b (see FIG.
(Indicated by P ⁺ ) is formed therein.

On the drain side of the semiconductor layer 13, P-type impurities are divided into low concentration and high concentration and diffused by doping or the like, and the low concentration drain region 13c (P ^{− in} FIG. 1). (Displayed with) and high-concentration drain region 13
d (denoted by P ⁺ in FIG. 1) is formed.

Further, a channel region 13e is formed in the central portion of the semiconductor layer 13.

The high-concentration source region 13b and the high-concentration drain region 13d of the semiconductor layer 13 are formed to have the same length, but the low-concentration source region 13a is longer than the low-concentration drain region 13c. Is formed long.

The gate insulating film 1 is formed on the semiconductor layer 13.
6 is formed by stacking, and the gate electrode 17 is formed by stacking on the gate insulating film 16.

Therefore, in the thin film transistor 10, since the low concentration source region 13a of the semiconductor layer 13 is formed longer than the low concentration drain region 13c, the source side parasitic resistance R _S is larger than the drain side parasitic resistance R _D. Has become.

Such a thin film transistor 10 is shown in FIG.
When used as a switching element of the active matrix type liquid crystal display device shown in FIG. 1, the thin film transistor 10 is connected to each pixel corresponding to each intersection of the gate line 1 and the drain line 2, and the thin film transistor 10 is connected.
The source electrode 14 is connected to the pixel capacitance 4 which is composed of a liquid crystal capacitance and an auxiliary capacitance which compensates for the shortage of the pixel capacitance of the liquid crystal pixel.
Then, the thin film transistor 10 has its gate electrode 17
Is connected to the gate line 1, and its drain electrode 15 is connected to the drain line 2.

The thin-film transistor 10 is similar to the thin-film transistor 3 shown in FIG. 4 in that it has a channel resistance R _CH , a gate-source parasitic capacitance C _GS , a gate-drain parasitic capacitance C _GD , a source-side parasitic resistance R _S and It has a drain-side parasitic resistance R _D , and there is an overlapping capacitance C _L between the gate line 1 and the drain line 2 due to the overlapping of the gate line 1 and the drain line 2.

In such a liquid crystal display device, similarly to the above, the thin film transistor 10 arranged in each pixel is
When the gate line 1 is selected, the gate line 1 is turned on, and the data signal voltage from the drain line 2 is written in the pixel capacitor 4 in the form of electric charge. Then, while another gate line 1 is selected, the non-selected thin film transistor 10 is turned off, and the pixel is driven by the written charges.

When the thin film transistor 10 is turned on, the source electrode 14 of the liquid crystal thin film transistor 10 is turned on.
The drain line 2 and the drain line 2 have almost the same potential,
When the thin film transistor 10 is turned off, redistribution of charges occurs between the pixel capacitance 4 including the liquid crystal and the auxiliary capacitance and the gate-source parasitic capacitance C _GS .

However, in the thin film transistor 10, as described above, the high concentration source region 13b and the high concentration drain region 13d of the semiconductor layer 13 are formed to have the same length, but the low concentration source region 13a is low. It is formed to be longer than the concentration drain region 13c. Therefore, the source side parasitic resistance R _{S of} the thin film transistor 10 has a larger value than the drain side parasitic resistance R _D. As a result, the source side parasitic resistance R _S having a large resistance value is connected to the pixel capacitance 4, and an effect similar to that when the gate-source parasitic capacitance C _GS is reduced occurs, and an AC component flows. It will be difficult. Therefore, the thin film transistor 1
Redistribution of electric charge generated between the pixel capacitance 4 and the gate-source parasitic capacitance C _GS when 0 is turned off can be reduced, and noise due to the switching operation of the thin film transistor 10, so-called switching noise, can be reduced. You can As a result, the image quality can be improved.

In order to verify the relationship between the source-side parasitic resistance R _S of the thin film transistor 10 and the switching noise, the voltage of the liquid crystal electrode when the length of the low concentration source region 13a of the thin film transistor 10 is changed. The change was measured.

The change in the voltage of the liquid crystal electrode is measured by using a thin film transistor 10 made of a polysilicon P-channel type and having a film thickness of 50 nm, a gate width and a gate length of 2 μm, and a mobility of 60 cm ² / V · S. It was Also,
The overlap between the gate and the source and the overlap between the gate and the drain are both 0, that is, self-aligned, and LDD
The sheet resistance of the low concentration source region 13a and the low concentration drain region 13c is 200 KΩ / □, and other conditions are standard conditions.

The data signal voltage is set to 11.5 [V] and the drain voltage is set to 7.5 [V], and as shown in FIG.
At the time point indicated by, the voltage of the liquid crystal electrode when the gate line 1 changed from selected to non-selected was measured.

Under such conditions, when the length of the low-concentration source region 13a on the source side is set to 1 μm, which is the same as the length of the low-concentration source region on the drain side, the thin film transistor may be self-aligned and small. First, as shown by the curve S1 in FIG. 2, the voltage of the liquid crystal electrode is the data signal voltage of the drain line 2 during the selected period 1
1.5 [V], but 11.57 when unselected
It is shown that the voltage rises to around [V] and that switching noise is generated.

However, if the length of the low-concentration source region 13a of the thin film transistor 10 is 3 μm, the voltage of the liquid crystal electrode is 11.56 [V] even if it is not selected, as shown by the curve S2 in FIG. If the voltage rises only to the following voltage and the length of the low concentration source region 13a is 5 μm, the voltage of the liquid crystal electrode is as shown by the curve S3 in FIG.
Even if it is not selected, the voltage rises only up to 11.55 [V] or less.

As described above, the length of the low concentration source region 13a of the thin film transistor 10 is set to the low concentration drain region 13c.
When the selection is changed to the non-selection, the increase in the voltage of the liquid crystal electrode can be suppressed and the switching noise can be reduced as the length becomes longer than the length. As a result, the display performance of the liquid crystal can be improved and the image quality can be improved.

FIG. 3 is a diagram showing another embodiment of the thin film transistor of the present invention.

This embodiment is applied to a thin film transistor similar to the embodiment shown in FIG. 1, and in order to make the parasitic resistance on the source side larger than the parasitic resistance on the drain side, the semiconductor of the thin film transistor. This is done by making the amount of impurities diffused into the source region of the layer smaller than the amount of impurities diffused into the drain region.

Therefore, in the description of this embodiment, the same components as those of the thin film transistor of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 3, the thin film transistor 20 is
Similar to the thin film transistor 10 of the above-described embodiment, the insulating film 12 is formed on the glass substrate 11, and the semiconductor layer 21 is stacked on the insulating film 12.

On the source electrode 14 side of the semiconductor layer 21, a low-concentration source region 21a in which a P-type impurity is divided into low concentration and high concentration and diffused by doping or the like.
(Figure 3 P ^- displayed) and heavily doped source region 21b (Figure 3
(Indicated by P ⁺ inside) is a low-concentration drain region 21c (indicated by P ⁻ in FIG. 3) in which a P-type impurity is divided into a low-concentration region and a high-concentration region and diffused by doping or the like on the drain electrode 15 side. ) And a high concentration drain region 21d (P ^{+ in} FIG. 1).
(Indicated by), and in the center of the channel region 13
e is formed.

The low-concentration source region 21a, the high-concentration source region 21b, the low-concentration drain region 21c and the high-concentration drain region 21d of the semiconductor layer 21 are all formed to have the same length, but the low-concentration source region is formed. 21a is
Impurities having a lower concentration than the impurity concentration of the low concentration drain region 21c are diffused.

Therefore, in the thin film transistor 20, since the impurity concentration of the low concentration source region 21a of the semiconductor layer 21 is lower than that of the low concentration drain region 21c, the source side parasitic resistance R _S becomes the drain side parasitic resistance R _D. It is a larger value. As a result, the thin film transistor 21 can be apparently made small in parasitic capacitance on the source side, and the influence of the parasitic capacitance can be reduced. Further, when the thin film transistor 20 is applied to the liquid crystal display device, the pixel capacitance 4 A source-side parasitic resistance R _S having a large resistance value is connected to the gate side, and an effect similar to that when the gate-source parasitic capacitance C _GS is increased occurs, and an AC component becomes difficult to flow. Therefore, when the thin film transistor 10 is turned off, redistribution of charges generated between the liquid crystal capacitance 4 and the gate-source parasitic capacitance C _GS can be reduced, and switching noise of the thin film transistor 10 can be reduced. As a result, the image quality can be improved.

[0052]

According to the thin film transistor of the present invention, since the parasitic resistance on the source side of the thin film transistor is set to a value larger than the parasitic resistance on the drain side, the parasitic capacitance on the source side can be apparently reduced. The effect of capacity can be reduced.

Further, according to the display device of the present invention, since the parasitic capacitance on the source side of the thin film transistor connected to the common electrode of the liquid crystal can be apparently reduced, the pixel capacitance on the liquid crystal side when the thin film transistor is turned off. It is possible to suppress the redistribution of the electric charge generated between the parasitic capacitance on the source side of the thin film transistor and the parasitic capacitance on the source side of the thin film transistor, and it is possible to reduce the noise generated by the switching of the thin film transistor. As a result, the image quality can be improved.

[Brief description of drawings]

FIG. 1 is a front sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a change state of a liquid crystal electrode voltage when a length of a low concentration source region of a thin film transistor is changed.

FIG. 3 is a front sectional view of a thin film transistor of another embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of one pixel of a matrix display device using thin film transistors as switching.

[Explanation of symbols]

10, 20 Thin film transistor 11 Glass substrate 12 Insulating film 13, 21 Semiconductor layer 13a, 21a Low concentration source region 13b, 21b High concentration source region 13c, 21c Low concentration drain region 13d, 21d High concentration drain region 13e, 21e Channel region 14 Source Electrode 15 Drain electrode 16 Gate insulating film 17 Gate electrode R _D Drain side parasitic resistance R _S Source side parasitic resistance C _GD Gate-drain parasitic capacitance C _GS Gate-source parasitic capacitance

Claims (4)

[Claims] 1. In a thin film transistor having a semiconductor layer, a source electrode, a drain electrode on a substrate and a gate electrode formed on the semiconductor layer with a gate insulating film interposed therebetween, the parasitic resistance on the source side is higher than the parasitic resistance on the drain side. A thin film transistor having a large value. 2. The length of the source region of the semiconductor layer is made longer than the length of the drain region of the semiconductor layer,
The thin film transistor according to claim 1, wherein the parasitic resistance on the source side is set to a value larger than the parasitic resistance on the drain side. 3. The source-side parasitic resistance is set to a value larger than the drain-side parasitic resistance by making the amount of impurities in the source region of the semiconductor layer smaller than the amount of impurities in the drain region of the semiconductor layer. Claim 1 characterized in that
The thin film transistor described. 4. A display device in which a drain electrode of a thin film transistor is connected to a signal line, a source electrode of the thin film transistor is connected to a common electrode of liquid crystal, and a gate electrode of the thin film transistor is connected to a gate line. A display device using the thin film transistor according to any one of claims 1 to 3.