JP3528253B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
More specifically, the present invention relates to a liquid crystal display device that drives liquid crystals while switching switching elements based on image data.

[0002]

2. Description of the Related Art As shown in FIG. 3, an active matrix type liquid crystal display device is provided with a gate line (scanning line) 1 in the row direction and a drain line (signal line) in the column direction as an equivalent circuit for each pixel. ) 2 is provided. A data signal is input to the drain line 2, and a gate voltage is selectively applied to the gate line 1 sequentially in response to horizontal scanning.

A thin film transistor (TFT) as a switching element is provided for each pixel corresponding to each intersection of the gate line 1 and the drain line 2.
3 is connected to the source electrode S of the TFT 3 and the liquid crystal capacitance CLC and the auxiliary capacitance CS are connected.

The gate electrode G of the TFT 3 is connected to the gate line 1, and the drain electrode D is connected to the drain line 2. Then, the gate electrode G of the TFT3
Generally, there is a gate-source parasitic capacitance CGS between the gate electrode and the source electrode S.

The conventional liquid crystal display device having the above structure is
As shown in FIG. 4, a gate voltage VG that alternates between VGH and VGL is applied to the gate line 1 to cause the liquid crystal capacitance CLC.
The reference voltage VCOM is applied to the common electrode, which is arranged to face the source electrode of the TFT 3 including
Is applied. Then, V is applied to the gate line 1 of the TFT3.
In the selected state in which GL is applied and turned on, the data signal voltage (drain voltage) VD having a waveform as shown in FIG. 4 is written from the drain line 2 to the liquid crystal capacitance CLC and the auxiliary capacitance CS in the form of electric charge, and another While the gate line 1 is selected, the unselected TFTs 3 are turned off, and the liquid crystal of each pixel is driven by the written charges.

FIG. 4 shows the waveforms of the gate voltage VG and the drain voltage VD when one row of the pixels arranged in a matrix is a black image and all the other rows are white images.

[0007]

However, in such a conventional liquid crystal display device, as shown in FIG. 3, there is a gate-source parasitic capacitance CGS between the gate electrode and the source electrode. Therefore, the voltage of the pixel capacitance composed of the liquid crystal capacitance CLC and the auxiliary capacitance CS at the time of driving the pixel, that is, the waveform of the source voltage VS of the TFT 3 is distorted differently from the drain voltage VD as shown in FIGS. Waveform.

FIG. 5 is a waveform diagram of the source voltage VS in the case of the p-channel MOS, and FIG. 6 is a waveform diagram of the source voltage VS in the case of the n-channel MOS. As shown in FIG. 5, the waveform of the source voltage VS is different from the drain voltage VD shown in FIG. 4 in that the rising and falling portions of the source voltage VS become gentle, and the source voltage VS shifts to the positive side by ΔVGS (n-channel MOS In the case, as shown in FIG. 6, it is attenuated on the negative side), "Low" and "High" portions.

Regarding that, for the TFT, a certain time is required for the TFT to charge the liquid crystal capacitance CLC (writing characteristic), and for the influence of the gate-source parasitic capacitance CGS, the gate voltage VG is "Low". From "to" Hig
When switching to h ", the source voltage VS rises sharply (jump characteristic). (This jump characteristic shifts to the positive side because the gate voltage VG changes from VGL to VGH in the case of p-channel MOS, In the case of an n-channel MOS, the gate voltage VG changes from VGH to VGL and shifts to the negative side.) The main cause is that the source voltage VS is attenuated by the leak current of the TFT (holding characteristic). .

Since the waveform of the source voltage VS determines the effective voltage Vrms applied to the liquid crystal, a liquid crystal display device (LCD)
Has a great influence on the optical characteristics, but especially, the component of ΔVGS in the VS waveform due to the above is the same polarity side when the drain voltage VD is positive or negative (in the case of p-channel MOS, it is positive). Side, negative side for n-channel MOS)
Therefore, the VS waveform is made asymmetric with respect to the reference voltage VCOM, and a direct current component due to the asymmetry of the VS waveform is applied to the liquid crystal to deteriorate the liquid crystal.

The above-mentioned ΔVGS is also called a jump-in voltage,
It can be expressed by the following equation.

ΔVGS = CGS (VGH−VGL) / (CS + CLC + CGS) To reduce the jump voltage ΔVGS, the electrostatic capacitance of the gate-source parasitic capacitance CGS may be reduced from the above equation.

However, due to its structure, the TFT is a thin film transistor having a self-alignment structure which can reduce the gate-source parasitic capacitance CGS.
Impurity ions diffused into the semiconductor layer using the gate electrode as a mask wrap around under the gate electrode, and an overlapping portion between the gate electrode and the n + region or p + region forming the source region of the semiconductor layer is generated. For this reason, there is a limit in reducing the gate-source parasitic capacitance CGS, and the jump voltage ΔVGS due to the jump characteristic of the source voltage VS cannot be sufficiently decreased. Therefore, the asymmetry of the source voltage VS cannot be eliminated and the liquid crystal There was a problem that deterioration could not be prevented.

The present invention has been made in view of the above problems, and suppresses the jump voltage generated by the jump characteristic of the source voltage to make the source voltage waveform symmetrical with respect to the reference voltage and to apply a DC component to the liquid crystal. It is an object of the present invention to provide a liquid crystal display device that does not easily deteriorate the liquid crystal.

[0015]

According to another aspect of the present invention, there is provided a liquid crystal display device, wherein a control voltage, which changes in an alternating manner, is applied to a gate electrode of a switching element, and a drain region is arranged at a predetermined interval via a gate insulating film. And switching the channel region between the source region, applying a voltage corresponding to display data to the pixel electrode connected to the source region side,
In a liquid crystal display device that drives and displays liquid crystal by a potential difference between the pixel electrode and a common electrode that is arranged to face the liquid crystal, the gate electrode and the source region other than the channel region of the switching element are insulated from each other. The above-mentioned object is achieved by providing a parasitic capacitance blocking electrode that is formed through a layer and has the same potential as the common electrode or the ground potential.

The parasitic capacitance blocking electrode is, for example,
As described in claim 2, the common electrode may be connected to an auxiliary capacitance electrode that is arranged opposite to the pixel electrode via an insulating layer at the same potential.

Further, for example, as described in claim 3, in the drain region and the source region of the switching element, impurities are diffused at a high concentration, and the drain region and the source region and the channel region are formed. The boundary portion of may be provided with regions in which impurities are diffused at low concentrations.

The parasitic capacitance blocking electrode is, for example,
As described in claim 4, the tip end position of the parasitic capacitance blocking electrode on the channel region side may be formed so as to cover the region where the impurities are diffused to the low concentration.

[0019]

In the liquid crystal display device according to the first aspect, a control voltage that changes in alternation is applied to the gate electrode of the switching element, switching is performed in the channel region of the switching element, and a voltage corresponding to display data is applied to the pixel electrode. A liquid crystal display device which drives a liquid crystal by a potential difference between a pixel electrode and a common electrode which is arranged to face the pixel electrode via a liquid crystal, wherein an insulating layer is provided between a gate electrode and a source region except a channel region of a switching element. A parasitic capacitance blocking electrode having the same potential as the common electrode or the ground potential is formed via the. Therefore, the parasitic capacitance blocking electrode can significantly reduce the parasitic capacitance generated between the source and gate electrodes, and since the source voltage waveform for AC driving becomes symmetrical with respect to the reference voltage, the DC component disappears, It is possible to prevent deterioration of the liquid crystal.

In the liquid crystal display device according to a second aspect of the invention, the parasitic capacitance blocking electrode is connected to an auxiliary capacitance electrode, which has the same potential as the common electrode and faces the pixel electrode via an insulating layer. . Therefore, due to the structure of the switching element, the parasitic capacitance blocking electrode can be easily formed simply by connecting to the auxiliary capacitance electrode having the same potential as the common electrode and extending the electrode, and the DC component of the AC-driven source voltage disappears. Therefore, deterioration of the liquid crystal can be prevented.

In a liquid crystal display device according to a third aspect, impurities are diffused in a high concentration in the drain region and the source region of the switching element, and a low concentration is formed at the boundary between the drain region and the source region and the channel region. A region in which impurities are diffused is provided in the concentration. Therefore, it is possible to obtain a structure in which electric field concentration is less likely to occur in the channel region.

In the liquid crystal display device according to a fourth aspect of the present invention, the tip end position of the parasitic capacitance blocking electrode on the channel region side is formed so as to cover the region where the impurities are diffused to the low concentration. Therefore, if the parasitic capacitance blocking electrode is not provided at a position covering the source-gate, a parasitic capacitance occurs, and if it covers the source-gate and further extends over the channel region, the switching operation becomes uncertain. However, since the tip position of the parasitic capacitance blocking electrode comes to the low-concentration impurity diffusion layer provided between the source region and the channel region, the generation of parasitic capacitance is minimized and the switching operation can be performed reliably. It is possible to widen the allowable range of misalignment.

[0023]

EXAMPLES The present invention will be described below based on examples.
1 and 2 are views showing an embodiment of the liquid crystal display device of the present invention. First, the configuration will be described. FIG. 1 is a cross-sectional view of a TFT arranged in each pixel of the liquid crystal display device 10 of this embodiment, and this TFT is a bottom gate p-channel TFT in which a gate electrode is provided on the substrate side. The liquid crystal display device 10 shown in FIG. 1 is used for vapor deposition, sputtering, and plasma CV.
It is formed by laminating a sheet film of D or the like.

That is, the liquid crystal display device 10 includes a thin film transistor (TFT) at a predetermined position on the glass substrate 11.
Is formed with a gate electrode G forming a part of the storage capacitor and a storage capacitor electrode 12 for generating a storage capacitor CS. The gate electrode G is connected to a gate line provided in the liquid crystal display panel, and the auxiliary capacitance electrode 12 is connected to an auxiliary capacitance line whose voltage is VCOM.

A characteristic structure of the present embodiment is that it is connected between the auxiliary capacitance electrode 12 and the source electrode S, and between the p + silicon source region 15c and the gate electrode G. The parasitic capacitance blocking electrode 13 is the insulating film 14.
It is formed to extend through. Amorphous silicon, polysilicon, single crystal silicon, etc. are used for the silicon Si of the TFT of this embodiment.

Then, the gate electrode G and the auxiliary capacitance electrode 1
2, an insulating film 14 made of silicon nitride (SiN) or silicon oxide (SiO) is formed on the entire upper surface of the glass substrate 11 including the parasitic capacitance blocking electrode 13 and corresponds to the gate electrode G and its peripheral portion. A semiconductor layer 15 forming a part of the thin film transistor is patterned and formed in a predetermined shape on the upper surface of the insulating film 14 in a portion to be formed.

A central portion of the semiconductor layer 15 corresponding to the gate electrode G is a channel region 1 made of an i-type silicon layer.
The drain region 15b and the source region 15c are formed on both left and right sides of the drain region 5a.

In this embodiment, p-type low-concentration impurity ions are diffused between the channel region 15a and the drain region 15b and the source region 15c made of p + silicon in which high-concentration impurity ions are diffused. Low concentration regions 15d and 15e made of p-silicon are provided. This structure is generally used for LDD (Lightly Dope).
d Drain) structure, which is designed to prevent electric field concentration in the channel region.

Further, when the parasitic capacitance blocking electrode 13 is formed, its tip position is accurately aligned with the position connecting the boundary position between the channel region and the source region 15c and the end portion of the gate electrode G. There was a need. However, in this embodiment, since the low-concentration regions 15d and 15e are provided, it is sufficient to perform the alignment so that the tip of the parasitic capacitance blocking electrode 13 is located in this region, and the allowable range of misalignment is widened. The generation of parasitic capacitance due to misalignment is minimized, and switching operation can be performed reliably.

Next, an interlayer insulating film 16 is formed on the upper surface of the insulating film 14 including the semiconductor layer 15. Further, on the interlayer insulating film 16, the above-mentioned auxiliary capacitance electrode 12 is formed.
And the ITO (Indi
a pixel electrode 17 made of um tin oxide) is formed.

Contact holes 18 and 19 are formed in portions of the interlayer insulating film 16 corresponding to the upper portions of the drain region 15b and the source region 15c, respectively.
A drain electrode D and a source electrode S made of aluminum and forming a part of a thin film transistor (TFT) are formed in the contact holes 18 and 19. The drain electrode D is connected to the drain line DL1 shown in FIG. 2, and the source electrode S is connected to the pixel electrode 17. Then, by the auxiliary capacitance electrode 12, the pixel electrode 17, the insulating film 14 between them, and the interlayer insulating film 16,
The auxiliary capacitance CS shown in FIG. 2 is constructed.

Further, as shown in FIG. 1, the liquid crystal display device 10 covers the pixel electrode 17, the source electrode S and the drain electrode D, and the alignment film 2 for controlling the alignment of liquid crystal molecules.
0 is formed, and the liquid crystal 21 is further arranged thereon. A common electrode made of ITO and a glass substrate (not shown) are arranged on the surface facing the liquid crystal 21. The pixel electrode 17, a common electrode provided corresponding to the pixel electrode 17, and the liquid crystal 21 between them form a liquid crystal capacitor CLC.

FIG. 2 is a circuit diagram for each pixel of the liquid crystal display device of this embodiment. As shown in FIG. 2, the liquid crystal display device of this embodiment has a gate line GL1 and a drain line DL.
A thin film transistor (TFT) 30 as a switching element is connected to each pixel corresponding to each intersection with 1. The drain electrode D of the TFT 30 is a drain line DL
1, the gate electrode G is connected to the gate line GL1, and the source electrode S is connected to the ITO of the pixel electrode 17. The source electrode S of the TFT 30 has a liquid crystal capacitance CLC for a common electrode (not shown) sandwiching the liquid crystal 21, an auxiliary capacitance CS for the auxiliary capacitance electrode 12, and the source region 15c and the parasitic capacitance blocking electrode 13 are over. Parallel capacitors are formed by the parasitic capacitances CNS caused by the wrapping, and the common voltage VCOM is applied to the common electrode, the auxiliary capacitance electrode 12 and the parasitic capacitance blocking electrode 13.

Next, the operation of this embodiment will be described. First,
To the gate line GL1 of the TFT 30 shown in FIG. 2, for example, a gate voltage VG in which the high level data VGH and the low level data VGL alternately change as shown in FIG. 4 is sequentially applied, and the TFT 30 is turned on according to the scanning timing. Then, the selected state is set. Since the TFT 30 is composed of a p-channel MOS, it is in a selected state when the gate voltage VS is the low level data VGL.

TF is connected to the drain line DL1.
According to the selection timing of T30, for example, the drain voltage VD which is display data as shown in FIG. 4 is supplied. Here, in the conventional p-channel MOS TFT, as shown in FIG. 3, when the gate is turned on at a predetermined timing and the drain voltage VD is supplied from the drain line 2, the pixel capacitance composed of the liquid crystal capacitance CLC and the auxiliary capacitance CS. , The waveform of the source voltage VS of the TFT3 is
Since it has a gate-source parasitic capacitance CGS,
Unlike the drain voltage VD, the jump voltage ΔVGS is shifted to the positive side as shown in FIG.
It shifts to the negative side by ΔVGS like).

The above jump voltage .DELTA.VGS is .DELTA.VGS = CGS (VGH-VGL) / (CS + CLC + CG) using the ON / OFF voltage VGL and VGH of the gate pulse.
It can be represented by S). Here, since the parasitic capacitance CGS is the sum of the parasitic capacitance CGS1 from the channel portion and the parasitic capacitance CGS2 between the gate and the source, the above equation is ΔVGS = (CGS1
+ CGS2) (VGH-VGL) / (CS + CLC + CGS1 + CGS
2) can be expressed as

In this embodiment, the parasitic capacitance CGS in the above equation is
Or the sum of the capacitances of the denominators of the above equations is reduced to reduce the jump voltage ΔVGS of the source voltage VS to reduce the DC voltage component and prevent deterioration of the liquid crystal. .

Specifically, as shown in FIG. 1, a parasitic capacitance blocking electrode 13 having the same potential as the reference voltage VCOM is formed in the insulating film 14 between the gate electrode G and the source region 15c made of p + silicon. It is provided.

In this structure, since the parasitic capacitance blocking electrode 13 serves as a barrier, the parasitic capacitance CGS2 = 0 due to the overlap between the gate electrode and the source region. Therefore,
In the equivalent circuit shown in FIG. 2, the jump voltage ΔVGS is ΔVGS
= CGS1 (VGH-VGL) / (CS + CLC + CGS1 + CNS)
Can be expressed as

Parasitic capacitance C from the channel portion in the above equation
GS1 has a parasitic capacitance CGS2 = 0 compared to the above CGS.
Therefore, there is a relationship of CGS1 <CGS, which is extremely small. Further, the parasitic capacitance CNS in the above equation has a relationship of CNS> CGS as compared with the above parasitic capacitance CGS, and acts in the direction of increasing the denominator of the above equation, so the jump voltage ΔVGS
Can be made smaller.

Here, the parasitic capacitance C shown in the equivalent circuit of FIG.
Since NG is a capacitance generated between the gate electrode G and the common electrode, it hardly affects the source voltage VS. On the other hand, the parasitic capacitance CNS has a large capacitance per se, but acts to improve the retention characteristic of reducing the discharge of the charges to be retained during one frame (or one field) period.

Thus, in this embodiment, the jump voltage Δ
Since VGS can be made much smaller than that of the conventional example, the ΔVGS component of the source voltage VS shown in FIGS. 5 and 6 becomes small, and the DC voltage is reduced as the asymmetry of the source voltage VS waveform with respect to the reference voltage VCOM is reduced. The components are reduced, and deterioration of the liquid crystal can be prevented.

The parasitic capacitance blocking electrode 13 described above is
In the present embodiment, the auxiliary capacitance electrode 12 was connected, but the connection target is not limited to this.
Even if the value is other than 2, if the connection is made so that the reference voltage VCOM is applied, the same advantageous effects as those of the above-described embodiment can be obtained.

In the TFT of the above embodiment, the p-channel type MOS is mainly used, but the n-channel type MOS can of course be used in the same manner. However, in this case, the gate voltage V which is the driving condition of the gate
Since GL and VGH are reversed, it is necessary to invert the gate pulse waveform.

Further, the structure of the TFT in the present invention is as follows.
The structure is not limited to the bottom gate type described above, and any structure other than the above may be used as long as an electrode (parasitic capacitance blocking electrode 13) for flowing the waveform of the reference voltage VCOM is provided in the insulating film near the source electrode. Good.

[0046]

According to the liquid crystal display device of the first aspect,
A parasitic capacitance blocking electrode having the same potential as the common electrode is formed between the gate electrode and the source electrode except the channel region of the switching element via an insulating layer. Therefore, the parasitic capacitance generated between the source and gate electrodes is significantly reduced, the source voltage waveform for AC driving becomes symmetrical with respect to the reference voltage, the DC component is removed, and deterioration of the liquid crystal can be prevented. .

According to another aspect of the liquid crystal display device of the present invention, the parasitic capacitance blocking electrode is connected to an auxiliary capacitance electrode that is arranged at the same potential as the common electrode and faces the pixel electrode via an insulating layer. Therefore, the parasitic capacitance blocking electrode can be easily formed only by extending the parasitic capacitance blocking electrode from the auxiliary capacitance electrode having the same potential as the common electrode, and the deterioration of the liquid crystal can be prevented.

According to the liquid crystal display device of the third aspect, since the regions where the low-concentration impurities are diffused are provided at the boundaries between the drain region and the source region of the switching element and the channel region, respectively, the above effects can be obtained. In addition, electric field concentration in the channel region can be alleviated.

According to the liquid crystal display device of the fourth aspect, since the tip end position of the parasitic capacitance blocking electrode on the channel region side is formed so as to cover the region where the impurities are diffused to the low concentration, the parasitic capacitance The generation can be minimized, the switching operation can be performed reliably, and the allowable range of misalignment when forming the parasitic capacitance blocking electrode can be widened.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a TFT arranged in each pixel of a liquid crystal display device of this embodiment.

FIG. 2 is a circuit diagram of each pixel of the liquid crystal display device of the present embodiment.

FIG. 3 is a circuit diagram of each pixel of a conventional liquid crystal display device.

FIG. 4 is a diagram showing drive voltage waveforms of a liquid crystal drive device.

FIG. 5 is a waveform diagram of a source voltage VS in the case of a p-channel MOS.

FIG. 6 is a waveform diagram of a source voltage VS in the case of an n-channel MOS.

[Explanation of symbols]

10 Liquid crystal display device 11 glass substrate 12 Storage capacitor electrode 13 Parasitic capacitance blocking electrode 14 Insulation layer 15 Semiconductor layer 16 Interlayer insulation film 17 pixel electrodes 18 contact holes 19 contact holes 20 Alignment film 21 liquid crystal

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/133 550 G09G 3/36

Claims (4)

(57) [Claims] 1. A switching element is applied with a control voltage, which changes in an alternating manner, to switch a channel region between a drain region and a source region, which are arranged at a predetermined distance through a gate insulating film, to switch the channel region. A liquid crystal display device in which a voltage corresponding to display data is applied to a pixel electrode connected to a source region side, and the liquid crystal is driven by a potential difference between the pixel electrode and a common electrode which is arranged to face the liquid crystal via a liquid crystal. In the above, a parasitic capacitance blocking electrode formed between the gate electrode and the source region excluding the channel region of the switching element via an insulating layer and having the same potential as the common electrode or a ground potential is provided. Liquid crystal display device. 2. The parasitic capacitance blocking electrode is connected to an auxiliary capacitance electrode, which has the same potential as the common electrode and is opposed to the pixel electrode via an insulating layer. 1. The liquid crystal display device according to 1. 3. The drain region and the source region of the switching element are highly diffused with impurities, and the boundary regions between the drain region and the source region and the channel region are respectively doped with low concentration impurities. The liquid crystal display device according to claim 1, further comprising a diffused region. 4. The parasitic capacitance blocking electrode is formed so that the tip end of the parasitic capacitance blocking electrode on the channel region side is in the region where the impurities are diffused to the low concentration. The described liquid crystal display device.