JPH07176702A - Dynamic random access memory and its testing method - Google Patents

Abstract

PURPOSE:To prevent the deterioration in data-hold time and improve the reliability in memory device even after long-time strict test. CONSTITUTION:A self-refresh mode starts for a device at first. A test of self- refresh time (tREF) is carried out in the self-refresh mode. The device is recognized as a no-good one in the case of 'FALL', or as a good one in 'PASS', while a self-refresh time (P1) is measured only for the good device. In addition, the refresh time (tREF) is measured in a normal mode. Thus the device is taken as a no-good one in 'FALL', or the device is taken as a good one in 'PASS' when the device passes the test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory device and its inspection method.

[0002]

2. Description of the Related Art Recently, the use of dynamic random access memory devices (hereinafter referred to as DRAM) has increased,
In particular, there is an increasing demand for a DRAM having a long data retention time and a long refresh time in consideration of battery backup and a DRAM having a self-refresh function. Here, DRA equipped with the conventional self-refresh function
M and its inspection method and manufacturing method will be described. First, the features of DRAM will be briefly described. DRAM
Stores data by accumulating charges in the memory cell capacitance, and reads the charges accumulated in the memory cell capacitance when reading data. The charges accumulated in the memory cell capacitance leak as time passes and the amount of charges decreases, and after a certain period of time, the data cannot be read accurately. Therefore, it is necessary to perform the operation of retaining the electric charge after a certain period of time. The operation of holding this charge is called a refresh operation. Normally, an external control signal must be input to perform this refresh operation. The self-refresh function is a function of performing a refresh operation by an internal control signal internally generated by DRAM without inputting an external control signal. In the refresh operation including the self-refresh function, the charge accumulated in the memory cell capacitance is amplified by the operation of the sense amplifier and the data is retained by rewriting, so that a large amount of current flows due to the operation of the sense amplifier and the corresponding amount of power is consumed. It Therefore, if the data retention time is long and the refresh cycle time is long, the power consumption can be reduced, which is particularly advantageous at the time of battery backup.

FIG. 11 shows an example of the timing for realizing the self-refresh function. FIG. 12 shows a conventional self-refresh function inspection method.

First, with reference to FIG. 11, the timing for providing the self-refresh function will be described. / RA
S (Row addres strobe), / CAS (Column addres strob)
e) is an external control signal, / RG0 is an internal control signal, P12 or P
13 indicates the period, and P12 is the refresh cycle time. As shown in the figure, / CAS is set to the logic voltage "L" and then / RAS is set to the logic voltage "L". Hold / RAS at logic voltage "L",
After a while, while / RAS is held at the logic voltage "L", the internal control signal / RG0 becomes a signal that generates one pulse signal from the logic voltage "H" to the logic voltage "L" in the cycle of the period P12. . The self-refresh operation is performed using the internal control signal / RG0 as a refresh signal.

Next, FIG. 12 illustrates a conventional self-refresh function inspection method. P12 is the refresh cycle period described above, tREF is the refresh time that is the data retention time of the memory cells, n is the minimum number of refresh times required to refresh all memory cells, FAIL is the failure of the inspection, PASS Indicates that the inspection has been passed. In the case of self-refresh with the timing shown in FIG. 11, the refresh time tREF is tREF.
= P12 × n. According to the conventional self-refresh function inspection method, all memory cells are normally refreshed at a refresh time tREF (tREF = P12 × n) which is actually entered in the self-refresh mode at the timing shown in FIG. 11 and determined by the internal control signal / RG0. It is to check whether it can be done. To perform this check, refresh time tREF (tREF = P12 ×
If the self-refresh function is not operating normally for a longer period than n), the data in the memory cell cannot be held and the malfunction time is held to check whether the memory cell operates normally.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the AM, the inspection method, and the manufacturing method, in the self-refresh function inspection, only the data retention time at the refresh time tREF determined by the internal control signal during the self-refresh function can be inspected. In addition, since the data retention time deteriorates during long-term use, strict inspections with sufficient margin have not been performed. Therefore, there is a problem that the semiconductor device may become defective during long-time use and the reliability of the semiconductor device may be lowered.

In view of the above problems, the present invention provides a dynamic random access memory device and a method for testing the same, which does not deteriorate the data retention time and can secure the reliability of the semiconductor device even after long-term use due to strict inspection. The purpose is to provide.

[0008]

In order to solve the above problems, a dynamic random access memory device of the present invention has a data retention function by self-data rewriting, and a self-refresh cycle of a standard self-refresh function. An external control signal sets a self-refresh function that provides a self-refresh cycle time longer than the time.

Further, a self-refresh cycle time switching circuit for changing the self-refresh cycle time is provided, and the self-refresh cycle time is measured by comparing the measured self-refresh cycle time with the actual value of the data retention time. Switch to a self-refresh cycle shorter than the refresh cycle.

Further, a redundant memory cell is provided, and a memory cell which is defective in the self-refresh function inspection having a self-refresh cycle time longer than the self-refresh cycle time of the self-refresh function of the standard is replaced with the redundant memory cell.

In order to solve the above-mentioned problems, the dynamic random access memory device inspection method of the present invention provides a self-refresh cycle time of a dynamic random access memory device having a data retention function by self-data rewriting. The measurement is performed, and the refresh time of the data retention time which is a constant multiple of the self-refresh cycle time is tested.

Further, the self-refresh cycle time is measured by comparing the self-refresh current with the RAS-only refresh current.

[0013]

According to the DRAM, the inspection method and the manufacturing method of the present invention, since a strict inspection can be performed with respect to the refresh time during the self-refresh function, a highly reliable semiconductor device can be obtained. The non-defective rate of the self-refresh function can be increased by the manufacturing method in which the memory cell is replaced with the redundant memory cell.

[0014]

EXAMPLES The present invention will be described below with reference to examples.

First, as a first embodiment of the present invention, a DRAM testing method for testing a refresh time of a data holding time which is a constant multiple of the self-refresh cycle time will be described with reference to the flow chart of FIG. The period P1 is the self-refresh cycle time, tREF is the refresh time which is the data retention time of the memory cells, α is a constant, and n is the minimum number of refresh times required to refresh all the memory cells. First, from the start of inspection, the self-refresh mode is entered and the self-refresh time tREF (tREF = P1 x
n) is inspected, it is determined as a defective product that fails (hereinafter referred to as FAIL), and for those that pass (hereinafter referred to as PASS), the self-refresh cycle time P1 is measured, and then in the normal mode. Refresh time tREF (tREF = α × P1
Xn: α> 1) is inspected. In this way, if the product fails, the product is regarded as a defective product, and the product that has passed is regarded as a good product and the inspection is completed. The feature of this inspection method is that it can perform a strict inspection on the refresh time during the self-refresh function, so it can be operated even if the refresh time, which is the data retention time, becomes a little shorter during long-term use. You can Therefore, a highly reliable semiconductor device can be obtained.

Next, a DRAM inspection method for measuring the self-refresh cycle time will be described with reference to FIGS. First, at the timing when the self-refresh function in FIG.
addres strobe), / CAS (Column addres strobe) are external control signals, / RG0 is an internal control signal, P1 and P2 are periods, and P1 is a refresh cycle time. As shown / CA
After setting S to logic voltage "L", / RAS is set to logic voltage "L", / RAS is held at logic voltage "L", and after a while / R
While holding AS at logic voltage "L", internal control signal /
RG0 becomes a signal that generates one pulse signal of logic voltage "L" from logic voltage "H" in the cycle of period P1. This internal control signal / RGO is used as a refresh signal to perform a self refresh operation. And the period P2
Current at that time (self-refresh current: ICCSEL
F) is measured. Next, Fig. 3 shows ROR (RAS only
At the timing of the refresh function, the / RAS (Ro
w address strobe), / CAS (Column addres strobe)
Is an external control signal, / RG0 is an internal control signal, and P3 to P5 are periods. As shown in the figure, when / CAS is in the logic voltage "H" and / RAS signal is input in the cycle of period P3, one pulse signal of logic voltage "H" to logic voltage "L" is input, and it follows it The control signal / RG0 also generates one pulse signal of the logic voltage "L" from the logic voltage "H" in the cycle of the period P4. Here, the period P3 and the period P4 are substantially equal. Then, in the period P5, the current at that time (ROR current: ICCROR) is measured. Usually, a large amount of current flows during the refresh operation, and the current value is determined by the cycle of the refresh operation. By utilizing this, the cycle of the period P3 of the signal / RAS can be obtained so that the self-refresh current during the self-refresh function operation and the ROR current during the ROR function operation become equal. In this way, internal control signal / RG0 during self-refresh function operation
The test method for measuring the refresh signal of 1 as the self-refresh cycle time is the test method for measuring the self-refresh cycle time according to the present invention. FIG. 4 is a flow of the above inspection method. A flow chart of this inspection method will be described. First, from the start of inspection, the self-refresh mode is entered and the self-refresh current (ICCSELF) is measured. Next, in the period P3, the ROR mode is entered, and the ROR current (ICC
ROR) is measured. Here, the self-refresh current (ICCSELF) measured previously and the ROR current (ICCROR) are compared, and if these values are not equal, the period P3 is P3 × ICCROR ÷
Set to the value of ICCSELF. In this period P3, the ROR mode is entered, the ROR current (ICCROR) is measured, the self refresh current (ICCSELF) and the ROR current (ICCROR) are compared, and the same operation is repeated. If these values are almost equal then the period
The inspection is completed by setting P3 to the self-refresh cycle time P1. When self-refresh current (ICCSELF) and ROR current (ICCROR) are not equal, cycle P3 is P3 × ICCROR ÷ ICCS
I set the value of ELF and repeated the same thing, ICCRO
This is because there is a relationship of R × P3 = ICCSELF × P1. The feature of this inspection method is that the self-refresh cycle time of the internal circuit can be measured only by the operation by the external control signal.

Next, as a second embodiment of the present invention, the first
A method of manufacturing a DRAM in which a memory cell that becomes defective in the inspection by the inspection method of the embodiment is replaced with a redundant memory cell will be described. FIG. 5 is a flow chart of an inspection method for this manufacturing method. Period P1 is the self-refresh cycle time,
tREF is a refresh time which is a data retention time of the memory cells, α is a constant, and n is the minimum number of refreshes required for refreshing all the memory cells. First,
Measure the self-refresh cycle time P1 from the start of the inspection,
Next, in the normal mode, the refresh time tREF (tREF = α ×
Inspect P1 × n: α> 1). If FAIL, redundant repair judgment is performed, and if FAIL is further determined to be defective. If the result is PASS in the redundancy repair determination, the redundancy repair address is stored and the refresh time tREF (tREF = α × P1 ×
n: α> 1), the self-refresh mode is entered with the PASS product and the self-refresh time tREF (tREF =
Check P1 × n). If FAIL, the product is considered defective and PASS
The products that have been tested are considered to be non-defective and the inspection is completed. This inspection method is characterized in that a strict inspection is performed for the refresh time during the self-refresh function and the defective memory cell is replaced with a redundant memory cell to repair the device, and the device is as highly reliable as in the first embodiment. It is possible to increase the non-defective rate of the self-refresh function.

Next, as a third embodiment of the present invention, in a DRAM having a self-refresh cycle time switching circuit for changing the cycle of self-refresh,
A manufacturing method for switching to a short self-refresh cycle by comparing the self-refresh cycle time measured by the inspection method of the present invention and the actual value of the data retention time (refresh time) will be described. FIG. 6 is a flow chart of an inspection method for this manufacturing method. The period P1 is the self-refresh cycle time, and the period P1 'is P1'<switched by the self-refresh cycle time switching circuit.
PREF is the self-refresh cycle time, tREFeff is the actual value of the refresh time that is the data retention time of the memory cells, α is a constant, and n is the minimum number of refresh times required to refresh all the memory cells. First, the actual value tREFeff of the refresh time is measured from the start of the inspection, and then the self-refresh cycle time P1 is measured by the method of the first embodiment. Refresh time capability tREFeff
And α × P1 × n (α> 1) are compared, and tREFeff ≧ α × P1 ×
If n, the inspection is terminated. If tREFeff <α × P1 × n, the self-refresh cycle time P1 is shortened to P1 ′ (P1 ′ <P1) and the inspection is terminated. A feature of the manufacturing method of switching to the self-refresh cycle by this inspection is that the self-refresh cycle can be switched to a shorter self-refresh cycle than the refresh time that is strict with respect to the refresh time in the self-refresh function.

Next, as a fourth embodiment of the present invention, a self-refresh cycle longer than the self-refresh cycle time of the self-refresh function (hereinafter referred to as standard self-refresh cycle) disclosed in product specifications or product standards. A DRAM having a self-refresh test function in which the cycle time can be set will be described with reference to FIGS. First, at the timing for the standard self-refresh function in Figure 7, / RAS (Row addre
s strobe), / CAS (Column addres strobe), / WE (W
rite enable) is an external control signal, / RG0 is an internal control signal,
P6 to P8 are periods, period P6 is a refresh cycle time in the self-refresh function, period P7 is a timing period for entering the self-refresh function, and period P8 is a self-refresh function period. As shown in the figure, / CAS is a logic voltage "L"
After that, / RAS is set to the logic voltage "L" while / WE is the logic voltage "H". Hold / RAS at logic voltage "L". While holding / RAS at logic voltage "L", internal control signal / RG0 is logic voltage "H" in the cycle of period P6.
Then, one pulse signal of logic voltage "L" is generated. This internal control signal / RG0 is used as a refresh signal to perform a self refresh operation.
Next, at the timing when the self-refresh test function is shown in FIG. 8, / RAS (Row addres strobe), / CAS
(Column addres strobe), / WE (Write enable) is an external control signal, / RG0 is an internal control signal, P9 to P11 are periods, period P9 is a refresh cycle time during the self-refresh function, and period P10 is the self-refresh function. The timing period, period P11, is the self-refresh test function period. As shown in the figure, after / CAS is set to the logical voltage "L", / RAS is set to the logical voltage "L" while / WE is set to the logical voltage "L", and / RAS is held at the logical voltage "L". / RAS
Control signal / RG while holding at logic voltage "L"
0 is a signal in which one pulse signal of logic voltage "H" to logic voltage "L" is generated in the cycle of the period P9. This internal control signal / RG0 is used as a refresh signal to perform a self refresh operation. Here, the refresh cycle time of the period P9 of the self-refresh test function is designed to be longer than the refresh cycle time of the period P6 of the standard self-refresh function. The self-refresh test function having a refresh cycle time longer than that of the standard self-refresh function checks the refresh time of the standard self-refresh function with a stricter refresh time as shown in the fifth embodiment of the present invention. In addition to this purpose, this self-refresh test function can be used as a product for ultra-low power consumption as a second standard self-refresh function having a longer refresh cycle time.

Next, as a fifth embodiment of the present invention, a fourth embodiment
An inspection method using the self-refresh test function of the embodiment will be described. FIG. 9 is a flow chart of this inspection method. A period P9 is a refresh cycle time in the self-refresh test function, tREF is a refresh time which is a data holding time of the memory cells, and n is a minimum number of refresh times required for refreshing all the memory cells. From the start of the inspection, the refresh time tREF (tREF = P9 × n) is inspected in the self-refresh test mode, and if PASS, it is judged as a good product, and if FAIL, it is judged as a defective product and the inspection is completed. In this way, the self-refresh function makes it possible to easily inspect a refresh time that is longer than the standard self-refresh function, so it operates even if the refresh time, which is the data retention time, becomes a little shorter during long-term use. That is, it can be a highly reliable device.

Next, as a sixth embodiment of the present invention, a fourth embodiment
A method of manufacturing a DRAM in which a memory cell that becomes defective in the inspection using the self-refresh test function of the above embodiment is replaced with a redundant memory cell will be described. FIG. 10 is a flow chart of an inspection method for this manufacturing method. The period P9 is the refresh cycle time in the self-refresh test function, tREF is the refresh time which is the data retention time of the memory cells, and n is the minimum number of refresh times required to refresh all the memory cells. First, from the start of the inspection, the refresh time tREF (tREF = P9 × n) is inspected in the self-refresh test mode. If FAIL, a redundant repair judgment is made, and if FAIL, a defective product is determined. If PASS is passed in the redundant repair determination, the redundant repair address is stored, and the inspection is completed with the PASS product in the inspection of the refresh time tREF (tREF = P9 × n) in the self-refresh test mode as described above. This inspection method is characterized in that the self-refresh test function makes it possible to easily perform a strict inspection for the refresh time in the standard self-refresh function, and replaces the defective memory cell with a redundant memory cell for repair. Similar to the fifth embodiment, it is possible to make the device highly reliable and increase the non-defective rate of the self-refresh function.

[0022]

According to the present invention, it is possible to increase the rate of non-defective products of self-refresh function products and to provide a highly reliable semiconductor device of self-refresh function products.

[Brief description of drawings]

FIG. 1 is a diagram showing an inspection method for measuring a self-refresh cycle time of a dynamic random access memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing another inspection method for measuring the self-refresh cycle time of the dynamic random access memory device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing another inspection method for measuring the self-refresh cycle time of the dynamic random access memory device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a method for inspecting a self-refresh function product of the dynamic random access memory device according to the first embodiment of the present invention.

FIG. 5 is a flow chart of a method for inspecting a self-refresh function product of a dynamic random access memory device according to a second embodiment of the present invention.

FIG. 6 is an operation flow chart of a dynamic random access memory device having a self-refresh cycle time switching circuit according to a third embodiment of the present invention.

FIG. 7 is a timing diagram of the self-refresh test function of the fourth embodiment of the present invention.

FIG. 8 is a timing diagram of the self-refresh test function of the fourth embodiment of the present invention.

FIG. 9 is a flow chart of an inspection method using a self-refresh test function according to a fifth embodiment of the present invention.

FIG. 10 is a flow chart of a self-refresh function product by the self-refresh test function of the sixth embodiment of the present invention.

FIG. 11 is a timing diagram of a conventional self-refresh test function.

FIG. 12 is a flowchart of a conventional self-refresh function inspection method.

[Explanation of symbols]

 P1 period tREF Refresh time α constant n Refresh count FAIL Defective product PASS Good product

Claims (5)

[Claims] 1. A self-refresh function having a data holding function by self-data rewriting and having a self-refresh cycle time longer than a self-refresh cycle time of a standard self-refresh function is set by an external control signal. Dynamic random access memory device. 2. A self-refresh cycle time switching circuit for changing the cycle time of the self-refresh, the self-refresh cycle time is measured by comparing the measured self-refresh cycle time with the actual value of the data retention time. 2. The dynamic random access memory device according to claim 1, wherein the self-refresh cycle is shorter than the refresh cycle. 3. A redundant memory cell is provided for replacing a defective memory cell in a self-refresh function inspection having a self-refresh cycle time longer than the self-refresh cycle time of the self-refresh function of the standard with the redundant memory cell. The dynamic random access memory device according to claim 1, wherein the random random access memory device is a memory device. 4. A refresh time test for measuring a self-refresh cycle time of a dynamic random access memory device having a data hold function by self-data rewriting, and a refresh time of a data hold time which is a constant multiple of the self-refresh cycle time. A method for inspecting a dynamic random access memory device, which is characterized by being performed. 5. The dynamic random access memory device according to claim 4, wherein the self refresh cycle time is measured by comparing a self refresh current and a RAS only refresh current.