CN116168759B - Self-refresh power consumption analysis method for semiconductor memory device - Google Patents
Self-refresh power consumption analysis method for semiconductor memory device Download PDFInfo
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Abstract
The disclosure provides a self-refresh power consumption analysis method of a semiconductor memory device, and relates to the technical field of semiconductors. The semiconductor memory device includes a memory array arranged in rows and columns. The method comprises the following steps: the method comprises the steps that when the semiconductor memory device is in a refresh mode, the total number of times of sending the refresh command after refreshing the memory array is obtained through testing, and the total number of times of sending the refresh command after refreshing the memory array in the self-refresh mode is taken as the total number of times of sending the refresh command after refreshing the memory array by the semiconductor memory device; when the semiconductor memory device is in the self-refresh mode, the self-refresh total duration of the memory array after the refresh is obtained by testing, and according to the total number of times of sending the refresh command and the self-refresh total duration, the analysis result of the self-refresh power consumption of the semiconductor memory device in the self-refresh mode is obtained, and the parameters affecting the self-refresh power consumption can be accurately analyzed and adjusted so as to reduce the self-refresh power consumption.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a self-refresh power consumption analysis method of a semiconductor memory device.
Background
The semiconductor memory device has a leakage phenomenon due to the device characteristics, so that the amount of charge stored in the capacitor changes with the leakage phenomenon, resulting in the disappearance of stored data over time. Thus, the stored charge needs to be refreshed to retain the data.
Refresh causes additional power consumption and delays memory access, resulting in reduced performance, and as the capacity of semiconductor memory devices increases, the time required for refresh increases, resulting in additional power consumption for refresh becoming non-negligible.
Disclosure of Invention
The present disclosure is directed to a self-refresh power consumption analysis method of a semiconductor memory device, which can accurately analyze and adjust parameters affecting self-refresh power consumption to reduce self-refresh power consumption.
The embodiment of the disclosure provides a self-refresh power consumption analysis method of a semiconductor memory device, which comprises a memory array arranged according to rows and columns. Wherein the method comprises the following steps: when the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command after refreshing the memory array, wherein the total number of times of sending the refresh command after refreshing the memory array in the self-refresh mode is taken as the total number of times of sending the refresh command after refreshing the memory array by the semiconductor memory device; when the semiconductor memory device is in the self-refresh mode, testing to obtain the total self-refresh time length after refreshing the memory array; and according to the total number of times of sending the refresh command and the total self-refresh duration, obtaining an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode.
In some exemplary embodiments of the present disclosure, the target row is included in the storage array. When the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command after refreshing the memory array, wherein the method comprises the following steps: testing and obtaining the refresh command times of refreshing the semiconductor memory device to the target row after the semiconductor memory device is powered on; and obtaining the total sending times of the refresh command according to the refresh command times test.
In some exemplary embodiments of the present disclosure, testing the number of refresh commands to refresh the target row after powering up the semiconductor memory device includes:
s31, writing first test data into the target row;
s32, sending a refresh command to the semiconductor memory device once;
s33, waiting a first time period to enable the semiconductor memory device to be in an idle state;
s34, sending n1 times of refreshing commands to the semiconductor storage device, wherein n1 is a positive integer greater than or equal to 1;
s35, waiting for a second time period to enable the semiconductor memory device to be in an idle state;
s36, reading first response data from the target row;
s37, judging whether a first test result of the target row is test passing or not according to the first test data and the first response data, if the first test result is test failing, increasing n1 according to a first preset step length, and repeatedly executing S31-S36 until the first test result is test passing;
S38, recording the refresh command frequency of n1+1 when the first test result is that the test passes;
wherein the first duration and the second duration are both less than the data retention time of the target row, and the sum of the first duration and the second duration is greater than the data retention time of the target row.
In some exemplary embodiments of the present disclosure, testing the number of refresh commands to refresh the target row after powering up the semiconductor memory device includes:
s41, writing first test data into the target row;
s42, waiting a first time period to enable the semiconductor memory device to be in an idle state;
s43, sending n1 times of refresh commands to the semiconductor storage device, wherein n1 is a positive integer greater than or equal to 1;
s44, waiting a second time period to enable the semiconductor memory device to be in an idle state;
s45, reading first response data from the target row;
s46, judging whether a first test result of the target row is test passing or not according to the first test data and the first response data, if the first test result is test failing, increasing n1 according to a first preset step length, and repeatedly executing S41-S46 until the first test result is test passing;
S47, recording the refresh command frequency n1 when the first test result is that the test passes;
wherein the first duration and the second duration are both less than the data retention time of the target row, and the sum of the first duration and the second duration is greater than the data retention time of the target row.
In some exemplary embodiments of the present disclosure, further comprising:
testing to obtain the data retention time of the target row.
In some exemplary embodiments of the present disclosure, testing the data retention time to obtain the target row includes:
s61, writing second test data into the target row;
s62, waiting for a preset time period to enable the semiconductor memory device to be in an idle state;
s63, reading second response data from the target row;
s64, judging whether a second test result of the target row is test passing or not according to the second test data and the second response data, if the second test result is test passing, increasing the preset time length according to a second preset step length, and repeatedly executing S61-S64 until the second test result is test failing;
s65, recording the preset time length when the second test result is that the test fails as the data retention time of the target row.
In some exemplary embodiments of the present disclosure, obtaining the total number of refresh command transmissions according to the refresh command number test includes:
s71, writing third test data into the target row;
s72, sending the refresh command of the refresh command times to the semiconductor storage device;
s73, waiting a third time period to enable the semiconductor memory device to be in an idle state;
s74, sending n2 refresh commands to the semiconductor storage device, wherein n2 is a positive integer greater than or equal to 1;
s75, waiting for a fourth time period to enable the semiconductor memory device to be in an idle state;
s76, reading third response data from the target row;
s77, judging whether a third test result of the target row is test passing or not according to the third test data and the third response data, if the third test result is test failing, increasing n2 according to a third preset step length, and repeatedly executing S71-S76 until the third test result is test passing;
s78, recording the total number of times of sending the refresh command when the third test result is that the test passes is n2;
wherein the third duration and the fourth duration are both less than the data retention time of the target row, and the sum of the third duration and the fourth duration is greater than the data retention time of the target row.
In some exemplary embodiments of the present disclosure, testing for a total self-refresh duration to refresh the memory array when the semiconductor memory device is in the self-refresh mode includes:
s81, writing fourth test data into the target row;
s82, sending the refresh command of the refresh command times to the semiconductor storage device;
s83, waiting for a fifth time period to enable the semiconductor memory device to be in an idle state;
s84, enabling the semiconductor memory device to be in the self-refresh mode in self-refresh time;
s85, waiting a sixth time period to enable the semiconductor memory device to be in an idle state;
s86, reading fourth response data from the target row;
s87, judging whether a fourth test result of the target row is test passing or not according to the fourth test data and the fourth response data, if the fourth test result is test failing, increasing the self-refresh time according to a fourth preset step length, and repeatedly executing S81-S87 until the fourth test result is test passing;
s88, recording the self-refreshing time of the fourth test result when the test passes as the self-refreshing total duration;
wherein the fifth time period and the sixth time period are both smaller than the data holding time of the target row, and the sum of the fifth time period and the sixth time period is larger than the data holding time of the target row.
In some exemplary embodiments of the present disclosure, causing the semiconductor memory apparatus to be in the self-refresh mode for a self-refresh time includes:
s841. sending a self-refresh entry command to the semiconductor memory device to control the semiconductor memory device to enter the self-refresh mode;
s842. placing the semiconductor memory device in the self-refresh mode during the self-refresh time;
s843. sending a self-refresh exit command to the semiconductor memory device to control the semiconductor memory device to exit the self-refresh mode.
In some exemplary embodiments of the present disclosure, obtaining an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode according to the total number of times of refresh command transmission and the total self-refresh duration includes: obtaining a total number of times of transmission of refresh commands and a total self-refresh time length of each of a plurality of semiconductor memory devices having the same capacity; detecting and obtaining self-refresh current of each semiconductor memory device in the self-refresh mode under the condition that self-refresh voltage is fixed; according to the self-refresh current of each semiconductor memory device, the obtained analysis result is that the total number of times of sending the refresh command and the total self-refresh duration are inversely related to the self-refresh power consumption.
In some exemplary embodiments of the present disclosure, the semiconductor memory apparatus has the same temperature in the refresh mode and the self-refresh mode.
In some exemplary embodiments of the present disclosure, further comprising: and obtaining the refresh command interval of the semiconductor memory device in the self-refresh mode according to the self-refresh total duration and the refresh command transmission total times.
According to another aspect of the present disclosure, there is provided a self-refresh power consumption analysis device of a semiconductor memory device including a memory array arranged in rows and columns; the self-refresh power consumption analysis device comprises a controller, wherein the controller executes the following steps: when the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command after refreshing the memory array, wherein the total number of times of sending the refresh command after refreshing the memory array in the self-refresh mode is taken as the total number of times of sending the refresh command after refreshing the memory array by the semiconductor memory device; when the semiconductor memory device is in the self-refresh mode, testing to obtain the total self-refresh time length after refreshing the memory array; and according to the total number of times of sending the refresh command and the total self-refresh duration, obtaining an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode.
According to yet another aspect of the present disclosure, there is provided a computer device comprising one or more processors; a memory configured to store one or more programs that, when executed by the one or more processors, cause the computer device to implement the self-refresh power consumption analysis method in any of the embodiments of the present disclosure.
According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium storing a computer program, characterized in that the computer program, when run on a computer, causes the computer to perform the self-refresh power consumption analysis method in any of the embodiments of the present disclosure.
According to yet another aspect of the present disclosure, there is provided a computer program product which, when executed by a processor, implements the self-refresh power consumption analysis method in any of the embodiments of the present disclosure.
According to the self-refresh power consumption analysis method of the semiconductor memory device, the semiconductor memory device comprises the memory arrays arranged according to rows and columns, when the semiconductor memory device is in a refresh mode, the total number of times of sending the refresh command for refreshing the memory arrays is obtained through testing, the total number of times of sending the refresh command for refreshing the memory arrays in the self-refresh mode is taken as the total number of times of sending the refresh command for refreshing the memory arrays in the self-refresh mode, when the semiconductor memory device is in the self-refresh mode, the total self-refresh time length for refreshing the memory arrays is obtained through testing, and according to the total number of times of sending the refresh command and the total self-refresh time length, the analysis result of the self-refresh power consumption of the semiconductor memory device in the self-refresh mode is obtained, parameters affecting the self-refresh power consumption can be accurately analyzed, and the self-refresh power consumption can be adjusted so as to reduce the self-refresh power consumption.
Drawings
Fig. 1 shows a self-refresh signal timing diagram provided by an embodiment of the present disclosure.
Fig. 2 is a schematic diagram showing a frequency relationship of a self-refresh frequency signal according to an embodiment of the present disclosure.
FIG. 3 is a schematic diagram showing the frequency relationship of self-refresh frequency signals in a DRAM according to an embodiment of the present disclosure.
Fig. 4 shows a flowchart of a self-refresh power consumption analysis method provided by an embodiment of the present disclosure.
Fig. 5 illustrates one of the flowcharts provided by the embodiments of the present disclosure for determining the number of refresh commands.
FIG. 6 illustrates a second flowchart for determining the number of refresh commands provided by an embodiment of the present disclosure.
Fig. 7 shows a flowchart of a data retention time of a test acquisition target row provided by an embodiment of the present disclosure.
Fig. 8 shows a flowchart for testing the total number of times a refresh command is sent.
FIG. 9 shows a flowchart for obtaining a total self-refresh duration in self-refresh mode provided by an embodiment of the present disclosure.
Fig. 10 is a flowchart showing a method for placing a semiconductor memory device in a self-refresh mode during a self-refresh time according to an embodiment of the present disclosure.
Fig. 11 shows a schematic diagram of a self-refresh power consumption analysis device according to an embodiment of the present disclosure.
Fig. 12 shows a schematic structural diagram of a computer device according to an embodiment of the disclosure.
Fig. 13 shows a schematic diagram of a computer-readable storage medium provided by an embodiment of the disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The semiconductor memory device has a leakage phenomenon due to the device characteristics, so that the amount of charge stored in the capacitor changes with the leakage phenomenon, resulting in the disappearance of stored data over time. Thus, the stored charge needs to be refreshed to retain the data. Refresh causes additional power consumption and delays memory access, resulting in reduced performance, and as the capacity of semiconductor memory devices increases, the time required for refresh increases, resulting in additional power consumption for refresh becoming non-negligible.
In order to accurately analyze the self-refresh power consumption to reduce the self-refresh power consumption, it is necessary to determine the self-refresh parameters, taking a semiconductor memory device as an example of a dynamic random access memory (Dynamic Random Access Memory, DRAM), but the disclosure is not limited to the type of the semiconductor memory device, and fig. 1 shows a schematic diagram of the protocol self-refresh parameters of a dynamic random access memory; wherein the refresh requirement (Refresh Requirements) may include: the number of banks per channel (Number of banks per channel), the Refresh Window (Refresh Window), the number of Refresh commands required in the Refresh Window (Required Number of REFRESH Commands in a tREFW Window), the average Refresh interval (Average Refresh Interval). Wherein the refresh window may also be referred to as a self-refresh total duration, denoted by tREFW; the number of refresh commands required in the refresh window may be referred to as the total number of refresh command transmissions (R), wherein the average refresh interval includes refreshing all banks of the chip (REFab) and refreshing specific bank pairs (per bank prefresh, REFpb), REFab being represented by the refresh command interval (tREFI).
Further, for different sizes of refresh requirements of 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, and 32Gb, the number of banks per channel is 16, the refresh window is 32ms, and the refresh command number is 8192, the average refresh interval for refreshing all banks of the chip is 3.906, and the average refresh interval for refreshing a specific bank pair is 488.
The main parameters affecting the self-refresh power consumption are the total number of times of sending the refresh command and the total self-refresh time length, so that the total number of times of sending the refresh command and the total self-refresh time length after the memory array is refreshed in the self-refresh (self refresh) mode need to be accurately determined, and the accuracy of the analysis result of analyzing the self-refresh power consumption can be improved.
However, in the related art, when the refresh Command interval for transmitting the refresh Command (refresh Command) is not uniformly spaced but fluctuates in real time after the self-refresh mode is entered in the inside of the actual semiconductor memory device, the total number of times of transmission of the refresh Command is obtained is inaccurate if the refresh Command interval for transmitting the refresh Command in the self-refresh mode is assumed to be uniformly spaced, and at the same time, the process in the inside of the semiconductor memory device is changed, and the refresh Command is transmitted once, and thus two refresh operations may be actually performed, fig. 2 shows a self-refresh signal timing chart including ck_c and ck_t as differential clock input signals, command Address signals (CA), chip Select signals (Chip Select, CS), and Command signals (Command), and T0, T1, T2, ta0, ta1, ta2, ta3, tb0, tb1, tb2, tb3, tc0, and Tc1 for 13 times.
Specifically, after issuing the full bank early warning (All Bank Precharce) command at time T0 and passing the tRPab period, a time interval is required to pass after sending the self-refresh entry command (Self Refresh Entry) at time Ta1 and before sending the self-refresh exit command (Self Refresh Exit) at time Tb1, i.e., time interval tSR in fig. 2, when the chip select signal is high; and at least some time interval has to elapse after the self-refresh exit command, i.e., time interval tXSR in fig. 2, before other commands can be issued to the memory cells. The Command address signal further includes Valid, which indicates that the Command signal is a Valid Command.
In this way, if the result of measuring the total number of times of transmission of the refresh command in the self-refresh mode is inaccurate, there may occur a case where the measured total number of times of transmission of the refresh command is doubled compared with the actual total number of times of transmission of the refresh command, and in addition, the self-refresh entry command and the self-refresh exit command have several hundred nanoseconds, which may result in that the measured total number of times of transmission of the refresh command is somewhat larger than the actual total number of times of transmission of the refresh command, so that the total number of times of transmission of the refresh command obtained by the related art is inaccurate.
Based on this, the inventors found through studies that the temperature and self-refresh frequency relationship is different due to the structure and process of each product of the dynamic random access memory. However, to meet the versatility, the protocol requires that each DRAM set a default frequency and specifies the relationship between the mode register MR4 and the frequency division of the default frequency. FIG. 3 is a schematic diagram showing the frequency relationship of the self-refresh frequency signal in a DRAM; the method comprises the following steps: the Function (Function) corresponds to a self-Refresh Rate (Refresh Rate), a Register Type (Register Type) of Read (Read), and an Operand (Operand) of OP [2:0 ]]Data (Data); the specific data comprise: 000 B Corresponding exceeding SDRAM low temperature operation limits (SDRAM Low temperature operating limit exceeded), 001 B Corresponding 4x refresh (4 x refresh), 010 B Corresponding 2x refresh (2 x refresh), 011 B Corresponding 1x refresh, default (1x refresh,default), 100 B Corresponding 0.5x refresh (0.5 x refresh), 101 B Corresponding 0.25x refresh, no degradation (0.5x refresh,no de-rating), 110 B Corresponding 0.25x refresh, degradation (0.5x refresh,with de-rating) and 111 B Corresponding to exceeding the SDRAM high temperature operating limit (SDRAM High temperature operating limit exceeded). The SDRAM is a synchronous dynamic random access memory (synchronous dynamic random-access memory).
Since the self-refresh frequency varies with the temperature, the total number of refresh command transmissions in the refresh mode is approximately equal to the total number of refresh command transmissions in the self-refresh mode when the refresh mode and the self-refresh mode are ensured to operate at the same temperature. Therefore, the total number of times of refresh command transmission in the self-refresh mode can be acquired more accurately by determining the total number of times of refresh command transmission in the refresh mode to be approximately equal to the total number of times of refresh command transmission in the self-refresh mode in this case, thereby further improving the accuracy of analyzing the self-refresh power consumption.
Based on this, the embodiment of the disclosure provides a self-refresh power consumption analysis method, where a semiconductor memory device includes a memory array arranged according to rows and columns, when the semiconductor memory device is in a refresh mode, a total number of times of sending a refresh command to refresh the memory array is obtained through testing, so as to be used as a total number of times of sending a refresh command to refresh the memory array in the self-refresh mode of the semiconductor memory device, when the semiconductor memory device is in the self-refresh mode, a total self-refresh time length to refresh the memory array is obtained through testing, and an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode is obtained according to the total number of times of sending the refresh command and the total self-refresh time length, so that accuracy of determining the total number of times of sending the refresh command is improved, further accuracy of analyzing the self-refresh power consumption is improved, parameters affecting the self-refresh power consumption can be accurately analyzed, and self-refresh power consumption is reduced.
In order to facilitate overall understanding of the technical solution provided by the embodiments of the present disclosure, first, a self-refresh power consumption analysis method of a semiconductor memory device is provided in the embodiments of the present disclosure, and the method may be performed by any computer device having a computing processing capability, which is not limited in particular.
Fig. 4 is a flowchart illustrating a self-refresh power consumption analysis method in an embodiment of the present disclosure, in which a semiconductor memory device includes a memory array arranged in rows and columns. As shown in fig. 4, the self-refresh power consumption analysis method provided in the embodiment of the present disclosure may include the steps of:
s401, when the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command for refreshing the memory array, wherein the total number of times of sending the refresh command for refreshing the memory array is used as the total number of times of sending the refresh command for refreshing the memory array in a self-refresh mode.
In the embodiment of the present disclosure, the total number of times of transmission of the refresh command may be understood as the number of times of transmission of the refresh command by refreshing all memory arrays of the semiconductor memory device one time by the refresh command (refresh command). Under the condition that the semiconductor memory device is guaranteed to have the same temperature in the refresh mode and the self-refresh mode, the total number of times of sending the refresh command obtained by testing can be used as the total number of times of sending the refresh command after the memory array is refreshed in the self-refresh mode when the semiconductor memory device is in the refresh mode.
When the semiconductor memory device is in the refresh mode, the test may be performed by refreshing the memory array in accordance with the rows of the memory array, or by refreshing the memory array in accordance with the columns of the memory array, and refreshing all cells (cells) in the memory array in one pass. In the following examples, a row of data is refreshed with each refresh command.
Illustratively, the memory array includes a target row, for example, the target row may be the 100 th row in the memory array, but the disclosure is not limited thereto, and the target row may be any row randomly selected in the memory array. And testing to obtain the number of times of refreshing commands to the target row after the semiconductor memory device is powered on, and testing to obtain the total number of times of transmitting the refreshing commands according to the number of times of refreshing commands.
Specifically, specific ways of testing the number of refresh commands to get refreshed to a target row after powering up the semiconductor memory device may include, but are not limited to, the following two:
fig. 5 shows one of flowcharts for determining the number of refresh commands, and as shown in fig. 5, may specifically include the following steps:
s31, writing first test data into the target row.
The first test data may be any one of the test data, and is not specifically limited in this disclosure, and the test data such as the second test data, the third test data, and the fourth test data in the following are not specifically limited. The first test data, the second test data, the third test data, and the fourth test data may be the same or different.
S32, sending a refresh command to the semiconductor memory device.
In the embodiment of the disclosure, it is assumed that N (N is a positive integer greater than 1) word lines WL (word line) are provided in the DRAM, and are respectively denoted by WL1, WL2, WL3 … … WLN-1, WLN, and when the DRAM is refreshed, any one of the word lines (assumed to correspond to a row) may be used as a start word line, and from the start word line, each word line in the DRAM may be sequentially refreshed in a cyclic manner according to a preset sequence. The preset sequence may be to refresh the next word line in sequence from the initial word line, and after refreshing the nth word line WLN, to continue to refresh the next word line in sequence from the first word line WL1, and to end a refresh cycle when the next word line is finally refreshed to the initial word line. The transmission of the refresh command to the semiconductor memory device in S32 may start with the start word line in the memory array, for example, a refresh command is transmitted once from row a.
When the DRAM is refreshed, the starting word line used as the starting word line of the cycle and the preset sequence of the cycle can be set by manufacturers of different DRAMs, and after the DRAM is obtained by a user of the DRAM, the starting word line used as the starting word line of the DRAM when the DRAM is refreshed and the preset sequence of the cycle can not be determined, and the number of times of refreshing performed when the DRAM is refreshed once can be determined. The method provided by the embodiment of the disclosure can determine the refresh times of the DRAM when the DRAM performs one-time cyclic refresh, so that the method can be used for analyzing the influence of the DRAM on the self-refresh power consumption of the DRAM.
S33, waiting for a first time period to enable the semiconductor memory device to be in an idle state.
S34, sending n1 times of refresh commands to the semiconductor memory device, wherein n1 is a positive integer greater than or equal to 1.
In the embodiment of the present disclosure, n1 times of refresh commands may be sent to the semiconductor memory device, starting from row a.
S35, waiting for a second time period to enable the semiconductor memory device to be in an idle state.
S36, reading the first response data from the target row.
S37, judging whether a first test result of the target row passes the test or not according to the first test data and the first response data; if the first test result is that the test fails, increasing n1 according to a first preset step length, and returning to the step S31; if the first test result is that the test is passed, S38 is executed.
S38, recording the refresh command frequency of n1+1 when the first test result is that the test passes.
The first time length and the second time length are smaller than the data holding time of the target row, and the sum of the first time length and the second time length is larger than the data holding time of the target row.
In the embodiment of the disclosure, the first duration and the second duration of waiting may be obtained by controlling a specific idle time in a read-write command in a test program.
FIG. 6 shows a second flowchart for determining the number of refresh commands, which may include the following steps, as shown in FIG. 6:
s41, writing first test data into the target row.
S42, waiting for a first time period to enable the semiconductor memory device to be in an idle state.
S43, transmitting n1 times of refresh commands to the semiconductor memory device, wherein n1 is a positive integer greater than or equal to 1.
S44, waiting for a second time period to enable the semiconductor memory device to be in an idle state.
S45, reading the first response data from the target row.
S46, judging whether a first test result of the target row passes the test according to the first test data and the first response data; if the first test result is that the test fails, increasing n1 according to a first preset step length, and returning to execute S41; if the first test result is that the test is passed, S47 is executed.
S47, recording the refresh command times of n1 when the first test result is that the test passes.
The first time length and the second time length are smaller than the data holding time of the target row, and the sum of the first time length and the second time length is larger than the data holding time of the target row.
Both the above two modes can determine the number of refresh commands to the 100 th row in the refresh mode after the semiconductor memory device is powered on. In the above two modes, since the data retention time is a parameter of the configuration program, the data retention time needs to be known in advance during the test to be able to configure the idle state time of the semiconductor memory device in the subsequent test, so the data retention time of the target row needs to be obtained by the test before the first test data is written to the target row. The data retention time can be understood as the time length of any row in the memory array, which can retain data, by continuously adjusting the idle state time of the semiconductor memory device until the data of any row is read, the test result is that the test is failed, that is, the data of the row is not read, which indicates that the data of the row has failed, and the time period from the time when the data is written to until the test result is that the test is failed can be used as the data retention time.
Both ways of determining the number of refresh commands are described as target behavior examples, and the test-obtained data retention time is also described as target behavior examples herein. As shown in fig. 7, fig. 7 shows a flowchart for testing the data retention time of the acquisition target line, which may specifically include the following steps:
s61, writing second test data into the target row.
S62, waiting for a preset time period to enable the semiconductor memory device to be in an idle state.
S63, reading the second response data from the target row.
S64, judging whether a second test result of the target row passes the test according to the second test data and the second response data; if the second test result is that the test passes, increasing the preset time length according to a second preset step length, and returning to the step S61; if the second test result is that the test fails, S65 is executed.
S65, recording the second test result as the data retention time of the target row with the preset duration when the test fails.
In the embodiment of the present disclosure, the data retention time of the target row may be understood as the read-write data of all the cells in the target row, and the test result is the time of passing the test, which may be considered as the data retention time of the target row.
Further, when the test obtains the data retention time, it is also possible to confirm that any one of the cells a in the target row is selected, and the data retention time of the cell a is measured.
After the refresh command number to the target row is obtained after the semiconductor memory device is powered up in the above manner, the refresh command number may be counted as M times. The total number of times of sending the refresh command can be obtained according to the test of the number of times of sending the refresh command, and the specific manner can be shown in fig. 8, fig. 8 shows a flow chart for testing the total number of times of sending the refresh command, and the method specifically can comprise the following steps:
s71, writing third test data into the target row.
S72, a refresh command of the refresh command number is transmitted to the semiconductor memory device.
In the embodiment of the disclosure, the refresh command is sent to the semiconductor memory device for a number of times, that is, M times, to ensure that the target row is in a state where the refresh is just completed, so that the next refresh command of the semiconductor memory device starts from the target row.
S73, waiting for a third time period to enable the semiconductor memory device to be in an idle state.
S74, transmitting n2 refresh commands to the semiconductor memory device, n2 being a positive integer greater than or equal to 1.
And S75, waiting for a fourth time period to enable the semiconductor memory device to be in an idle state.
S76, reading the third response data from the target row.
S77, judging whether a third test result of the target row passes the test according to the third test data and the third response data; if the third test result is that the test fails, increasing n2 according to a third preset step length, and returning to execute S71; if the third test result is that the test is passed, S78 is executed.
S78, recording the total number of times of sending the refresh command when the third test result is that the test passes is n2.
The third time length and the fourth time length are smaller than the data holding time of the target row, and the sum of the third time length and the fourth time length is larger than the data holding time of the target row.
In the embodiment of the present disclosure, the refresh command sent in S74 is started from the target row through S72, and after the first refresh command is sent, the first refresh command may be taken as an example of a refresh, and a fourth period of time is waited, where the fourth period of time is longer than the data retention time of the target row, if the first refresh command in S74 does not refresh the target row, the data of the target row fails, and when the data of the target row is read, the test result is that the test fails, and it may be obtained that the first refresh command does not refresh the target row. And continuously increasing the refreshing times of the refreshing command according to a third preset step length until the test result is that the test is passed, indicating that the refreshing command starts refreshing from the target row and the refreshing command ends until the target row, and obtaining the total times of transmitting the refreshing command.
In this way, after determining the total number of times of transmission of the refresh command when the semiconductor memory device is in the refresh mode, the total number of times of transmission of the refresh command when the semiconductor memory device is in the self-refresh mode and the memory array is refreshed can be regarded as the total number of times of transmission of the refresh command when the semiconductor memory device is in the self-refresh mode, and S402 is executed.
S402, when the semiconductor memory device is in the self-refresh mode, testing to obtain the total self-refresh duration of the memory array after being refreshed.
In the embodiment of the disclosure, the total self-refresh duration obtained after the refresh of the memory array is tested may be as shown in fig. 9, where fig. 9 shows a flowchart for obtaining the total self-refresh duration in the self-refresh mode; the method specifically comprises the following steps:
s81, writing fourth test data into the target row.
S82, sending the refresh command of the refresh command times to the semiconductor memory device.
S83, waiting for a fifth time period to enable the semiconductor memory device to be in an idle state.
S84, the semiconductor memory device is in a self-refresh mode in the self-refresh time.
In the embodiment of the present disclosure, the semiconductor memory device needs to be in the self-refresh mode during the self-refresh time to obtain the total self-refresh duration, and fig. 10 is a flowchart showing the semiconductor memory device being in the self-refresh mode during the self-refresh time; as shown in fig. 10, the method specifically includes the following steps:
s841, a self-refresh entry command is sent to the semiconductor memory device to control the semiconductor memory device to enter the self-refresh mode.
S842, the semiconductor memory device is in the self-refresh mode during the self-refresh time.
S843, a self-refresh exit command is sent to the semiconductor memory device to control the semiconductor memory device to exit the self-refresh mode.
In the embodiments of the present disclosure, by continuously transmitting a self-refresh entry command and a self-refresh exit command to the semiconductor memory device, the semiconductor memory device can be put in a self-refresh mode for a self-refresh time until the self-refresh total duration is obtained.
S85, waiting for a sixth time period to enable the semiconductor memory device to be in an idle state.
S86, reading fourth response data from the target row.
S87, judging whether a fourth test result of the target row passes the test according to the fourth test data and the fourth response data; if the fourth test result is that the test fails, increasing the self-refresh time according to a fourth preset step length, and returning to execute S81; if the fourth test result is that the test is passed, S88 is executed.
S88, recording the self-refresh time when the fourth test result is that the test passes as the total self-refresh duration.
Wherein, the fifth time length and the sixth time length are smaller than the data holding time of the target row, and the sum of the fifth time length and the sixth time length is larger than the data holding time of the target row.
After the total self-refresh duration is obtained, the self-refresh power consumption of the semiconductor memory device may be analyzed according to the total number of times the semiconductor memory device has been refreshed in the self-refresh mode by transmitting a refresh command to refresh the memory array, and S403 may be executed.
S403, according to the total number of times of sending the refresh command and the total self-refresh duration, obtaining the analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode.
In the embodiment of the disclosure, the self-refresh power consumption is analyzed according to the total sending times of the refresh command and the self-refresh duration, so that the self-refresh current can be tested by a machine under the condition of fixed self-refresh voltage, and the self-refresh power consumption can be represented by the self-refresh current.
The specific analysis mode can be as follows: and obtaining the total number of times of sending the refresh command and the total self-refresh duration of each of the plurality of semiconductor memory devices with the same capacity, detecting and obtaining the self-refresh current of each semiconductor memory device in the self-refresh mode under the condition of fixed self-refresh voltage, and according to the self-refresh current of each semiconductor memory device, obtaining an analysis result that the total number of times of sending the refresh command and the total self-refresh duration are inversely related to the self-refresh power consumption.
The above analysis results are illustrated by the following table, as shown in table 1 below:
TABLE 1
The above table is used to illustrate that, taking six different types of particles as examples, each particle corresponds to its own capacity, and the larger the capacity, the more memory arrays need to be refreshed, and the larger the corresponding self-refresh power consumption.
The refresh command interval of the semiconductor memory device in the self-refresh mode is obtained according to the self-refresh total duration and the total number of times of refresh command transmission.
The association relationship between the self-refresh total duration, the total number of times of refresh command transmission, and the refresh command interval can be expressed by the formula (1):
（1）
wherein,,representing a refresh command interval; />Representing the total self-refresh duration; r represents the total number of refresh command transmissions.
Also included in the table is a preset data retention time obtained by multiplying the refresh time interval 3.9us by the total number of refresh command transmissions in the refresh parameters of fig. 1. It should be noted that, the preset data retention time is an ideal value, which may be different from the result obtained by the actual test, the refresh time interval 3.9us in the refresh parameter is only a recommended value, and the actual refresh time interval may be greater or less than the value, which is based on the actual determined result.
The test data retention time is the actual data retention time obtained by the step test shown in fig. 7. Based on the data obtained by the test, the actual refresh time interval of the particle 1 can be solved, and then the refresh time interval of the particle 1 is 4.421us.
As can be seen from the table, the larger the total number of times of sending the refresh command is, the smaller the self-refresh current is, and the smaller the self-refresh power consumption is; the greater the total self-refresh duration, the smaller the self-refresh current and the less self-refresh power consumption. For example, by comparing the grain 1, the grain 2, and the grain 5, in the case where the total self-refresh time period is approximately equal, the total number of refresh command transmission times of the grain 1 is maximum, and the self-refresh current thereof is minimum.
Based on the self-refresh power consumption analysis method of the semiconductor memory device, the total number of times of sending the refresh command and the total self-refresh time length of the memory array of the semiconductor memory device in the self-refresh mode can be accurately obtained, the refresh time interval can be calculated according to the association relation among parameters, the self-refresh power consumption is analyzed through the parameters to obtain the influence factors influencing the self-refresh power consumption, the self-refresh power consumption is reduced by adjusting the related influence factors, the self-refresh power consumption is an important characteristic parameter of the semiconductor memory device, and the product has market competitiveness at the end of the month of the self-refresh power consumption.
Based on the same inventive concept, there is also provided a self-refresh power consumption analysis device of a semiconductor memory device in an embodiment of the present disclosure, as described in the following embodiment. Since the principle of solving the problem of the embodiment of the device is similar to that of the embodiment of the method, the implementation of the embodiment of the device can be referred to the implementation of the embodiment of the method, and the repetition is omitted.
Fig. 11 is a schematic diagram of a self-refresh power consumption analysis device of a semiconductor memory device according to an embodiment of the present disclosure, and as shown in fig. 11, the device may include: a controller 1101, the controller 1101 performing the steps of: when the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command of the memory array after refreshing, wherein the total number of times of sending the refresh command of the memory array after refreshing the memory array in the self-refresh mode is taken as the total number of times of sending the refresh command of the memory array after refreshing the memory array in the self-refresh mode; when the semiconductor memory device is in a self-refresh mode, testing to obtain the total self-refresh time length of the memory array after being refreshed; and according to the total number of times of sending the refresh command and the total self-refresh duration, obtaining an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode.
Referring to fig. 12, fig. 12 is a schematic structural diagram of a computer device according to an embodiment of the present disclosure. As shown in fig. 12, a computer device in an embodiment of the present disclosure may include: one or more processors 1201, memory 1202, and input-output interfaces 1203. The processor 1201, the memory 1202, and the input-output interface 1203 are connected via a bus 1204. The memory 1202 is used for storing a computer program including program instructions, and the input output interface 1203 is used for receiving data and outputting data, such as for data interaction between a host and a computer device, or for data interaction between respective virtual machines in a host; the processor 1201 is configured to execute program instructions stored in the memory 1202.
The processor 1201 may perform the following operations, among others: when the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command of the memory array after refreshing, wherein the total number of times of sending the refresh command of the memory array after refreshing the memory array in the self-refresh mode is taken as the total number of times of sending the refresh command of the memory array after refreshing the memory array in the self-refresh mode; when the semiconductor memory device is in a self-refresh mode, testing to obtain the total self-refresh time length of the memory array after being refreshed; and according to the total number of times of sending the refresh command and the total self-refresh duration, obtaining an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode.
The memory 1202 may include read only memory and random access memory, and provides instructions and data to the processor 1201 and the input output interface 1203. A portion of memory 1202 may also include non-volatile random access memory. In a specific implementation, the computer device may execute, through each built-in functional module, an implementation manner provided by each step in any method embodiment described above, and specifically may refer to an implementation manner provided by each step in a diagram shown in the method embodiment described above, which is not described herein again.
Embodiments of the present disclosure provide a computer device comprising: a processor, an input-output interface, and a memory, where the processor obtains a computer program in the memory, and performs the steps of the method shown in any of the embodiments above.
The embodiments of the present disclosure further provide a computer readable storage medium, where a computer program is stored, fig. 13 shows a schematic diagram of a computer readable storage medium in an embodiment of the present disclosure, and as shown in fig. 13, a program product capable of implementing the method of the present disclosure is stored on the computer readable storage medium 1300. The computer program is adapted to be loaded by the processor and to perform the method of analyzing self-refresh power consumption of the semiconductor memory device provided by the steps of any of the embodiments described above.
The disclosed embodiments also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the methods provided in the various alternatives of any of the embodiments described above.
Claims (9)
1. A self-refresh power consumption analysis method of a semiconductor memory device is characterized in that the semiconductor memory device comprises a memory array arranged according to rows and columns; wherein the method comprises the following steps:
When the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command after refreshing the memory array, wherein the total number of times of sending the refresh command after refreshing the memory array in the self-refresh mode is taken as the total number of times of sending the refresh command after refreshing the memory array by the semiconductor memory device;
when the semiconductor memory device is in the self-refresh mode, testing to obtain the total self-refresh time length after refreshing the memory array;
according to the total number of times of sending the refresh command and the total self-refresh duration, obtaining an analysis result of self-refresh power consumption of the semiconductor memory device in the self-refresh mode;
the method for obtaining the analysis result of the self-refresh power consumption of the semiconductor memory device in the self-refresh mode according to the total number of times of sending the refresh command and the total self-refresh duration comprises the following steps:
obtaining a total number of times of transmission of refresh commands and a total self-refresh time length of each of a plurality of semiconductor memory devices having the same capacity;
detecting and obtaining self-refresh current of each semiconductor memory device in the self-refresh mode under the condition that self-refresh voltage is fixed;
according to the self-refresh current of each semiconductor memory device, the obtained analysis result is that the total number of times of sending the refresh command and the total self-refresh duration are inversely related to the self-refresh power consumption.
2. The method of claim 1, wherein the storage array includes a target row therein;
when the semiconductor memory device is in a refresh mode, testing to obtain the total number of times of sending the refresh command after refreshing the memory array, wherein the method comprises the following steps:
testing and obtaining the refresh command times of refreshing the semiconductor memory device to the target row after the semiconductor memory device is powered on;
and obtaining the total sending times of the refresh command according to the refresh command times test.
3. The method of claim 2, wherein testing for a number of refresh commands to refresh to the target row after power-up of the semiconductor memory device comprises:
s31, writing first test data into the target row;
s32, sending a refresh command to the semiconductor memory device once;
s33, waiting a first time period to enable the semiconductor memory device to be in an idle state;
s34, sending n1 times of refreshing commands to the semiconductor storage device, wherein n1 is a positive integer greater than or equal to 1;
s35, waiting for a second time period to enable the semiconductor memory device to be in an idle state;
s36, reading first response data from the target row;
s37, judging whether a first test result of the target row is test passing or not according to the first test data and the first response data, if the first test result is test failing, increasing n1 according to a first preset step length, and repeatedly executing S31-S36 until the first test result is test passing;
S38, recording the refresh command frequency of n1+1 when the first test result is that the test passes;
wherein the first duration and the second duration are both less than the data retention time of the target row, and the sum of the first duration and the second duration is greater than the data retention time of the target row.
4. The method of claim 2, wherein testing for a number of refresh commands to refresh to the target row after power-up of the semiconductor memory device comprises:
s41, writing first test data into the target row;
s42, waiting a first time period to enable the semiconductor memory device to be in an idle state;
s43, sending n1 times of refresh commands to the semiconductor storage device, wherein n1 is a positive integer greater than or equal to 1;
s44, waiting a second time period to enable the semiconductor memory device to be in an idle state;
s45, reading first response data from the target row;
s46, judging whether a first test result of the target row is test passing or not according to the first test data and the first response data, if the first test result is test failing, increasing n1 according to a first preset step length, and repeatedly executing S41-S46 until the first test result is test passing;
S47, recording the refresh command frequency n1 when the first test result is that the test passes;
wherein the first duration and the second duration are both less than the data retention time of the target row, and the sum of the first duration and the second duration is greater than the data retention time of the target row.
5. The method of claim 3 or 4, further comprising:
testing to obtain the data retention time of the target row.
6. The method of claim 5, wherein testing for data retention time of the target row comprises:
s61, writing second test data into the target row;
s62, waiting for a preset time period to enable the semiconductor memory device to be in an idle state;
s63, reading second response data from the target row;
s64, judging whether a second test result of the target row is test passing or not according to the second test data and the second response data, if the second test result is test passing, increasing the preset time length according to a second preset step length, and repeatedly executing S61-S64 until the second test result is test failing;
s65, recording the preset time length when the second test result is that the test fails as the data retention time of the target row.
7. The method of claim 2, wherein obtaining the total number of refresh command transmissions based on the refresh command number test comprises:
s71, writing third test data into the target row;
s72, sending the refresh command of the refresh command times to the semiconductor storage device;
s73, waiting a third time period to enable the semiconductor memory device to be in an idle state;
s74, sending n2 refresh commands to the semiconductor storage device, wherein n2 is a positive integer greater than or equal to 1;
s75, waiting for a fourth time period to enable the semiconductor memory device to be in an idle state;
s76, reading third response data from the target row;
s77, judging whether a third test result of the target row is test passing or not according to the third test data and the third response data, if the third test result is test failing, increasing n2 according to a third preset step length, and repeatedly executing S71-S76 until the third test result is test passing;
s78, recording the total number of times of sending the refresh command when the third test result is that the test passes is n2;
wherein the third duration and the fourth duration are both less than the data retention time of the target row, and the sum of the third duration and the fourth duration is greater than the data retention time of the target row.
8. The method of claim 2, wherein testing for a total self-refresh duration to refresh the memory array while the semiconductor memory device is in the self-refresh mode comprises:
s81, writing fourth test data into the target row;
s82, sending the refresh command of the refresh command times to the semiconductor storage device;
s83, waiting for a fifth time period to enable the semiconductor memory device to be in an idle state;
s84, enabling the semiconductor memory device to be in the self-refresh mode in self-refresh time;
s85, waiting a sixth time period to enable the semiconductor memory device to be in an idle state;
s86, reading fourth response data from the target row;
s87, judging whether a fourth test result of the target row is test passing or not according to the fourth test data and the fourth response data, if the fourth test result is test failing, increasing the self-refresh time according to a fourth preset step length, and repeatedly executing S81-S87 until the fourth test result is test passing;
s88, recording the self-refreshing time of the fourth test result when the test passes as the self-refreshing total duration;
wherein the fifth time period and the sixth time period are both smaller than the data holding time of the target row, and the sum of the fifth time period and the sixth time period is larger than the data holding time of the target row.
9. The method of claim 8, wherein placing the semiconductor memory device in the self-refresh mode for a self-refresh time comprises:
s841. sending a self-refresh entry command to the semiconductor memory device to control the semiconductor memory device to enter the self-refresh mode;
s842. placing the semiconductor memory device in the self-refresh mode during the self-refresh time;
s843. sending a self-refresh exit command to the semiconductor memory device to control the semiconductor memory device to exit the self-refresh mode.
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