JPH07176684A - Semiconductor device - Google Patents

Abstract

PURPOSE:To mount a plurality of semiconductor chips without increasing the overall size and to realize high speed transmission while reducing the weight and enhancing the heat dissipation properties by providing a bonding pattern being connected through holes and a stiffener base having I/O part being connected with the bonding pattern of an interposer. CONSTITUTION:An interposer 12 is provided with a plurality of through holes 11 corresponding to a circuit pattern regularly at a predetermined interval in the central region thereof. A bonding pattern 17 is arranged at a constant pitch in four directions at the outer end of the region where the through holes 11 are arranged regularly. Furthermore, a stiffener base 13 formed of a glass fiber reinforced polymide board (copper clad by 18mum on the opposite sides) of 0.8mm thick having through holes 10, 10A is fixed to the outer periphery of the interposer 12 on the CPU chip 6 side. This structure allows mounting of a plurality of semiconductor chips without increasing the overall size thus realizing high speed transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure in which a plurality of semiconductor chips are three-dimensionally mounted.

[0002]

2. Description of the Related Art Conventional semiconductor devices include, for example, a plurality of semiconductor chips arranged in a plane on a substrate, such as a multi-chip package (MCP), a hybrid IC, and a multi-chip module (MCM). Equivalent to. Among them, the MCP provides a wiring structure around the substrate, connects a plurality of semiconductor chips arranged in the center of the substrate to one end of the wiring structure, and connects the other end of the wiring structure to an external pin connected to an external circuit. It has a connected structure, and has a heat dissipation structure on the opposite side of the external pin if necessary. According to this MCP, it is possible to achieve high density and unitization of circuit devices, which contributes to ease of assembly of a system using the same and simplification of configuration.

[0003]

However, the conventional semiconductor device having a plurality of semiconductor chips mounted thereon has the following problems.

(1) The size of the package becomes large. Since the plurality of semiconductor chips are arranged in a plane, the area occupied by the package becomes large and the printed circuit board for mounting becomes large.

(2) The wiring length becomes long. Since the plurality of semiconductor chips are arranged in a plane, the wiring length for connection becomes long and the resistance value increases. Also, the inductance,
Since the capacitance also increases, the transmission delay time increases and high-speed transmission becomes difficult.

(3) The package becomes heavy. Since the package is generally solidified with a resin or the like by molding, if the shape becomes large due to the above (1), the weight also becomes heavy, and there is a limit to weight reduction. The weight of a system such as a computer incorporating such a package becomes heavy.

(4) The heat dissipation becomes poor. Generally, what is hardened with resin or the like by molding is thermally insulated, and even if a heat dissipation structure is provided, sufficient heat dissipation cannot be obtained. Therefore, an object of the present invention is to provide a semiconductor device having a structure that is not so large even if a plurality of semiconductor chips are mounted, is capable of high-speed transmission, is lightweight, has good heat dissipation, and is inexpensive in terms of total cost. To provide.

[0008]

According to the present invention, even if a plurality of semiconductor chips are mounted, the size is not so large, high-speed transmission is possible, the weight and the heat dissipation are good, and the total cost is low. Therefore, there is provided a semiconductor device having an interposer having bonding patterns connected by through holes on the first and second surfaces and a stiffener base having an input / output unit connected to the bonding pattern of the interposer.

In the present invention, the mounting method (element connecting method) of the first semiconductor chip and the second semiconductor chip is a wire bonding method or a gang bonding method (T
Method using an AB tape carrier).

[0010]

According to the present invention, the interposer having the bonding patterns on the first and second surfaces incorporates a part of the mounting printed board into the package, and the semiconductor mounted on the first and second surfaces. Since the chip is connected to the input / output unit of the stiffener base via the bonding pattern and further connected to the external circuit, the printed circuit board for mounting is formed compactly.

[Embodiment 1] An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, showing a main body substrate portion 1 (mold-sealed) having a heat dissipation cap 4 and a bump 14 provided on the bottom.

FIG. 2 is an exploded view of the structure. As shown in FIG. 2, the main body substrate portion 1 includes an interposer 12 and a stiffener base 13.

The interposer 12 has a 125 μm-thick polyimide resin called Upilex (registered trademark) as a base film, and a double-sided CCL (copper) in which copper foil is adhered to the front and back by a polyimide adhesive.
The circuit pattern is formed by Clad Laminates.

On the front side of the interposer 12, 12
A tape carrier package (TCP) 2 having an I / O chip 5 mounted on a base film 7 made of a polyimide film having a thickness of 5 μm and provided with a lead-out terminal 8 having a 300-pin terminal is attached to the back surface of the tape carrier package (TCP) 2. A CPU 3 having a similar configuration is mounted, and a TCP 3 provided with a lead terminal 8A having a 300-pin terminal is attached.

The surfaces of TCP2 and TCP3 are coated with a potting resin (not shown), and the I / O chip 5 and the CPU chip 6 are TA.
B (Tape Automated Bonding)
The above-mentioned terminals 8 and 8A are drawn out by the method. Further, a heat dissipation cap 4 is attached to the I / O chip 5 and the CPU chip 6 to enhance heat dissipation.

The shape of the heat dissipation cap 4 may be set according to the heat dissipation of the chip. For example, in the case of a chip such as a cache memory in which heat dissipation is not important, it can be omitted or a small size can be selected.

The interposer 12 is provided with a plurality of through holes 11 arranged in a central region thereof at a predetermined interval in accordance with the circuit pattern described above. The land layer 1 described later is provided on the inner diameter of each through hole 11.
1A is formed.

At the outer end of the region where the through holes 11 are defined and arranged, there are joint patterns 17 and 17A (back side; not shown) arranged at equal pitches over the entire circumference in four directions.

In addition, a predetermined number of lead-through through holes 11B arranged at equal intervals are provided in the vicinity of the outer edge of the interposer 12, and an external transmission line 19 connected to the bonding pattern 17 is formed in the through hole 11B. It is connected to and pulled out on the back side.

FIG. 3 is a sectional view of the semiconductor device of the present invention, in which the lead terminals 8 and 8A of the I / O chip 5 and the CPU chip 6 are joined to the joining patterns 17 and 17A at the joining portions 15 and 15A. There is.

The joint portions 15 and 15A are formed by, for example, tin bump plating on the side of the interposer 12 to form a TCP.
Gold plating is applied to the 2 and 3 lead terminals 8 and 8A,
A so-called Au-Sn, in which both are brought into contact with each other to perform heat treatment
It is joined by the eutectic joining method.

The internal transmission lines 20 and 20A (back side) are connected to the through holes 11 side of the joining patterns 17 and 17A.
/ O chip 5 and CPU chip 6 lead-out terminal 8,
8A is connected. Further, the external transmission lines 19 and 19A are continuously provided on the bonding patterns 17 and 17A.

The outer edge of the interposer 12 on the CPU chip 6 side has through holes 10 and 10A.
mm thickness glass fiber reinforced polyimide substrate (double-sided copper foil 18
The stiffener base 13 formed of (with μm) is attached.

The external transmission line 19 on the I / O chip 5 side is
At the outer edge of the interposer 12, the through hole 1
It is drawn out to the stiffener base 13 side via 1B, and is further connected to a bump 14 for mounting a substrate provided at the lower end of the through hole 10 via a joint portion 21.

The external transmission line 19A connected to the lead-out terminal 8A of the CPU chip 6 is similarly connected to the board mounting bump 14A provided at the lower end of the through hole 10A via the joint 21A. These bumps 14,
14A is provided so as to be located at the terminal 18 of the printed circuit board (PCB) 22.

The joint portions 21 and 21A are the joint portions 1 described above.
Similar to 5, 15A, for example, stiffener base 13
Gold plating is formed on the side, a tin-plated bump is formed on the pattern of the external transmission line 19 of the interposer 12, and both are brought into contact with each other to perform heat treatment.
They are joined by the Sn eutectic joining method.

FIG. 4 shows the routing of the internal transmission lines 20 and 20A. In the figure, the bonding pattern 1 on the I / O chip 5 side is shown.
7 is shown by a solid line, and the joint pattern 17A on the CPU chip 6 side is shown by a dotted line. The bonding pattern 17 is also provided directly above the bonding pattern 17A, but the description thereof is omitted.
The solid line shows that the I / O chip 5 side is passed and the dotted line shows that the CPU chip 6 side is passed.

The number of I / O chips 5 on the front side and the CPU chips 6 on the back side that need to be connected differs depending on the combination of the LSI chips to be mounted, but if the number is 30% of the total number of terminals, for example, 90 for 300 pins
The books are routed by the internal transmission line 20, and the remaining 70% of the 210 books are the lead terminals 8 of the I / O chip 5.
Input and output signals from.

When the wirings are orthogonal to each other on the interposer 12, the wirings are turned to the back surface through the through holes 11. A land layer 11A made of copper foil is provided in the inner diameter of the through hole 11, and the internal transmission line 20 is connected to the front side of the through hole 11 so that the internal transmission line 20A is pulled out to the back side to prevent a short circuit. . When there are many orthogonal internal transmission lines 20, 20A, the nearest through hole 11 is used each time to prevent a short circuit.

In the wiring of an LSI chip having a combination of a small number of orthogonal internal transmission lines 20, 20A, it is possible to use the through holes 11 less often, but when there are many orthogonal internal transmission lines 20, 20A, many through holes 11 are formed.
Is required. In such a case, the through hole 11
It is preferable that the position and the number of are set in advance and provided on the interposer 12.

Further, it is preferable to set the wiring paths of the internal transmission lines 20, 20A so that the inductance due to the electric interference between the front side wiring and the back side wiring becomes as small as possible. This is because the wiring resistance increases as the number of through holes 11 used increases on the same transmission line, which causes transmission delay and transmission failure. Therefore, it is necessary to improve the mounting direction of the front and back chips and the route. Determine the optimal route as you go.

An address is attached to each through hole 11, and the address of the through hole 11 used for each wiring combination is registered in a separate table. The line length of the wiring is also described in the same table (not shown), and the total wiring resistance is finally calculated by the value.

When the combination of the internal transmission lines 20 and 20A causes large inductance interference, for example, a solid conductive pattern (not shown) is widely provided around the through hole 11 and the solid conductive pattern is provided in the nearest position. Take measures such as connecting to the ground terminal (not shown).

The database of such electrical specifications is organized so that the electrical judgment of each connection can be made immediately. It will be used as reference data when performing electrical operation check after the package is completed, and it will be collated with operation measurement data such as transmission waveform, rising pulse, delay time, generated noise, etc. to develop an even better package. Useful.

The manufacturing process of the semiconductor device of the present invention will be described below. First, the polyimide film is the base film 7
Then, TCP 2 and 3 are prepared by making a TAB tape carrier having the following structure, connecting the I / O chip 5 and the CPU chip 6 to each other, and coating the chip surface with a potting resin.

Next, an interposer 12 having circuit patterns on both sides and through holes 11 and 11B is formed.

Next, the TCP connection portion and the stiffener connection portion of the interposer 12 are partially tin-plated in the film portion to a thickness of 7 μm, and the TCP side is gold-plated to a thickness of 1 μm to form the lead terminals 8 of the TCPs 2 and 3. After the bonding pattern 17 of the interposer 12 is aligned, a heating tool is brought into contact with it to bond Au / Sn. After the bonding of one chip is completed, the other chip is bonded in the same manner.

Next, the stiffener base 13 having the through holes 10 and 10A is formed from the glass fiber reinforced polyimide substrate.

Next, a portion of the stiffener base 13 corresponding to the joints 21 and 21A is plated with gold of 1.0 μm, the interposer 12 and the stiffener base 13 are aligned with each other, and Au—Sn joining is performed. After assembly is complete,
Potting sealing is performed using an epoxy-based liquid resin.

Example 2 In Example 1, the bumps 14 and 14A were formed before joining the stiffener base.

The bumps were formed by printing a plating resist on the area other than the bump forming area by a screen printing method, and forming a bump having a height of 200 μm and a diameter of 0.5 mm by a high-speed plating method using copper sulfate. The total number of bumps is 400.

[Third Embodiment] In the second embodiment, Sn60% -Pb is formed by a solder paste printing method instead of the copper bumps.
Eutectic solder bumps were formed. The height of the solder bump is 0.
It was 4 mm.

[Embodiment 4] In Embodiment 1, L on the front side
The SI chip has two cache memories. In this case, the cache memory also has a TCP shape.

[Embodiment 5] In Embodiment 1, gold plated pins separately prepared by Kovar are inserted into the through holes 10 and 10A to form a PGA type mounting package.

[Embodiment 6] In Embodiment 1, I on the front side
A copper piece having the same outer diameter as the chip and a thickness of 0.5 mm was attached to both surfaces of the / O chip and the CPU chip on the back side with an epoxy adhesive.

[Embodiment 7] FIG. 5 shows an interposer 12 having an I / O chip 5 and a CPU chip 6 mounted on both sides without interposing a base film, and an interposer 1.
2 shows a semiconductor device 31 having a Flip TAB type TCP having a stiffener base 13 provided on the outer edges of both surfaces of the No. 2 and chip-coated with a potting resin 25.

FIG. 6 (A) shows a semiconductor device 30 having a film laminate type TCP made in Example 1, and FIG. 6 (B) shows a flip TAB made in Example 7.
This is a semiconductor device 31 having a TCP scheme. The size of the semiconductor device 31 is as small as 20 mm, while the semiconductor device 30 is 32 mm square.

[Embodiment 8] FIG. 7 shows a chip board 24A on which an I / O chip 5 is mounted on one side, and a chip on which a CPU chip 6 is mounted via a spacing unit 23 on which the chip board 24A is mounted. A semiconductor device 32 having a board 24B is shown.

According to this structure, in order to mount the I / O chip 5 and the CPU chip 6 on one side of the chip board 24A and the chip board 24B, the semiconductor chips are mounted on both sides of the interposer. Therefore, it is possible to solve the problem that the bonding between the chips is easy and the function of the integrated package is impaired due to the defective bonding of one of the semiconductor chips.

[Embodiment 9] In Embodiment 1, the structure of the semiconductor device is the same as the spaceing unit type of Embodiment 8. The same 125 μm-thick polyimide substrate as the interposer 12 of Example 1 was used for the chip-on-board. Further, the chip-on-board and the spacing unit were similarly bonded by the Au-Sn bonding method.

[Embodiment 10] FIG. 8 shows a module 26 in which eight sets of semiconductor devices 30 each having a film laminate type TCP in Embodiment 1 are three-dimensionally stacked to have a height of 10 mm.

The total height of one semiconductor device is 0.4 mm.
Two thick chips and an interposer thickness of 0.1
Designed to be 5mm + space 0.2, total 1.15mm
Is. Therefore, the height of 8 sets was 9.2 mm. A pedestal 33 made of a 0.8 mm copper plate was attached to the top of the module 26.

When semiconductor devices are piled up to form a module type, heat dissipation deteriorates. The pedestal 33 provided on the uppermost part of the stacked semiconductor devices is used as a mounting pedestal for a radiation fin that improves the radiation characteristics of the module. That is,
Aluminum die-cast radiating fins are attached on top of this according to the required heat radiation characteristics in various shapes.

[Embodiment 11] FIG. 9 shows a semiconductor device 31 of the Flip TAB method according to the seventh embodiment.
8 shows a module 27 made by stacking 8 sets in the same manner as. According to this shape, the outer diameter of the module 27 is 20 mm
The corners were small. Further, the radiating base 33 is the first embodiment.
It was attached in the same manner as 0.

Table 1 shows the size and weight when the semiconductor device of the present invention having the above-described structure is manufactured.

[Table 1] As shown in Table 1, the semiconductor device of the present invention can have a compact outer shape even if a large number of cache memories, standard logics, etc., which are required for system upgrades, are provided in the package.

By thus stacking the semiconductor devices three-dimensionally into a module, the connection between the semiconductor chips mounted on each interposer can be simplified, and further, the power supply, the ground wiring, etc. By using all of the common wirings, the lead terminals for one semiconductor chip can be mounted on the PCB.

For example, when a module is constructed by stacking eight packages, the connection length in the module is only 10 mm to 20 mm, which is about 1/10 of the wiring length of a normal plastic package.

In addition, since all the wiring between the semiconductor chips can be provided in the module, the wiring resistance is reduced and the noise level is reduced, so that high-speed transmission becomes possible. In addition, the printed circuit board is made compact, so that the printed circuit board can be made lighter and can be manufactured at low cost.

[Embodiment 12] In the module structure of Embodiment 11, the temperature detecting sensor chip of the package was incorporated in the uppermost stage of eight sets stacked.

The temperature sensing sensor incorporates both a silicon diode PN junction element and a silicon transistor PNP junction element. As a result of the test, the PN junction element has a temperature and a forward voltage in the range of -50 ° C to 100 ° C. Shows a linear relationship, and the PNP junction element has a temperature of −50 ° C.
It showed linearity in the range of 250 ° C.

In the case of the module structure, since the heat dissipation of the chips in the middle part of the stack is particularly deteriorated, the SRAM
Although it is used like a data bank equipped with memory devices such as, the temperature rises when data is caught and fetched at high speed, and a protection circuit is required.

According to this embodiment, by incorporating the temperature detecting sensor, it is possible to systematically issue a command such as switching the power supply voltage to a low voltage or pausing when the module temperature reaches 75 ° C. .

[Embodiment 13] Flip TA of Embodiment 7
In a B-structure semiconductor device, a TAB is not used to connect a semiconductor element and an interposer, and a CCB (Contro
Illed Collapse Bonding) method was used.

FIG. 10 shows a sectional structure of a semiconductor device in which the solder bumps 32 are formed on the lower surface of the chip by the CCB method by the plating method. The solder bumps 32 are connected to the pattern of the interposer 12.

According to this semiconductor device, since there is no connection terminal on the outer peripheral portion of the chip, the outer shape can be made smaller. Moreover, since the entire lower surface of the chip can be used as the terminal surface, it can be said that the structure can be made more highly functional toward future increase in the number of pins.

The composition of the solder bump is 60% Pb-40% S.
It was set to n. That is, in reflow surface mounting, it is for preventing excessive melting of the CCB solder (the composition of the reflow surface mounting solder is usually 60% Pb-40% Sn).

As a method of forming solder bumps, a plating resist was formed on the lower surface of the chip, and then partial plating (electroplating) of solder was performed, and then the plating resist was peeled off and reflowed to obtain a spherical ball shape. On the other hand, on the interposer side, a pattern was accurately formed by etching at a position corresponding to the solder bump, and after mounting a chip on this pattern, the fusion bonding of the solder pattern was completed through an infrared heating furnace.

[0068]

As described above, according to the semiconductor device of the present invention, the interposer having the joint patterns connected by the through holes on the first and second surfaces is connected to the interposer joint pattern. Since the stiffener base having the input / output section is provided, the size is not so large even when a plurality of semiconductor chips are mounted, high-speed transmission is possible, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is an exploded structural diagram of the semiconductor device shown in FIG.

3 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 4 is an explanatory diagram showing connection of semiconductor chips mounted on the interposer 12.

FIG. 5 is a cross-sectional view showing another embodiment of the present invention.

6A is a perspective view showing a film laminate type TCP, and FIG. 6B is a flip TAB TCP.
FIG.

FIG. 7 is an explanatory diagram showing another embodiment of the present invention.

FIG. 8 is a perspective view of a module 26 formed by three-dimensionally stacking eight sets of semiconductor devices 30 of the present invention.

FIG. 9 is a perspective view of a module 27 formed by three-dimensionally stacking eight sets of semiconductor devices 31 of the present invention.

FIG. 10 is a sectional view showing another embodiment of the present invention.

[Explanation of symbols]

1 main body board section 2 TCP
(Front side) 3 TCP (Back side) 4 Heat dissipation cap 5 I / O chip 6 CPU
Chip 7 Base film 8, 8A Lead-out terminal 10, 10A, 11, 11B Through hole 11A Land layer 12 Interposer 13 Stiffener base 14, 14A
Bump 15,15A Joint 17,17A
Junction pattern 18 terminals 19 External transmission line 20, 20A Internal transmission line 21, 21A
Joining part 22 PCB 23 Spacing unit 24A, 24B Chip on board 25 Potting resin 26, 27 Module 30, 31
Semiconductor device 32 bump

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mamoru Mita 3-1-1 Sukegawa-cho, Hitachi-city, Ibaraki Hitachi Cable Company, Ltd. (72) Inventor Toyohiko Kumakura 3-1-1 Sukegawa-cho, Hitachi, Ibaraki No. 1 Hitachi Cable Co., Ltd. Electric Cable Factory (72) Inventor Ryuji Yonemoto 3550 Kida Yomachi, Tsuchiura City, Ibaraki Prefecture Hitachi Cable Co., Ltd. System Materials Research Center

Claims (11)

[Claims] 1. An interposer having circuit patterns connected by through holes on first and second surfaces, and a stiffener base having an input / output unit connected to the circuit pattern of the interposer, The first and second semiconductor chips are mounted on the first and second surfaces of the interposer and connected to the circuit pattern, and the input / output unit of the stiffener base is connected to an external circuit. A semiconductor device characterized by the above. 2. The circuit pattern is connected to a joint pattern connected to a terminal of the semiconductor chip, an internal transmission pattern connecting the through hole and the joint pattern, and the input / output unit of the stiffener base. The semiconductor device according to claim 1, comprising a through hole and an external transmission pattern connecting the bonding pattern. 3. The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on the interposer by wire bonding or a TAB method. 4. The semiconductor device according to claim 1, wherein the lead-out of the stiffener base terminal is a bump or a pin. 5. The connection between the interposer and the stiffener base is an Au—Sn bonding method.
The semiconductor device according to the item. 6. The semiconductor device according to claim 1, wherein the arrangement of the through holes is defined in advance. 7. The interposer according to claim 1, wherein the semiconductor chips are mounted on both sides of the interposer, or the interposers are separately mounted on a board and the upper and lower semiconductor chips are connected to each other by a separately provided interposer. The semiconductor device described. 8. The semiconductor device according to claim 1, wherein the combination of the interposer and the stiffener base is stacked three-dimensionally upward to form a module structure. 9. The semiconductor device according to claim 1, wherein the semiconductor chip is potted and sealed with a liquid resin. 10. The semiconductor device according to claim 1, wherein the semiconductor chip has a heat radiating plate and a pedestal for mounting the heat radiating plate on the back side thereof. 11. The semiconductor device according to claim 1, wherein the through hole connecting the circuit pattern has an address.