JPH07175711A - データ処理システムにおけるデータ探索方法およびアクティブメモリ - Google Patents

データ処理システムにおけるデータ探索方法およびアクティブメモリ

Info

Publication number
JPH07175711A
JPH07175711A JP6116799A JP11679994A JPH07175711A JP H07175711 A JPH07175711 A JP H07175711A JP 6116799 A JP6116799 A JP 6116799A JP 11679994 A JP11679994 A JP 11679994A JP H07175711 A JPH07175711 A JP H07175711A
Authority
JP
Japan
Prior art keywords
data
memory
search
circuit
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6116799A
Other languages
English (en)
Japanese (ja)
Inventor
Pawate Basabaraji
パワテ バサバラジ
George Doddington
ディー．ドッディントン ジョージ
Shivaling S Mahant-Shetti
エス．マハント − シェッティ シバリング
Derek Smith
スミス デレック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH07175711A publication Critical patent/JPH07175711A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4804—Associative memory or processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Microcomputers (AREA)
  • Complex Calculations (AREA)
JP6116799A 1993-05-28 1994-05-30 データ処理システムにおけるデータ探索方法およびアクティブメモリ Pending JPH07175711A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/069,308 US5528550A (en) 1993-05-28 1993-05-28 Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit
US069308 1993-05-28

Publications (1)

Publication Number Publication Date
JPH07175711A true JPH07175711A (ja) 1995-07-14

Family

ID=22088098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6116799A Pending JPH07175711A (ja) 1993-05-28 1994-05-30 データ処理システムにおけるデータ探索方法およびアクティブメモリ

Country Status (4)

Country Link
US (1) US5528550A (forum.php)
EP (1) EP0629942A1 (forum.php)
JP (1) JPH07175711A (forum.php)
TW (1) TW260764B (forum.php)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3603440B2 (ja) * 1996-01-12 2004-12-22 富士通株式会社 半導体記憶装置
US5953738A (en) * 1997-07-02 1999-09-14 Silicon Aquarius, Inc DRAM with integral SRAM and arithmetic-logic units
US6366999B1 (en) * 1998-01-28 2002-04-02 Bops, Inc. Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
US6665790B1 (en) * 2000-02-29 2003-12-16 International Business Machines Corporation Vector register file with arbitrary vector addressing
US7119576B1 (en) 2000-09-18 2006-10-10 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US7346644B1 (en) 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US9015390B2 (en) * 2003-04-25 2015-04-21 Micron Technology, Inc. Active memory data compression system and method
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US20070185870A1 (en) 2006-01-27 2007-08-09 Hogue Andrew W Data object visualization using graphs
US8954426B2 (en) * 2006-02-17 2015-02-10 Google Inc. Query language
US8266198B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8266199B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8041759B1 (en) 2006-02-09 2011-10-18 Altera Corporation Specialized processing block for programmable logic device
US7836117B1 (en) 2006-04-07 2010-11-16 Altera Corporation Specialized processing block for programmable logic device
US7822799B1 (en) 2006-06-26 2010-10-26 Altera Corporation Adder-rounder circuitry for specialized processing block in programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US8954412B1 (en) 2006-09-28 2015-02-10 Google Inc. Corroborating facts in electronic documents
US20080133817A1 (en) * 2006-12-04 2008-06-05 Ulrich Brandt Memory module, memory controller, communication unit, and method of operating
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US7814137B1 (en) 2007-01-09 2010-10-12 Altera Corporation Combined interpolation and decimation filter for programmable logic device
US7865541B1 (en) 2007-01-22 2011-01-04 Altera Corporation Configuring floating point operations in a programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US8645450B1 (en) 2007-03-02 2014-02-04 Altera Corporation Multiplier-accumulator circuitry and methods
US7949699B1 (en) 2007-08-30 2011-05-24 Altera Corporation Implementation of decimation filter in integrated circuit device using ram-based data storage
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8244789B1 (en) 2008-03-14 2012-08-14 Altera Corporation Normalization of floating point operations in a programmable integrated circuit device
US8626815B1 (en) 2008-07-14 2014-01-07 Altera Corporation Configuring a programmable integrated circuit device to perform matrix multiplication
US8255448B1 (en) 2008-10-02 2012-08-28 Altera Corporation Implementing division in a programmable integrated circuit device
US8307023B1 (en) 2008-10-10 2012-11-06 Altera Corporation DSP block for implementing large multiplier on a programmable integrated circuit device
US7970964B2 (en) 2008-11-05 2011-06-28 Micron Technology, Inc. Methods and systems to accomplish variable width data input
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8886696B1 (en) 2009-03-03 2014-11-11 Altera Corporation Digital signal processing circuitry with redundancy and ability to support larger multipliers
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
US8549055B2 (en) 2009-03-03 2013-10-01 Altera Corporation Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US9606807B2 (en) * 2009-06-04 2017-03-28 Micron Technology, Inc. Direct communication with a processor internal to a memory device
US9535876B2 (en) * 2009-06-04 2017-01-03 Micron Technology, Inc. Conditional operation in an internal processor of a memory device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US7948267B1 (en) 2010-02-09 2011-05-24 Altera Corporation Efficient rounding circuits and methods in configurable integrated circuit devices
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8458243B1 (en) 2010-03-03 2013-06-04 Altera Corporation Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US20150089127A1 (en) * 2013-09-23 2015-03-26 Kuljit S. Bains Memory broadcast command
US9379687B1 (en) 2014-01-14 2016-06-28 Altera Corporation Pipelined systolic finite impulse response filter
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5113507A (en) * 1988-10-20 1992-05-12 Universities Space Research Association Method and apparatus for a sparse distributed memory system
JP2960533B2 (ja) * 1990-11-30 1999-10-06 株式会社日立製作所 記号列検索モジュール及びそれを備えたシングルチップマイクロコンピュータ
US5390139A (en) * 1993-05-28 1995-02-14 Texas Instruments Incorporated Devices, systems and methods for implementing a Kanerva memory

Also Published As

Publication number Publication date
TW260764B (forum.php) 1995-10-21
US5528550A (en) 1996-06-18
EP0629942A1 (en) 1994-12-21

Similar Documents

Publication Publication Date Title
JPH07175711A (ja) データ処理システムにおけるデータ探索方法およびアクティブメモリ
US5500828A (en) Apparatus, system and methods for distributed signal processing
US6631439B2 (en) VLIW computer processing architecture with on-chip dynamic RAM
US6223279B1 (en) Single chip microcomputer having a dedicated address bus and dedicated data bus for transferring register bank data to and from an on-line RAM
US7404066B2 (en) Active memory command engine and method
KR100415417B1 (ko) 이미지-처리프로세서
US7568086B2 (en) Cache for instruction set architecture using indexes to achieve compression
KR100268747B1 (ko) 데이터 처리 장치
US6510510B1 (en) Digital signal processor having distributed register file
US4872133A (en) Floating-point systolic array including serial processors
KR100287355B1 (ko) 그래픽/영상을 처리하기 위한 스마트 비디오 메모리 및 그 처리 방법
US20020023201A1 (en) VLIW computer processing architecture having a scalable number of register files
US8341328B2 (en) Method and system for local memory addressing in single instruction, multiple data computer system
JPH06215160A (ja) データ処理方法および装置
WO2005088640A9 (en) Improvements relating to orthogonal data memory
US6405233B1 (en) Unaligned semaphore adder
US7080234B2 (en) VLIW computer processing architecture having the problem counter stored in a register file register
Yamashita et al. A 3.84 GIPS integrated memory array processor LSI with 64 processing elements and 2 Mb SRAM
JPS62151940A (ja) レジスタ退避／復帰方式
US5928350A (en) Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle
EP0626659A1 (en) Apparatus, system and method for distributed processing
EP0226103A2 (en) Address generation for cellular array processors
Loughlin High-Speed Systolic Array Testbed.
JPH06168177A (ja) パイプラインメモリ装置
JPS60157632A (ja) 演算処理装置

Legal Events

Date Code Title Description
A977 Report on retrieval

Effective date: 20050607

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050705

A02 Decision of refusal

Effective date: 20051206

Free format text: JAPANESE INTERMEDIATE CODE: A02