JPH07170090A - Hybrid integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the influence of an electric field between circuits in a hybrid integrated circuit device using an FET carrier and to miniaturize the device. CONSTITUTION:In a hybrid integrated circuit device, FET carriers 6, 7 on which FETs have been formed are mounted on a dielectric circuit board 2 inside one package and circuits are formed. In the hybrid integrated circuit device, isolation grooves 8 are formed in the dielectric circuit board 2 so as to cover its whole thickness in positions between a plurality of circuits 11 to 14 constituted of the FET carriers, and an electric field which is generated between the circuits is cut off by the isolation grooves 8. By preventing the influence of the electric field between the circuits, the operation of the hybrid integrated circuit device is stabilized, the interval between the circuits can be reduced, and the device can be minaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which a high frequency circuit is constructed by using FETs.

[0002]

2. Description of the Related Art An example of a conventional hybrid integrated circuit device of this type is shown in FIG. This circuit is an example of a hybrid integrated circuit in which a UHF three-stage amplifier using an FET carrier is configured as shown in the equivalent circuit in FIG. Two carrier openings 22 and 23 are formed in the alumina substrate 21, and the first FET carrier 24 and the second FET opening are formed in the carrier openings 22 and 23.
The FET carrier 25 is mounted. Further, on the surface of the alumina substrate 21, the input circuit 11 and the first inter-stage circuit 1
2, the second inter-stage circuit 13 and the output circuit 14 are formed by a film circuit, and the first and second FET carriers 24, 2 are formed.
5 is electrically connected to the lead terminal. Here, 1st floor
One GaAs FET is incorporated in the ET carrier 24, and its gate terminal and drain terminal are connected to the lead terminal. In addition, the second FET carrier 25 has 2
Each GaAs FET is built in, and each gate terminal and drain terminal is connected to the lead terminal.
Reference numeral 26 is a chip capacitor.

However, in such a hybrid integrated circuit device, since the circuit distance between the first interstage circuit 12 and the output circuit 14 is particularly short, the mutual isolation of the circuits becomes low, and the first interstage circuit 12 and Due to the high frequency potential difference between the output circuit 14 and the output circuit 14, an electric field is easily generated between them. FIG. 8 is a view showing that state, and is a cross-sectional view of the alumina substrate 21 taken along the line DD of FIG. When such an electric field is generated, a coupling capacitance CX as indicated by a broken line in FIG. 7 is equivalently connected between the first inter-stage circuit 12 and the output circuit 14, which causes the output circuit 14 to be connected.
Therefore, there is a problem that a feedback circuit is generated from the first interstage circuit 12 to a desired characteristic not being realized, and a positive feedback loop is generated to cause oscillation.

In order to prevent this, the first interstage circuit 1
Although it is sufficient to increase the distance between the circuit 2 and the output circuit 14, this increases the size of the alumina substrate, which is an obstacle to downsizing of the hybrid integrated circuit device. That is, since the FET carrier including a plurality of FETs such as the second FET carrier 25 is originally intended to reduce the size of the circuit, the lead terminal interval is 2.54 m, for example.
It is designed to be as narrow as m. On the other hand, performance of the hybrid integrated circuit device, for example in 900MH _Z amplifier gain 30dB is desired in the 2FET carrier 25. Therefore, the distance between the first inter-stage circuit 12 and the output circuit 14 is set to 10 mm, and the mutual inter-circuit isolation 4 is set.
In order to secure 0 dB or more, it is necessary to design the size of the alumina substrate 21 to be at least 20 × 18 mm or more.

As a means for dealing with such a problem, there has been proposed, for example, in Japanese Patent Application Laid-Open No. 56-13759. As shown in FIG. 9, this structure has an alumina substrate 3
A film circuit 32 is formed on the surface of No. 1 and a plurality of FET elements 33A to 33D are formed on the surface of the alumina substrate 31.
To form a hybrid integrated circuit device. And each F
A circuit 35 is configured by the ET element 33 and the membrane circuit 32, and a ground conductor pattern 34 is provided between each circuit as a part of the membrane circuit. The ground conductive pattern 34 surrounds each circuit in an island shape. It has a structure. With this structure, as shown in the sectional structure of line EE in FIG.
The ground conductor pattern 34 has the effect of blocking the electric field between the T element and the circuit, and the problems such as feedback can be alleviated.

[0006]

However, even with such a configuration, when the size between each FET element or circuit and the ground conductor pattern 34 is small, or when the size between each FET element or circuit is small. Is the ground conductor pattern 34
It is difficult to obtain a sufficient effect of blocking the electric field due to. For this reason, it is necessary to maintain the size between each FET element or circuit and the space between the FET element and the ground conductor pattern to be equal to or more than a predetermined size, and as a result, the miniaturization of the hybrid integrated circuit device is restricted.

Therefore, particularly in the hybrid integrated circuit device using the FET carrier integrally incorporating a plurality of FETs as shown in FIG. 8, the gate terminals and drain terminals of the respective FETs are arranged close to each other, and Since it is difficult to take large mutual dimensions, it is difficult to directly apply the technique described in the above-mentioned publication to such a device. An object of the present invention is to provide a hybrid integrated circuit device which is miniaturized while preventing the influence of electric fields between the circuits.

[0008]

According to the hybrid integrated circuit device of the present invention, a FET is mounted on a dielectric circuit board having an FET carrier containing a plurality of FETs in one package.
Separation grooves are formed at a position between a plurality of circuits formed of carriers over the entire thickness thereof, and the separation grooves block the electric field generated between the circuits. This separation groove is FE
It is formed at a position for separating lead terminals respectively connected to a plurality of FETs incorporated in the T carrier. Alternatively, the separation groove is formed between the input side circuit and the output side circuit formed of the FET carrier.

[0009]

[Function] In order to prevent the influence of the electric field between the circuits by blocking the electric field between the circuits by the separation groove formed on the dielectric circuit board, abnormal oscillation is caused by the feedback from the output side circuit to the input side circuit. Prevent and stabilize the operation of the hybrid integrated circuit device. Further, even if the distance between the circuits is reduced, the influence of the electric field between the circuits can be avoided, and the device can be downsized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a plan view of a hybrid integrated circuit according to a first embodiment of the present invention, FIG.
(A) and (b) are AA line and B of FIG. 1, respectively.
It is sectional drawing which follows the -B line. In these figures, for example, the vertical and horizontal dimensions are 20 x 14 mm2 and the thickness is 0.5 mm.
A base metal 1 is formed of the copper plate, and an alumina substrate 2 having the same vertical and horizontal dimensions and a thickness of 0.8 mm is integrally connected to the surface of the base metal 1 by tin-lead solder. A film circuit pattern 3 is formed on the surface of the alumina substrate 2 by, for example, a thick film printing method of copper paste. Further, first and second carrier openings 4 and 5 are formed at required locations on the alumina substrate 2, here, at two locations, and the FET carriers 6 and 6 are provided in the respective carrier openings 4 and 5. 7 are decorated.

Here, the carrier openings 4 and 5 are formed over the entire thickness of the alumina substrate 2, and the FET carriers 6 and 7 are formed of the base metal 1 exposed in the openings 4 and 5. Mounted directly on the surface. Further, the alumina substrate 2 between the carrier openings 4 and 5 is formed with a separation groove 8 communicating the carrier openings 4 and 5, and the separation groove 8 also covers the entire thickness of the alumina substrate 2. Has been formed. These carrier openings 4,
5 and the separation groove 8 can be easily formed, for example, in the manufacturing process of the alumina substrate 2 by punching out the carrier openings 4, 5 and the separation groove 8 with a mold before firing and firing. The width of the separation groove 8 is about 0.8 mm.

Of the FET carriers 6 and 7, the first FET carrier 6 is one GaAs in one carrier.
The FET is built in, the source terminal is connected to the ground plane of the carrier, and the gate terminal and the drain terminal are F
It is connected to a lead terminal protruding from the opposite side of the package of the ET carrier 6. Further, the second FET carrier 7 has a configuration in which two lead terminals 7a to 7d are respectively projected to the left and right as shown in the conceptual configuration diagram in FIG. 3, and the first FET 2 and the second FET 2 are provided in the carrier. GaAs
It has FETs Q1 and Q2. These FET Q
1 and Q2 are formed on a gallium arsenide substrate having a length and width of 0.8 × 1.2 mm2 and a thickness of 0.14 mm, for example. The source terminal of each FET is connected to the ground plane of the carrier, and the gate terminal and drain terminal are connected to the lead terminals 7a to 7d, respectively. At this time, the wiring inside the carrier is performed so that the gate terminal of one FET and the drain terminal of the other FET are connected to the lead terminal on the same side of the carrier so that no external circuit crossing is required.

Further, the membrane circuit pattern 3 has chip components 9 such as chip capacitors mounted at predetermined positions, whereby an input circuit 11, a first interstage circuit 12,
The second inter-stage circuit 13 and the output circuit 14 are configured. In this case, the first inter-stage circuit 11 and the output circuit 14 connected to the second FET carrier 7 are formed in the region separated by the separation groove 8 described above. And the first F
The ET carrier 6 is mounted in the first carrier opening 4, and its lead terminal is connected to the input circuit 11 and the first interstage circuit 12
Connect to one end of. Also, the second FET Killia 7 is
The gate terminal of the first FET Q1 is connected to the other end of the first interstage circuit 12, and the drain terminal is connected to one end of the second interstage circuit 13. The gate terminal of the second FET Q2 is connected to the other end of the second interstage circuit 13, and the drain terminal is connected to the output circuit 14. The source terminals are grounded to the base metal 1 through the ground planes of the FET carriers 6 and 7, respectively.

Therefore, according to this configuration, the second FE
Of the first and second FETs integrated inside the T carrier 7, the first inter-stage circuit 12 to which the gate terminal of the first FET Q1 is connected and the drain terminal of the second FET Q2 are The output circuit 14 to be connected is formed on the same alumina substrate 2, but is separated via the separation groove 8. Therefore, as shown in the electric field state along the line CC in FIG. 1, even if the electric fields in the circuits 12 and 14 occur inside the alumina substrate, they are separated by the separation groove 8 and interfere with each other. Is prevented. For example, since the relative permittivity εr of the alumina substrate 2 is 10 and that of the separation groove 8 is εr of air, the electric field passing through the separation groove 8 is small. Therefore, the coupling capacitance due to the electric field as shown in FIG. 8 does not occur between the first interstage circuit 12 and the output circuit 14, and the feedback circuit from the output circuit 14 to the first interstage circuit 12 is provided. It never happens. As a result, problems such as oscillation can be prevented.

Further, since the width of the separation groove can be formed narrower than that in the case of using the ground circuit pattern as shown in FIG. 9, it is effective for downsizing the integrated circuit device. By the way, if the spacing between circuits is the same as before,
In this embodiment, the isolation can be reduced by 8 dB. In addition, the alumina substrate 2 with a plate thickness of 0.8 mm
In order to obtain a 40dB isolation is 0MH _Z, spacing between the circuit can be reduced from a conventional 10mm to 4 mm, it can be miniaturized.

FIG. 5 is a plan view of the hybrid integrated circuit according to the second embodiment of the present invention. In this embodiment, one second carrier opening 5A provided on the alumina substrate 2 is used as a second carrier of the second embodiment.
The same FET carrier 7A as the FET carrier is mounted. Further, an input circuit 11A, an interstage circuit 12A, and an output circuit 14A are formed around the carrier opening 5A,
The gate terminal and drain terminal of the first FET in the FET carrier 7A are connected to the input circuit 11A and the interstage circuit 12A, respectively, and the gate terminal and drain terminal of the second FET are connected to the interstage circuit 12A and the output circuit 14A, respectively.
Then, between the lead terminals on the same side of the FET carrier on opposite sides of the carrier opening 5A, a separation groove 8A having a width of 0.8 mm and a length of about 3 mm is formed over the entire thickness of the alumina substrate 2. The lead terminals on the same side are separated by the separation groove 8A. This separation groove 8
The length of 3 mm of A is the length of each lead terminal (about 1.5 m
It is more than twice the length of m). In addition, 9 is a chip component.

Therefore, also in this structure, the gate terminal and the drain terminal of each of the first and second FETs in the FET carrier 7A are separated by the separation groove 8A, and the input circuit 11A and the stage connected to these terminals are connected. Circuit 12
A and the output circuit 14A are separated from each other. As a result, it is possible to prevent an electric field from being formed between the mutual circuits via the alumina substrate 2, and the output circuit 14A to the input circuit 11 can be prevented.
Return to A can be prevented.

It is needless to say that the present invention is not limited to the hybrid integrated circuit device having the above-mentioned circuit configuration, but can be applied to other circuit configurations. Further, the width and length of the separation groove can be appropriately designed depending on the strength of the electric field.

[0019]

As described above, according to the present invention, an isolation groove is formed over the entire thickness of a dielectric circuit board between a plurality of circuits composed of FET carriers, and an electric field generated between the circuits by the isolation groove. Since the circuit is cut off, it is possible to prevent the influence of the electric field between the circuits, prevent abnormal oscillation due to feedback from the output side circuit to the input side circuit, etc., and stabilize the operation of the hybrid integrated circuit device. . Further, even if the distance between the circuits is reduced, the influence of the electric field between the circuits can be avoided, and the device can be downsized.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of a hybrid integrated circuit device of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA and the line BB of FIG.

FIG. 3 is a diagram showing an internal structure of an FET carrier.

FIG. 4 is a diagram showing an electric field state at a CC line portion in the hybrid integrated circuit device of FIG.

FIG. 5 is a plan view of a second embodiment of the hybrid integrated circuit device of the present invention.

FIG. 6 is a plan view of an example of a conventional hybrid integrated circuit device.

7 is an equivalent circuit diagram of the circuit device of FIG.

8 is a diagram showing an electric field state at a portion taken along the line DD of FIG.

FIG. 9 is a plan view of a conventional hybrid integrated circuit device having a circuit disconnection effect.

FIG. 10 is a diagram showing an electric field state at a portion taken along line EE in FIG.

[Explanation of symbols]

 1 Base Metal 2 Alumina Substrate 3 Membrane Circuit Pattern 4, 5 Carrier Opening 6, 7 FET Carrier 8, 8A Separation Groove 11, 11A Input Circuit 12, 13, 12A Interstage Circuit 14, 14A Output Circuit

─────────────────────────────────────────────────── ───Continued from the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical indication H05K 1/18 S 7128-4E

Claims (4)

[Claims] 1. A hybrid integrated circuit device comprising an FET carrier containing a plurality of FETs in one package, the FET carrier being mounted on a dielectric circuit board to form a plurality of circuits. 2. A hybrid integrated circuit device characterized in that an isolation groove is formed over the entire thickness of the dielectric substrate between the circuits and the electric field generated between the circuits is blocked by the isolation groove. 2. The hybrid integrated circuit device according to claim 1, wherein the separation groove is formed at a position for separating lead terminals respectively connected to a plurality of FETs incorporated in the FET carrier. 3. The hybrid integrated circuit device according to claim 1, wherein the separation groove is formed between an input side circuit and an output side circuit which are composed of FET carriers. 4. A dielectric circuit board is mounted on a base metal, the dielectric circuit board is provided with an opening through which the base metal is exposed, and an FET carrier is mounted on the base metal in the opening, and a separation groove is provided. 4. The hybrid integrated circuit device according to claim 2, wherein is formed continuously with the opening.