JPH07169870A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH07169870A JPH07169870A JP5312164A JP31216493A JPH07169870A JP H07169870 A JPH07169870 A JP H07169870A JP 5312164 A JP5312164 A JP 5312164A JP 31216493 A JP31216493 A JP 31216493A JP H07169870 A JPH07169870 A JP H07169870A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- integrated circuit
- hollow portion
- case
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、中空式集積回路の製造
方法に係り、特に、集積回路内部の半導体チップ及びワ
イヤーボンディング部に中空部を形成する方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hollow integrated circuit, and more particularly to a method for forming a hollow portion in a semiconductor chip and a wire bonding portion inside the integrated circuit.
【０００２】[0002]
【従来の技術】従来から、封着樹脂による半導体チップ
の保護及びワイヤーボンディング部のストレス対策を目
的として、集積回路内部の半導体チップ及びワイヤーボ
ンディング部に中空部を形成する方法が採られている。
中空部の形成方法として、例えば、実開 昭６２−１８
０９４８号に示されている。2. Description of the Related Art Conventionally, a method of forming a hollow portion in a semiconductor chip and a wire bonding portion inside an integrated circuit has been adopted for the purpose of protecting the semiconductor chip with a sealing resin and preventing stress in the wire bonding portion.
As a method of forming the hollow portion, for example, the actual development of Sho 62-18
No. 0948.
【０００３】図３は従来の集積回路の樹脂ケースによる
封着構造を示す断面図である。以下、図に従って説明す
る。１は電子回路の形成された半導体チップで、周辺部
には半導体チップ１の回路をリード線３１に接続するた
めの複数のボンディングパッド（図示せず）を有する。
２は半導体チップ１を搭載する金属製のダイパッドであ
る。３１は集積回路をプリント基板等に実装するための
複数のリード線で、集積回路の完成直前までは複数のリ
ード線３１をフレームで連結したリードフレームの状態
で取り扱われる。４は半導体チップ１のボンディングパ
ッドとリード線３１を接続する金線等のワイヤーで、超
音波等によりワイヤーボンディングされる。５は樹脂製
のケースで、上ケース５１と下ケース５２より構成さ
れ、リード線３１を挟み込んで封着用樹脂５３等で封着
される。６は集積回路内部の中空部である。FIG. 3 is a sectional view showing a sealing structure of a conventional integrated circuit with a resin case. Hereinafter, description will be given with reference to the drawings. Reference numeral 1 denotes a semiconductor chip on which an electronic circuit is formed, and a peripheral portion has a plurality of bonding pads (not shown) for connecting the circuit of the semiconductor chip 1 to a lead wire 31.
Reference numeral 2 is a metal die pad on which the semiconductor chip 1 is mounted. Reference numeral 31 is a plurality of lead wires for mounting the integrated circuit on a printed circuit board or the like, and is handled in a lead frame state in which the plurality of lead wires 31 are connected by a frame until just before the completion of the integrated circuit. Reference numeral 4 denotes a wire such as a gold wire that connects the bonding pad of the semiconductor chip 1 and the lead wire 31 and is wire-bonded by ultrasonic waves or the like. Reference numeral 5 denotes a resin case, which is composed of an upper case 51 and a lower case 52, and is sandwiched with the lead wire 31 and sealed with a sealing resin 53 or the like. Reference numeral 6 is a hollow portion inside the integrated circuit.
【０００４】次に、製造方法について述べる。半導体チ
ップ１はダイパッド２上に接着剤等でダイボンディング
され、続いて、半導体チップ１の複数のボンディングパ
ッドとリード線３１の間を金線を用いて超音波等により
ワイヤーボンディングされる。ワイヤーボンディングの
完了したアセンブリーは上下から樹脂製のケース５１、
５２で封着用樹脂５３を介して封着された後、樹脂が硬
化されて集積回路は完成する。Next, a manufacturing method will be described. The semiconductor chip 1 is die-bonded onto the die pad 2 with an adhesive or the like, and subsequently, a plurality of bonding pads of the semiconductor chip 1 and the lead wires 31 are wire-bonded by ultrasonic waves or the like using a gold wire. The assembly after wire bonding is completed from the top and bottom with a resin case 51,
After being sealed at 52 via the sealing resin 53, the resin is cured and the integrated circuit is completed.
【０００５】また、別の封着方法として、セラミック製
のケースにボンディングの完了したアセンブリーを収容
して、セラミック製のケースをガラスで封着する方法が
ある。As another sealing method, there is a method of accommodating the bonded assembly in a ceramic case and sealing the ceramic case with glass.
【０００６】[0006]
【発明が解決しようとする課題】上述の図３の集積回路
の中空構造では、樹脂製の蓋をする際に、温度変化によ
りシール剤にブローホールができ、封着が不完全にな
り、湿度等で集積回路が劣化するおそれがある。また、
セラミック製のパッケージは封着の信頼性は高いが高価
になるという問題がある。従って本発明は、集積回路内
部に容易に中空部を形成する方法を提供することを目的
とする。In the hollow structure of the integrated circuit of FIG. 3 described above, when the lid made of resin is used, blowholes are formed in the sealant due to temperature changes, the sealing is incomplete, and the humidity is insufficient. There is a risk that the integrated circuit will deteriorate due to such reasons. Also,
A ceramic package has a problem that the sealing is highly reliable but expensive. Therefore, it is an object of the present invention to provide a method for easily forming a hollow portion inside an integrated circuit.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明は、半導体チップとリード線がワイヤーでボン
ディングされた半導体アセンブリーの周囲に中空部が形
成されてなる集積回路において、加熱により気化または
液化する中空部形成材と、前記半導体アセンブリーを収
容する前記気体または液体を排出する排出孔が設けられ
たケースと、前記ケース内に半導体アセンブリーととも
に充填される樹脂で構成され、前記半導体アセンブリー
の周囲に前記中空部形成材を塗布して前記ケース内に収
納し、前記樹脂を充填して、硬化させた後、加熱して前
記中空部形成材を気化または液化させて、前記ケースの
排出孔より排出させて、集積回路内部に中空部を形成す
ることを特徴とするものである。In order to achieve the above-mentioned object, the present invention provides an integrated circuit in which a hollow portion is formed around a semiconductor assembly in which a semiconductor chip and a lead wire are bonded by a wire, and vaporizes by heating. Alternatively, the semiconductor assembly includes a hollow portion forming material that is liquefied, a case that is provided with a discharge hole that discharges the gas or the liquid that contains the semiconductor assembly, and a resin that is filled with the semiconductor assembly in the case. The hollow-portion forming material is applied to the periphery and housed in the case, and the resin is filled and cured, and then heated to vaporize or liquefy the hollow-portion forming material, and the discharge hole of the case. It is characterized in that it is further discharged to form a hollow portion inside the integrated circuit.
【０００８】また、半導体チップとリード線がワイヤー
でボンディングされた半導体アセンブリーの周囲に中空
部が形成されてなる集積回路において、前記半導体アセ
ンブリーの周囲に樹脂剥離剤を塗布してケース内に収納
し、樹脂を充填して、硬化させて、樹脂の収縮により集
積回路内部に中空部を形成することを特徴とするもので
ある。Also, in an integrated circuit in which a hollow portion is formed around a semiconductor assembly in which a semiconductor chip and a lead wire are bonded by a wire, a resin release agent is applied to the periphery of the semiconductor assembly and the resin is housed in a case. It is characterized in that the resin is filled and cured to form a hollow portion inside the integrated circuit by contraction of the resin.
【０００９】[0009]
【作用】本発明の第１の発明によれば、半導体チップと
リード線とのボンディング部に塗布された中空部形成材
と、樹脂で集積回路の封着が完成し、その後、集積回路
を加熱することにより内部の中空部形成材が気体または
液体となって、ケースの排出孔より排出され、中空部形
成材の部分に中空部ができる。According to the first aspect of the present invention, the sealing of the integrated circuit is completed with the hollow portion forming material applied to the bonding portion between the semiconductor chip and the lead wire and the resin, and then the integrated circuit is heated. By doing so, the hollow portion forming material inside becomes gas or liquid and is discharged from the discharge hole of the case, and a hollow portion is formed in the hollow portion forming material portion.
【００１０】また、第２の発明によれば、半導体チップ
とリード線とのボンディング部に塗布された剥離剤と樹
脂で集積回路の封着が完成し、その後、樹脂の硬化によ
る収縮で剥離剤を介して、半導体チップと該ワイヤーボ
ンディング部の周囲に中空部ができる。Further, according to the second aspect of the invention, the sealing of the integrated circuit is completed by the release agent applied to the bonding portion between the semiconductor chip and the lead wire and the resin, and then the release agent is contracted by the curing of the resin. A hollow portion is formed around the semiconductor chip and the wire bonding portion via.
【００１１】[0011]
【実施例】図１は本発明の一実施例の集積回路の完成断
面図と封着前平面図である。以下、図に従って説明す
る。１は電子回路の形成された半導体チップで、周辺部
には半導体チップ１の回路をリード線３１に接続するた
めの複数のボンディングパッド１１を有する。２は半導
体チップ１を搭載する金属製のダイパッドで、完成直前
まではフレーム３３に接続される支持板３２により連結
したリードフレーム３の状態で取り扱われる。３１は集
積回路のプリント基板等に実装される複数のリード線
で、完成直前までは複数のリード線３１をフレーム３３
で連結したリードフレーム３の状態で取り扱われる。４
は半導体チップ１のボンディングパッド１１とリード線
３１を接続する金線等のワイヤーで、超音波等によりワ
イヤーボンディングされる。７は加熱により液化する中
空部形成材である。尚、この中空部形成材７は集積回路
内部に充填される樹脂８５の硬化温度（Ｔａ）よりも高
い温度で（Ｔｂ）液化するものである。８は半導体チッ
プ１，ダイパッド２，リード線３１等からなるアセンブ
リーを収容するケースで、樹脂製のケース８１と、中空
部形成材７の加熱により発生する液体を排出する排出孔
８４が設けられた樹脂板８２で構成される。８５はケー
ス８１の内部に充填された熱硬化性の樹脂である。１６
は集積回路内部の中空部である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a completed sectional view and a plan view before sealing of an integrated circuit according to an embodiment of the present invention. Hereinafter, description will be given with reference to the drawings. Reference numeral 1 denotes a semiconductor chip on which an electronic circuit is formed, and a peripheral portion has a plurality of bonding pads 11 for connecting the circuit of the semiconductor chip 1 to a lead wire 31. Reference numeral 2 denotes a metal die pad on which the semiconductor chip 1 is mounted, which is handled as a lead frame 3 connected by a support plate 32 connected to a frame 33 until just before completion. Reference numeral 31 is a plurality of lead wires mounted on a printed circuit board of an integrated circuit.
It is handled in the state of the lead frame 3 connected by. Four
Is a wire such as a gold wire that connects the bonding pad 11 of the semiconductor chip 1 and the lead wire 31 and is wire-bonded by ultrasonic waves or the like. Reference numeral 7 is a hollow portion forming material which is liquefied by heating. The hollow portion forming material 7 is liquefied at a temperature (Tb) higher than the curing temperature (Ta) of the resin 85 filled in the integrated circuit. Reference numeral 8 denotes a case for accommodating an assembly composed of the semiconductor chip 1, the die pad 2, the lead wire 31 and the like. It is composed of a resin plate 82. Reference numeral 85 is a thermosetting resin filled inside the case 81. 16
Is a hollow portion inside the integrated circuit.
【００１２】次に、製造方法について述べる。半導体チ
ップ１はダイパッド２上に接着剤等でダイボンディング
され、続いて、半導体チップ１の複数のボンディングパ
ッド１１とリード線３１の間を金線を用いて超音波等に
よりワイヤーボンディングされる。ワイヤーボンディン
グの完了したアセンブリーは、樹脂板８２上に載せられ
て、半導体チップ１部及びワイヤーボンディング部４１
を覆うように例えば、ウレタンプレポリマー、ホットメ
ルト材料等の中空部形成材７が塗布され乾燥される。次
に、樹脂製のケース８１内に例えば、シリコンゴム等の
熱硬化性の樹脂８５が充填され、その上に中空部形成材
７が塗布されたアセンブリーが置かれ、アセンブリー全
体が樹脂で覆われ、加熱されて（加熱温度Ｔａ＝１２０
℃）樹脂が硬化される。Next, the manufacturing method will be described. The semiconductor chip 1 is die-bonded on the die pad 2 with an adhesive or the like, and subsequently, a plurality of bonding pads 11 of the semiconductor chip 1 and the lead wires 31 are wire-bonded by ultrasonic waves using a gold wire. The assembly with the completed wire bonding is placed on the resin plate 82, and the semiconductor chip 1 part and the wire bonding part 41 are mounted.
A hollow portion forming material 7 such as a urethane prepolymer or a hot melt material is applied so as to cover the above and is dried. Next, for example, a thermosetting resin 85 such as silicon rubber is filled in the resin case 81, the assembly coated with the hollow portion forming material 7 is placed thereon, and the entire assembly is covered with the resin. , Heated (heating temperature Ta = 120
The resin is cured.
【００１３】次に、樹脂硬化の完了した集積回路は樹脂
硬化温度（加熱温度Ｔａ＝１２０℃）より高い温度（例
えば、加熱温度Ｔｂ＝１５０℃）で加熱されることによ
り、内部の中空部形成材７のウレタンプレポリマー等が
液化して、樹脂板８２の排出孔８４から排出される。こ
の温度ならば、充填された樹脂８５は軟化せずそのまま
の形状を保持しているために、中空部形成材７が排出さ
れた跡には中空部１６が形成されている。その後、樹脂
ケース８２の排出孔８４が熱硬化性樹脂８６等で塞が
れ、さらに、リード線３１及び支持板３２がＡ−Ａの部
分で切断されて集積回路が完成する。Next, the resin-cured integrated circuit is heated at a temperature (for example, heating temperature Tb = 150 ° C.) higher than the resin curing temperature (heating temperature Ta = 120 ° C.) to form an internal hollow portion. The urethane prepolymer or the like of the material 7 is liquefied and discharged from the discharge hole 84 of the resin plate 82. At this temperature, the filled resin 85 does not soften and retains the shape as it is, so that the hollow portion 16 is formed at the trace of the hollow portion forming material 7 being discharged. After that, the discharge hole 84 of the resin case 82 is closed by the thermosetting resin 86 and the like, and the lead wire 31 and the support plate 32 are further cut at the AA portion to complete the integrated circuit.
【００１４】以上のように本実施例では、中空部を形成
する部分に中空部形成材を塗布し、加熱して中空部形成
材７を液化してケース外へ排出することにより簡単にア
センブリー周囲に中空部１６が形成できる。また、図２
は本発明の第２の実施例の集積回路の断面図である。以
下、図に従って説明する。As described above, in the present embodiment, the hollow portion forming material is applied to the portion forming the hollow portion, and the hollow portion forming material 7 is liquefied and discharged to the outside of the case by simply liquefying the hollow portion forming material 7 and discharging it from the case. The hollow portion 16 can be formed in Also, FIG.
FIG. 6 is a sectional view of an integrated circuit according to a second embodiment of the present invention. Hereinafter, description will be given with reference to the drawings.
【００１５】１は電子回路の形成された半導体チップ
で、周辺部には半導体チップ１の回路をリード線３１に
接続するための複数のボンディングパッドを有する。２
は半導体チップ１を搭載する金属製のダイパッドであ
る。３１は集積回路をプリント基板等に実装するための
複数のリード線で完成直前までは複数のリード線３１を
フレームで連結したリードフレームの状態で取り扱われ
る。４は半導体チップ１のボンディングパッドとリード
線３１を接続する金線等のワイヤーで、超音波等により
ワイヤーボンディングされる。７１はシリコンオイル等
の樹脂剥離剤である。９はアセンブリーを収容するケー
スで、樹脂製のケース９１と、樹脂板９２で構成され
る。８７は樹脂製ケース９１の内部に充填された熱硬化
性の樹脂である。２６は集積回路内部の中空部である。Reference numeral 1 denotes a semiconductor chip on which an electronic circuit is formed, and a peripheral portion has a plurality of bonding pads for connecting the circuit of the semiconductor chip 1 to a lead wire 31. Two
Is a metal die pad on which the semiconductor chip 1 is mounted. Reference numeral 31 denotes a plurality of lead wires for mounting the integrated circuit on a printed circuit board or the like, and is handled in a lead frame state in which the plurality of lead wires 31 are connected by a frame until just before completion. Reference numeral 4 denotes a wire such as a gold wire that connects the bonding pad of the semiconductor chip 1 and the lead wire 31 and is wire-bonded by ultrasonic waves or the like. 71 is a resin peeling agent such as silicone oil. Reference numeral 9 denotes a case for accommodating the assembly, which includes a resin case 91 and a resin plate 92. Reference numeral 87 is a thermosetting resin filled in the resin case 91. 26 is a hollow portion inside the integrated circuit.
【００１６】次に、製造方法について述べる。半導体チ
ップ１はダイパッド２上に接着剤等でダイボンディング
され、続いて、半導体チップ１の複数のボンディングパ
ッド１１とリード線３１の間を金線を用いて超音波等に
よりワイヤーボンディングされる。ワイヤーボンディン
グの完了したアセンブリーは、半導体チップ１部及びワ
イヤーボンディング部を覆うようにシリコンオイル等の
剥離剤７１が塗布される。次に、樹脂製のケース９１内
に熱硬化性の樹脂８７が充填され、その上に剥離剤７１
が塗布されたアセンブリーが置かれ、アセンブリー全体
が樹脂で覆われ、樹脂板９２で蓋をされる。その後、加
熱されて樹脂８７が硬化される。樹脂８７が冷却される
と、樹脂８７が収縮して剥離剤７１の塗布された周囲に
中空部２６が形成される。その後、リード線３１がフレ
ームの部分で切断されて集積回路は完成する。Next, the manufacturing method will be described. The semiconductor chip 1 is die-bonded on the die pad 2 with an adhesive or the like, and subsequently, a plurality of bonding pads 11 of the semiconductor chip 1 and the lead wires 31 are wire-bonded by ultrasonic waves using a gold wire. The wire bonding completed assembly is coated with a release agent 71 such as silicon oil so as to cover the semiconductor chip 1 part and the wire bonding part. Next, a thermosetting resin 87 is filled in a resin case 91, and a release agent 71 is placed on the thermosetting resin 87.
The assembly to which is applied is placed, the entire assembly is covered with resin, and the assembly is covered with a resin plate 92. After that, the resin 87 is heated and hardened. When the resin 87 is cooled, the resin 87 contracts and the hollow portion 26 is formed around the release agent 71. After that, the lead wire 31 is cut at the frame portion to complete the integrated circuit.
【００１７】以上のように本実施例では、中空部を形成
する部分に剥離剤を塗布するだけで簡単に中空部が形成
できる。As described above, in this embodiment, the hollow portion can be easily formed only by applying the release agent to the portion forming the hollow portion.
【００１８】[0018]
【発明の効果】以上説明したように、本発明では半導体
チップおよびワイヤーボンディング部に中空部形成材ま
たは樹脂剥離剤を塗布するだけで、大した製造設備の変
更なしに、簡単に中空部が形成でき、コスト低減と信頼
性の確保が図られる。As described above, according to the present invention, the hollow portion can be easily formed by simply applying the hollow portion forming material or the resin release agent to the semiconductor chip and the wire bonding portion without changing the manufacturing equipment. The cost can be reduced and the reliability can be ensured.
【図１】本発明の一実施例の集積回路の完成断面図と封
着前平面図。FIG. 1 is a completed sectional view and a plan view before sealing of an integrated circuit according to an embodiment of the present invention.
【図２】本発明の第２の一実施例の集積回路の断面図。FIG. 2 is a sectional view of an integrated circuit according to a second embodiment of the present invention.
【図３】従来の集積回路の断面図。FIG. 3 is a cross-sectional view of a conventional integrated circuit.
１・・・半導体チップ ２・・・ダイボンディングパッド ３１・・・リード線 ４・・・ワイヤー ５、８、９・・・ケース ６、１６、２６・・・中空部 1 ... Semiconductor chip 2 ... Die bonding pad 31 ... Lead wire 4 ... Wire 5, 8, 9 ... Case 6, 16, 26 ... Hollow part
Claims (2)
ンディングされた半導体アセンブリーの周囲に中空部が
形成されてなる集積回路において、 加熱により気化または液化する中空部形成材と、 前記半導体アセンブリーを収容する前記気体または液体
を排出する排出孔が設けられたケースと、 前記ケース内に半導体アセンブリーとともに充填される
樹脂で構成され、 前記半導体アセンブリーの周囲に前記中空部形成材を塗
布して前記ケース内に収納し、前記樹脂を充填して、硬
化させた後、加熱して前記中空部形成材を気化または液
化させて、前記ケースの排出孔より排出させて、集積回
路内部に中空部を形成することを特徴とする集積回路の
製造方法。1. An integrated circuit in which a hollow portion is formed around a semiconductor assembly in which a semiconductor chip and a lead wire are bonded by a wire, and a hollow portion forming material which is vaporized or liquefied by heating and the semiconductor assembly is housed. A case provided with a discharge hole for discharging the gas or the liquid, and a resin that is filled with the semiconductor assembly in the case. The hollow portion forming material is applied to the periphery of the semiconductor assembly to form the case inside the case. After storing, filling with the resin and curing, heating to vaporize or liquefy the hollow portion forming material and discharge from the discharge hole of the case to form a hollow portion inside the integrated circuit. And a method of manufacturing an integrated circuit.
ンディングされた半導体アセンブリーの周囲に中空部が
形成されてなる集積回路において、 前記半導体アセンブリーの周囲に樹脂剥離剤を塗布して
ケース内に収納し、樹脂を充填して、硬化させて、樹脂
の収縮により集積回路内部に中空部を形成することを特
徴とする集積回路の製造方法。2. In an integrated circuit having a hollow portion formed around a semiconductor assembly in which a semiconductor chip and a lead wire are bonded by a wire, a resin release agent is applied to the periphery of the semiconductor assembly and is housed in a case. A method for manufacturing an integrated circuit, comprising: filling a resin, curing the resin, and then shrinking the resin to form a hollow portion inside the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5312164A JPH07169870A (en) | 1993-12-13 | 1993-12-13 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5312164A JPH07169870A (en) | 1993-12-13 | 1993-12-13 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07169870A true JPH07169870A (en) | 1995-07-04 |
Family
ID=18026010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5312164A Withdrawn JPH07169870A (en) | 1993-12-13 | 1993-12-13 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07169870A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681574A (en) * | 2012-08-31 | 2014-03-26 | 飞思卡尔半导体公司 | Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture |
| KR101398016B1 (en) * | 2012-08-08 | 2014-05-30 | 앰코 테크놀로지 코리아 주식회사 | Lead frame package and manufacturing method thereof |
-
1993
- 1993-12-13 JP JP5312164A patent/JPH07169870A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101398016B1 (en) * | 2012-08-08 | 2014-05-30 | 앰코 테크놀로지 코리아 주식회사 | Lead frame package and manufacturing method thereof |
| US9633932B2 (en) | 2012-08-08 | 2017-04-25 | Amkor Technology, Inc. | Lead frame package having discharge hole and method of manufacturing the same |
| CN103681574A (en) * | 2012-08-31 | 2014-03-26 | 飞思卡尔半导体公司 | Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010306 |