JPH07169284A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain an EEPROM capable of securing a sufficient writing voltage margin by gradually boosting writing voltage while repeating writing operation and verifying operation cycle for each bit. CONSTITUTION:An EEPROM cell having a matrix array is constituted by laminating a floating gate 3 of a electric charge accumulating layer and a control gate 1 on a (p) type well 6 on an (n) type silicon substrate 7. After control voltage Vcg0 having a pulse width of DELTAt is applied to this gate 1 as a high voltage pulse Vpp to perform writing operation, a control voltage pulse Vcg of which a pulse width is increased by DELTAt and voltage is boosted by DELTAVpp is applied, a verifying operation cycle is repeated, and quantity of electric charges injected to a memory cell is controlled. In this case, pulse width and quantity of boosting DELTAVpp of the voltage Vcg are selected so that the maximum quantity of variation DELTAVth of a threshold value Vth of a memory cell at the time of injecting electron at a first time is made equal to boosted DELTAVpp. By using this method, sufficient margin can be secured for writing voltage Vpp for each memory cell having different threshold values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to an EEPROM for writing / erasing a memory cell by a tunnel current.

[0002]

2. Description of the Related Art As one of the EEPROMs, a NAND cell type EEPROM capable of high integration is known. This is to connect a plurality of memory cells in series so that their sources and drains are shared by adjacent ones.
It is connected to the bit line as a unit. The memory cell usually has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the select gate, and the source side is also connected to the common source line via the select gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (about 20V) is applied to the control gate of the selected memory cell, and an intermediate voltage Vppm (= 10V) (= 10V) is applied to the control gate and the select gate of the memory cell on the bit line side.
V) is applied, and 0 V or an intermediate voltage Vm (= about 8 V) is applied to the bit line according to the data.

When 0V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electron injection occurs in the charge storage stack. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is set to "0", for example. When Vm is applied to the bit line, electron injection does not effectively take place, so that the threshold value remains unchanged and remains negative. This state is "1" in the erased state.
Data writing is simultaneously performed on memory cells sharing a control gate.

Data erasing is simultaneously performed on all the memory cells in the NAND cell. That is, all the control gates are set to 0V and the p-type well is set to 20V. At this time, the selection gate, the bit line and the source line are also set to 20V. As a result, in all memory cells, the electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction.

For data reading, whether or not a current flows in the selected memory cell with the control gate of the selected memory cell set to 0V and the control gates and the selection gates of the other memory cells set to the power supply potential Vcc (for example, 5V). Is detected.

Due to the limitation of the read operation, the threshold value after writing "0" must be controlled between 0V and Vcc. Therefore, the write verify is performed and “0” is written.
Only the memory cells with insufficient writing are detected, and the rewriting data is set so that the rewriting is performed only for the memory cells with insufficient "0" writing (verification for each bit). A memory cell in which "0" is insufficiently written is detected by setting the selected control gate to, for example, 0.5 V (verify voltage) and reading (verify read). That is, if the threshold voltage of the memory cell has a margin with respect to 0 V and is not 0.5 V or more, a current flows in the selected memory cell, and it is detected that "0" writing is insufficient.

By writing data while repeating the write operation and the write verify, the write time is optimized for each memory cell, and the threshold value after "0" write is controlled between 0V and Vcc. .

In such a NAND cell type EEPROM, since the write voltage Vpp at the time of writing is constant, the threshold voltage of the memory cell changes quickly at the beginning of writing when the amount of electrons in the charge storage layer is relatively small, and electron injection is performed. The threshold change of the memory cell is slow in the latter stage of writing when the amount of electrons in the charge storage layer is relatively large. Further, the electric field applied to the insulating film through which the tunnel current flows is strong in the initial stage of writing, and the electric field is weak in the latter stage of writing.

Therefore, if the write voltage Vpp is increased to increase the write speed, the maximum threshold value after writing becomes high, the threshold distribution width after writing becomes wide, and the voltage is applied to the insulating film through which the tunnel current flows. The generated electric field becomes strong and the reliability deteriorates. Conversely, if Vpp is lowered in order to narrow the threshold distribution width after writing, the writing speed becomes slow. In other words, there is a problem that the write voltage margin is narrow.

Hereinafter, this problem will be described in detail.
Here, as the memory cell, consider the configuration of FIG. 1 described later. In FIG. 1, 1 is a control gate, 2 is an inter-gate insulating film, 3 is a floating gate, 4 is a tunnel oxide film, 5 is an n-type diffusion layer, and 6 is a p-type well.

Conventionally, for example, when electrons are injected into a floating gate, a control gate voltage Vcg is applied as shown in FIG. 21A and the p-type well and the n-type diffusion layer are set to 0V. In this case, the control gate voltage Vcg is kept at the constant voltage Vpp for the constant time T. Since the amount of electrons in the floating gate is small initially, the floating gate potential Vfg is relatively high as shown in FIG. 21B, and the tunnel current Itunnel is relatively large as shown in FIG. As the injection of electrons into the floating gate progresses, the amount of electrons in the floating gate increases, so that the floating gate potential Vfg becomes relatively low and the tunnel current Itu.
nnel is relatively small. Therefore, the amount of change in the threshold value Vth of the memory cell is initially large and gradually decreases as shown in FIG.

Generally, when electrons are injected into the floating gate while performing a threshold value confirming operation of the memory cell called verify, it becomes as shown in FIG. The control gate voltage Vcg is divided into several pulses, and after the electron injection operation to each floating gate, verification is performed. In FIG. 22, the control gate voltage Vcg during the verify operation is set to 0V for convenience, but some voltage is often applied to the control gate depending on the verify method. When the verify detects that the threshold value of the memory cell has reached the desired value, the electron injection operation is terminated. When performing electron injection into a plurality of memory cells at the same time, when it is detected that the threshold value of the memory cells has reached a desired value by verification,
The electron injection operation is completed for each memory cell.

FIG. 23 is a diagram showing changes in the threshold value of each memory cell when electrons are injected into a plurality of memory cells by the same method as in FIG. Usually, the shape of the memory cell varies little by little, and as a result, the change with time of electron injection varies. In the memory cell in which electrons are most easily injected, the upper limit Vth of the range in which the threshold value of the memory cell should immediately fall is set to Vth.
-max is reached and the threshold value is Vth-m in the first electron injection operation.
The upper limit voltage Vpp-max of the voltage Vpp is determined so as not to exceed ax. In the memory cell that is the most difficult to inject electrons, it is difficult to reach the lower limit Vth-min of the range in which the threshold of the memory cell should fit, and the threshold value is Vth-min within the predetermined number of electron injection operations.
The lower limit voltage Vpp-min of the voltage Vpp is determined so as to exceed Vpp.

Vpp-max-Vpp-min is called a Vpp margin and must be a positive value. If Vth-max is lowered and the threshold distribution width is narrowed, Vpp must be lowered and the Vpp margin approaches 0V. When electron injection / emission is repeated, the tunnel oxide film deteriorates, and the electron injection / emission characteristics change. Therefore, if the Vpp margin is insufficient, there is a problem in reliability.

[0016]

As described above, the conventional NA is used.
In the ND cell type EEPROM, the write voltage Vpp
There is a so-called trade-off relationship that the threshold distribution width after writing becomes wider when the value is increased and the writing speed becomes slower when the writing voltage Vpp is decreased. Further, since the write voltage Vpp margin is narrow, there is a problem that the device reliability is lowered.

The present invention has been made in consideration of the above circumstances, and an object thereof is to ensure a sufficient write voltage Vpp margin and to narrow the threshold distribution width of a memory cell. It is an object of the present invention to provide an EEPROM that can perform high-speed electron injection.

[0018]

The essence of the present invention is to gradually increase the write voltage Vpp while repeating the cycle of the write operation and the verify operation for each bit.
The write voltage Vpp is increased by ΔVpp every cycle,
The one-time writing time Δt is constant. further,
ΔVpp and Δt are set so that the threshold distribution width after writing “0” is ΔVpp.

That is, the present invention (claim 1) is a memory cell array in which electrically rewritable memory cells, which are formed by stacking a charge storage layer and a control gate on a semiconductor layer, are arranged in a matrix. In order to change the threshold value of an arbitrary number of memory cells in the memory cell array, a threshold voltage changing voltage pulse is applied between the control gate and the semiconductor layer for a time Δt.
The threshold voltage changing means applied during 0, the threshold value verifying means for detecting the state after application of the threshold voltage changing voltage pulse of an arbitrary number of memory cells, and the desired voltage among the arbitrary number of memory cells. A threshold value changing means for applying a threshold value changing voltage pulse to the memory cell whose threshold value has not reached the threshold value for a time Δt and changing the threshold value again. After the threshold value changing operation by the threshold value changing means and the threshold value verifying operation by the threshold value verifying means, the re-threshold value changing operation and the threshold value verifying operation by the re-threshold value changing means are performed. In the non-volatile semiconductor memory device which repeats until the desired value is reached, the threshold voltage fluctuation voltage pulse is increased by the pulse wave height increment ΔVpp at each rethreshold voltage fluctuation operation to reach the desired threshold value. The threshold voltage distribution width of the memory cell is |
It is characterized by electrically erasing or writing data so that ΔVpp |.

Further, the present invention (claim 2) is a memory cell array in which electrically rewritable memory cells, which are formed by stacking a charge storage layer and a control gate on a semiconductor layer, are arranged in a matrix. In order to change the threshold value of an arbitrary number of memory cells in the memory cell array and erase means for erasing the data of the memory cells to the state of data “0”, write data ( Write pulse applying means for applying a threshold voltage fluctuation voltage pulse (Vpp1, Vpp2, ..., Vppn) according to "1", "2", ..., "N") and a threshold of an arbitrary number of memory cells. A threshold value verifying means for detecting a state after the application of the value variation pulse, and a desired threshold value according to write data (“1”, “2”, ..., “n”) among an arbitrary number of memory cells. Value (Vth1, Vth2 , Vthn), and a rewriting pulse applying means for applying a threshold value changing pulse according to the write data to the insufficiently written memory cell and again changing the threshold value according to the write data. After the threshold voltage changing operation by the write pulse applying means and the threshold verifying operation by the threshold verifying means, the rethreshold changing operation and the threshold verifying operation by the rewriting pulse applying means are performed on the memory cell. In the non-volatile semiconductor memory device that repeats until the threshold value reaches a desired value according to the write data, the threshold voltage fluctuation voltage pulse is Vpp1 = Vpp2-
ΔVppd2 = Vpp3−ΔVppd2 = ... = Vppn−ΔVppdn, and the desired threshold value is Vthi−Vthi−1 = Δ.
It is characterized in that it is Vppdi (i = 2, 3, ..., N).

Here, the following are preferred embodiments of the present invention. (1) The threshold voltage fluctuation voltage pulse by the write pulse applying means is applied for the time Δt0, the threshold voltage fluctuation voltage pulse by the rewriting pulse applying means is applied for the time Δt, and the threshold voltage fluctuation voltage pulse is applied again. Electrical writing is performed so that the pulse wave height increment ΔVpp is increased each time the threshold voltage is changed, and the threshold distribution width of the memory cell reaching the desired threshold becomes | ΔVpp |. (2) The pulse width of the threshold fluctuation pulse used during the threshold fluctuation operation and the re-threshold fluctuation operation must be constant. (3) The threshold fluctuation pulse wave height used during the re-threshold fluctuation operation is increased by the pulse wave height increment ΔVpp during the pulse width Δt, and the threshold fluctuation pulse wave height used during the threshold fluctuation operation is ΔVpp × Δt0 during the pulse width Δt0
Be increased by / Δt. (4) The threshold fluctuation pulse wave height used during the re-threshold fluctuation operation is increased by the pulse wave height increment ΔVpp at a constant rate of increase during the pulse width Δt, and the threshold value used during the threshold fluctuation operation. Value fluctuation pulse height is pulse width Δt0
It should be increased by a constant increase rate of ΔVpp × Δt0 / Δt during the period. (5) The threshold fluctuation pulse width Δt0 used during the threshold fluctuation operation and the threshold fluctuation pulse width Δt used during the rethreshold fluctuation operation are equal. (6) The threshold fluctuation pulse width Δt0 used during the threshold fluctuation operation is longer than the threshold fluctuation pulse width Δt used during the rethreshold fluctuation operation. (7) A plurality of memory cells are connected in series to form a NAND cell structure, connected to the bit line via the first select gate, and connected to the source line via the second select gate.

[0022]

According to the present invention, the write voltage Vpp is gradually increased as the write time elapses. For memory cells that are easy to write, writing is completed at a relatively low write voltage Vpp, and for memory cells that are difficult to write. By writing with a relatively high write voltage Vpp, a wide write voltage Vpp margin can be obtained.

Further, ΔVpp and Δt are set so that the threshold distribution width after writing “0” is ΔVpp, which means that the threshold shift amount in one cycle is a substantially constant value ΔVpp. Therefore, the voltage applied to the insulating film through which the tunnel current flows is controlled to be the same in every cycle, the maximum value can be reduced, and the reliability is improved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows the structure of the nonvolatile memory cell used in the embodiment of the present invention. The floating gate (charge storage layer) 3 and the control gate 1 are stacked on the p-type well 6 on the n-type silicon substrate 7. The p-type well 6 and the floating gate 3 are insulated by the tunnel oxide film 4, and the floating gate 3 and the control gate 1 are insulated by the inter-gate insulating film 2. The n-type diffusion layer 5 forms the source / drain of the memory cell transistor.

The capacitance between the floating gate 3 and the control gate 1 and the capacitance between the floating gate 3 and the p-type well 6 are Ccg and Cox, respectively, as shown in FIG. 1 (b). Capacity C
ox also includes the capacitance between the floating gate 3 and the n-type diffusion layer 5.
The memory cell stores data at the threshold value, and the threshold value is determined by the amount of charge stored in the floating gate 3. The amount of charge in the floating gate 3 is changed by the tunnel current passing through the tunnel oxide film 4.

That is, when the control gate 1 is set to a sufficiently high potential with respect to the p-type well 6 and the n-type diffusion layer 5, electrons are injected into the floating gate 3 through the tunnel oxide film 4 and the threshold value becomes high. Conversely, for the control gate 1, the p-type well 6
When the n-type diffusion layer 5 is set to a high potential, electrons are emitted from the floating gate 3 through the tunnel oxide film 4 and the threshold value becomes low.

FIG. 2 shows an electron injection method according to the first embodiment of the present invention. (A) is the control gate voltage Vc
g, (b) are the floating gate potential Vfg, (c) is the tunnel current Itunnel, and (d) is the threshold Vth of the memory cell.

A high voltage Vpp pulse is applied to the control gate, and verification is performed after the Vpp pulse is applied. The first Vpp pulse voltage is Vcg0, and is gradually increased by ΔVpp. The pulse width is a fixed time Δt. Δt and ΔVpp are
The maximum change amount ΔVth of the threshold value of the memory cell in one electron injection operation is set to be equal to ΔVpp. Actually, when Vpp is sufficiently high and the tunnel current starts to flow out sufficiently, if the threshold change amount ΔVth of the memory cell in one electron injection operation is made equal to ΔVpp,
The electrons injected in one electron injection operation cancel the voltage increase applied to the tunnel oxide film due to the increase ΔVpp of Vpp in the next electron injection operation, and thereafter, the threshold change amount ΔVth is changed every time. It becomes a constant value ΔVpp.

If the initial pulse voltage Vcg0 is sufficiently small, the threshold value of the memory cell in which electrons are most easily injected is
A wide Vpp that can be reliably controlled below the upper threshold Vth-max
A margin is obtained, and at the same time, Vth-max-Vth-min =
It can be set to ΔVpp. In the memory cell that is the most difficult to inject electrons, Vpp is increased to increase Vth at high speed.
-Reach min. The threshold value is verified for each memory cell by the verification, and if it is detected that the threshold lower limit Vth-min is reached, the electron injection operation is terminated for each memory cell.

In this method, since Vpp is further increased as the electron injection amount is increased, the maximum value Vfg-max of the floating gate voltage Vfg is suppressed and deterioration of the tunnel oxide film is also suppressed. Actually, the threshold change amount ΔVth becomes a constant value ΔVpp in every electron injection operation, and the floating gate voltage Vfg is applied in the same manner every time, and as a result, Vfg-max is suppressed.

FIG. 3 shows an electron injection method according to the second embodiment of the present invention. Basically, it is similar to the first embodiment, but several pulses in the initial stage of electron injection are combined into one and the verify operation is omitted to speed up the operation. This method is effective for high-speed electron injection when the threshold of the memory cell does not reach Vth-min with several pulses in the initial stage of electron injection in the electron injection method shown in FIG. Is.

FIG. 4 shows the change over time in the threshold values of the memory cell most susceptible to electron injection, the typical memory cell, and the memory cell least susceptible to electron injection in the second embodiment. In order to prevent the deterioration of the tunnel oxide film, it is preferable that Vfg-max be small. Therefore, as shown in FIG. 5, it is preferable to reduce the Vpp pulse width Δt and the Vpp increase rate ΔVpp. However, this increases the number of verify operations and takes time for electron injection. In addition, the threshold distribution width is unnecessarily narrow and wasteful.

FIG. 6 shows an electron injection method according to the third embodiment of the present invention. This is the Vpp seen in FIG.
It is a collection of several pulses. Initially, more Vpp pulses are put together, as described in FIGS. By this method, the floating gate voltage Vfg becomes almost constant, and while suppressing deterioration of the tunnel oxide film as compared with the method described in FIGS. 3 and 4, Vth-max-Vth-min = Δ
Vpp can be used for high-speed electron injection.

FIG. 7 shows an electron injection method according to the fourth embodiment of the present invention. This is the method shown in FIG. 6 in which Δt0 → 0 and ΔVpp0 → 0.
The pulse has a constant dVpp / dt and continuously rises by ΔVpp. With this method, the floating gate potential during electron injection can be made substantially constant, and deterioration of the tunnel oxide film can be suppressed to a minimum.

During the electron injection operation into the NMOS memory cell described above, if Vpp is sufficiently high, the channel portion is inverted and the drain, source and channel portions are at the same potential. Therefore, for example, the method shown in FIG. 7 is the same as the method shown in FIGS.

The method shown in FIG. 8 uses the control gate voltage V
The drain voltage Vd is gradually decreased while keeping cg constant.
As a result, the method shown in FIG. 7 and the method shown in FIG. 8 produce the same effect. If the initial value Vd0 of the voltage applied to the drain is high and exceeds the breakdown voltage by the method shown in FIG. 8, the method shown in FIG. 9 may be used. That is, the initial value Vd0 of the drain voltage is lowered, and at the same time, the initial value Vcg0 of the control gate is also lowered. Drain voltage Vd is 0
When the voltage reaches V, the control gate voltage Vcg is increased by Vd0 and Vd is decreased from Vd0. Even with such a method, the same effect as the method shown in FIG. 7 can be obtained.

In FIGS. 7 to 9, dVpp / dt = constant, but even if this is difficult in practice, dVpp / dt
While maintaining / dt ≧ 0, Vpp is changed at the rate of ΔVpp during the time of Δt, and the threshold distribution width after electron injection is ΔV.
By setting pp, an effect close to that when dVpp / dt = constant is obtained.

Of course, the voltage Vpp has an upper limit, which is determined by the breakdown voltage Vbreak of the device. When Vpp reaches Vbreak, Vpp cannot be further increased. Even in this case, Vpp
Until the Vbreak reaches Vbreak, the effect of the present invention can be obtained. 2 to 9, the case of electron injection has been described, but the case of electron emission can be similarly performed by reversing the polarity of the control gate with respect to the p-type well.

FIG. 10 shows a memory cell array of a NAND cell type EEPROM according to the fifth embodiment of the present invention. Eight memory cells M1 to M8 are connected in series so that adjacent ones share the source and drain to form one NAND cell, one terminal of which is the first
Is connected to the bit line BL via the selection transistor S1. The other terminal is connected to the second selection transistor S2.
Via the common source line Vs. The selection gates SG1 and SG2 are gate electrodes of the selection transistors S1 and S2,
The control gates CG1 to CG8 are gate electrodes of memory cells. A page is composed of a group of memory cells sharing the control gate CG, and a block is composed of a group of NAND cells sharing the select gate SG. Each memory cell has a structure as shown in FIG. 1, and the memory cell array is formed in a common p-type well.

Erasure of this NAND cell type EEPROM
Write, read, and write verify operations are
It is as follows. Erasure is performed in block units. p
The mold well is set to a high voltage Vpp (~ 20V), and the control gates CG1-8 in the selected block are set to 0V. The control gates and all select gates in the non-selected blocks are brought to Vpp. The electrons in the floating gate are emitted to the p-type well, and the threshold value of the memory cell becomes negative.

After erasing, data writing is collectively performed page by page from the page farthest from the bit line. During the write operation, Vpp (about 10 to 20 V) is applied to the control gate (for example, CG4) of the selected page, and the control gates CG1 to CG3, 5 to 8 of the unselected page and the first selection gate SG1 are applied. An intermediate potential Vm (-10V) is applied. The bit line BL is supplied with 0V in the case of "0" write operation and Vm in the case of "1" write operation. Second
The selection gate SG2 of is at 0V.

In the case of "0" write operation, the potential difference Vpp between the selected control gate CG4 and the channel causes electrons to be injected from the channel to the floating gate by the tunnel current, and the threshold value changes in the positive direction. In the case of "1" write operation, since the potential of the channel is set to Vm,
The electric field applied to the tunnel oxide film is weak, and effective injection of electrons into the floating gate does not occur. Therefore, the threshold does not change.

After the write operation, verify is performed to confirm the threshold value of the memory cell. A verify potential (~ 0.5) is applied to the selected control gate (eg, CG4).
V), and the non-selected control gates CG1 to CG3 to CG5 to CG8,
The power supply voltage Vcc is applied to the first and second selection gates SG1 and SG2. If the bit line BL and the source line are electrically connected to each other after the "0" write operation, the threshold value of the selected memory cell is equal to or lower than the verify potential and the "0" write is insufficient, and the "0" is rewritten. The write operation is executed again. Otherwise, it is determined that the threshold value is equal to or higher than the verify potential and "0" writing is sufficient, and it is judged that further injection of electrons into the floating gate is not necessary, and "1" writing operation is executed at the time of rewriting. After the "1" write operation, the "1" write operation is executed again during the rewrite operation regardless of the threshold value of the memory cell.

By writing data while repeating the write operation and verify operation, the write time is adjusted for each memory cell. When it is detected that all the memory cells for one page are sufficiently written, the data writing for one page is completed.

For reading, the selected control gate (for example, CG4) is set to 0V, and the non-selected control gates CG1 to CG1.
The power source voltage Vcc is applied to the third and fifth selection gates SG1 and SG2. If the potential of the precharged bit line BL is lowered, the threshold value of the memory cell is 0 V or less and the data is "1". If the potential of the bit line BL is held, the threshold value of the memory cell is 0 V or higher and the data is "0".
Is. From the read operation, the threshold of the memory cell must be lower than the power supply voltage Vcc.

Next, such a NAND cell type EEPR
A method of applying the write voltage Vpp to the selected control gate CG of the OM during writing will be described. FIG. 11 is a diagram showing a configuration of a circuit for driving the control gate. For each control gate and select gate, control gate driver 11,
A transfer circuit 9 is provided which selectively transfers the outputs of the first and second selection gate drivers 10 and 12. Cell array 8
The group of 10 transfer circuits 9 corresponding to the block of is selected by block selection signals φwi and φwBi. Booster circuit 1
3 is the power supply voltage Vcc to Vpp required for writing / erasing,
Vm is generated and supplied to the control gate driver 11 and the first and second selection gate drivers 10 and 12.

FIG. 12 more specifically shows the structures of the transfer circuit 9, the control gate driver 11, and the booster circuit 13 of the control gate CG4 of FIG. The transfer circuit 9 is composed of an n-channel MOS transistor (n-ch. MOS Tr.) Qn1 and a p-channel MOS transistor (p-ch. MOS Tr.) Qp1 and a n-ch. MOS Tr. It is composed of a reset circuit composed of Qn2. When the signals φwi and φwBi become “H” and “L”, respectively, the voltage of the node N1 is transferred to the control gate, and when they become “L” and “H”, the control gate is grounded. The booster circuit 13 includes a Vm booster circuit 14 and Vm.
It is composed of a pp booster circuit 15. Control gate driver 1
1 is a first switch circuit 16, a second switch circuit 17,
It comprises a third switch circuit 18.

The first switch circuit 16 is the Vm booster circuit 1
It controls whether or not the output Vm of 4 is connected to the node N1. The second switch circuit 17 controls whether or not the output Vpp of the Vpp booster circuit 15 is connected to the node N1, and the voltage transferred to the node N1 is Vpp-ΔVpp. The third switch circuit 18 controls whether or not the output Vpp of the Vpp booster circuit 15 is connected to the node N1.
The amount of current when transferring pp is controlled to control the rate of increase dVpp / dt of the potential of the node N1.

FIG. 13 shows a specific structure of the control gate driver 11. The first switch circuit 16 is pc
h. MOS Tr. Qp2 to 4, n-ch. MOS Tr. Qn3, 4, n-channel D-type MOS transistor (n-ch. D-type MOS T
r.) QD1 and inverter I1. Qp2,
The circuit composed of 3, Qn3, 4 and inverter I1 is 0V
The signal .phi.1 oscillating between Vcc and Vcc is converted into a signal oscillating between 0V and Vpp. φ1 is "L", the gate of Qp4 is Vpp, the gate of QD1 is 0V, and Vm and N1 are separated. φ1 is "H", the gate of Qp4 is 0V, Q
The gate of D1 becomes Vpp, and Vm and N1 are connected. Q
D1 is for preventing Vpp from being transferred to Qp4 when N1 becomes Vpp.

The second switch circuit 17 is a p-ch. MOS Tr.
Qp5-8, n-ch. MOS Tr. Qn5, 6 and inverter I2. When φ2 is "L", the gate of Qp7 becomes Vpp, and Vpp and N1 are separated. φ2 is “H”, Qp7
Has a gate of 0 V, Vpp and N1 are connected, and a voltage lower than Vpp by a threshold value of Qp8 (up to 1 V) is transferred to N1.

The third switch circuit 18 is a p-ch. MOS Tr.
Qp9 to 11, n-ch. MOS Tr. Qn7, 8, an inverter I3, and a current control circuit 19. φ3 is “L”, Qp1
The gate of 1 becomes Vpp, and Vpp and N1 are separated.
When .phi.3 is "H", the gate of Qp11 becomes 0V, Vpp and N1 are connected, and Vpp is transferred to N1 while the current control circuit 19 controls dVpp / dt.

P-ch. MOS Tr. Qp12, n-ch. MOS Tr. Q
n9, n-ch. D-type MOS Tr. QD2, N1 is VGH or V
It is a circuit to make cc. φ4 is "H" and N1 is VG
When H and φ4 are "L", N1 becomes Vcc. The voltage VGH is normally 0 V, and the verify voltage VVRFY (up to 0.
5V). When the signal φ5 becomes "L" and Vm or Vpp is applied to the node N1, QD2 becomes Vm to Qp12.
And Vpp are not transferred.

FIG. 14 is a diagram showing a specific structure of the current control circuit 19 shown in FIG. FIG. 14A shows p-ch.
It is composed of MOS Tr. Qp13-15 and n-ch. D-type MOS Tr. QD3, 4 and signal .phi.3B is an inverted signal of signal .phi.3 in FIG. When the signal .phi.3 becomes "H" and .phi.3B becomes "L" and the node N2 becomes Vpp, the gate of Qp15 becomes Vpp-2Vtp.
(Vtp is the threshold of p-ch. MOS Tr.), And node N
The current from 3 to N1 is controlled by Qp15.

FIG. 14B shows p-ch. MOS Tr. Qp16,1.
7, n-ch. MOS Tr. Qn10, capacitor C1 and resistor R1
Composed of. Signal φ3 is "H", node N2 is Vpp
Then, the gate of Qp16 changes from Vpp to 0V under the control of the capacitor C1 and the resistor R1. Therefore, the current from the node N3 to N1 is controlled by Qp16.

FIG. 15 shows the EEP configured as described above.
It is a timing diagram which shows the write-in operation of ROM. Here, it is assumed that the control gate CG4 is selected. First, the voltages Vm and Vpp are boosted from the power supply voltage Vcc by the booster circuits 14 and 15. The voltage Vpp increases from Vpp1 by Vtp each time writing / verifying is repeated. The signals φwi and φwBi seen in FIG. 12 are Vpp and 0V, respectively, in the selected block.

In the write operation, the signal φ4 becomes "L", the node N1 becomes Vcc, and the control gates CG1 to CG8 of the selected block become all Vcc. At the same time, the selection gate SG1 of the selected block is also set to Vcc and the bit line B
L is set to Vcc only when "1" is written. The select gate SG2 is set to 0V during the write operation. φ1 is "H"
Therefore, the control gates CG1 to CG8, the selection gate SG1 and
The "1" write bit line BL becomes Vm. The selected control gate CG4 is raised while being controlled from Vm to Vpp1 over time Δt0 when φ3 becomes "H". The non-selection control gates CG1 to 3 and 5 to 8 and the selection gate SG1 and the "1" write bit line BL remain Vm. Signals for unselected control gates φ1, φ2, φ3
, Φ4 are shown by dotted lines in the figure.

Φ4 becomes "H" and all control gates CG1
~ 8 is 0V. At this time, the selection gate SG1 is also 0V
And the bit line BL is reset to 0V after a delay.

Then, the verify operation is performed. The selection control gate CG4 becomes the verify potential VVRFY, and the non-selection control gates CG1 to 3 and 5 to 8 have φ4 "L" and V
cc is assumed. The selection gates SG1 and SG2 also become Vcc.
When it is detected that the threshold value of the memory cell to be written "0" exceeds VVRFY, "1" is written in the rewriting operation, and excessive "0" writing is prevented. "0"
When it is detected that the threshold value of the memory cell to be written does not exceed VVRFY, "0" is written again during the rewriting operation. In the memory cell to be written with "1", "1" is written again during the rewriting operation.

In the second and subsequent write operations, the selection control gate CG4 is charged to Vm, then φ2 is output, and the selection control gate CG4 is rapidly charged to the maximum voltage of the selection control gate in the previous write operation. Furthermore, φ3 becomes "H", and V
It can be raised while being controlled by tp for a time Δt. For example, during the second write operation, Vpp1 to Vpp2
It is raised while being controlled to (Vpp2 = Vpp1 + Vtp).

At the time of the first writing operation (Vpp1-Vm)
/ Δt0 and Vtp / Δt during the second and subsequent write operations are set to be approximately the same value. At the time of the first write operation, the threshold value of the memory cell in which the fastest "0" is written is equal to or less than the maximum value of the threshold distribution that should be accommodated after the write of "0", and at the second and subsequent write operations, " 0 ”is the threshold of the memory cell to be written Δ
Vpp (ΔVpp is an increase rate of Vpp, Vtp in this example) is set to shift (FIG. 16). Therefore, "0"
The threshold distribution width after writing is ΔVpp (in this example, Vt
p).

The data write operation is repeated by repeating the above write operation and verify operation, and when it is detected that the threshold values of all the memory cells to be "0" written exceed VVRFY.

Another embodiment of the control gate driver 11 will be described.
Shown in FIGS. Here, two Vpp booster circuits A
20 and a Vpp booster circuit B21 are provided, and their outputs are VppA and VppB. The fourth switch circuit 22 has V
It controls whether or not the output VppA of the pp booster circuit A20 is connected to the node N1.

FIG. 19 is a timing chart showing the write operation. VppA and VppB are the same Vpp1 during the first write operation, and VppB = VppA after the second write operation.
+ ΔVpp. Other than VppA and VppB, it is the same as FIG. In this embodiment, the setting of ΔVpp is as shown in FIG.
It is easier than the embodiment shown in FIG.

FIG. 20 shows an electron injection method according to the seventh embodiment of the present invention. This is to store three states (data “0”, “1”, “2”) in one memory cell. The Vpp pulse waveform is the same as that shown in FIG. 7, but the voltage applied to the memory cell for writing "2" and the memory cell for writing "1" is ΔV.
Only ppB is different. In the verify operation, the memory cells to be written "2" have not reached the desired threshold value (VVRFY2), and the memory cells to be "1" written have not reached the desired threshold value (VVRFY1). , Respectively, and "2" or "1" additional writing is performed only to those memory cells. At this time, dVpp2 / d
t = dVpp1 / dt = ΔVppA, and ΔVppA is made equal to the threshold change amount dVth / dt of the memory cell.

As a result, the threshold distribution ΔVth after writing “2” and “1” becomes ΔVppA. Also, ΔVppB
Is equal to the threshold margin ΔVmarjin between the threshold distributions after writing “2” and “1” plus the threshold distribution width ΔVth (ΔVppB = ΔVth + ΔVmarj
in, or ΔVppB = VVRFY2−VVRFY1). As a result, “2” and “1” writing are independently processed in parallel, and writing is performed at high speed. Naturally, the maximum voltage applied to the tunnel oxide film of the memory cell can be suppressed to the minimum.

Further, in the sense that "2" and "1" writing are independently processed in parallel and writing is performed at high speed, no matter what form the Vpp pulse waveform is,
It is effective to make the difference between the voltages applied to the memory cell for writing "2" and the memory cell for writing "1" by ΔVppB.

According to the above-mentioned gist, the same operation can be performed in the case of multi-value storage of four or more values. In FIG. 20, the case of electron injection has been described, but the case of electron emission can be similarly performed by reversing the polarity of the control gate with respect to the p-type well.

Basically, according to the present invention, the potential change of the floating gate due to the injection or emission of electrons (holes) is applied to the oxide film portion under the floating gate where the electrons (holes) move under the gradually increasing Vpp. The feature is that it is designed to cancel the rise of the electric field. Therefore, according to this principle,
In addition to the injection or emission of electrons (holes) by the tunnel current through the entire surface of the channel as in the embodiment described above, for example, the injection of electrons (holes) by the tunnel current between the drain or source and the floating gate, or hot electron Alternatively, the same effect can be obtained by using a hot hole.

[0069]

As described above, according to the present invention, the write voltage Vpp is gradually increased while repeating the cycle of the write operation and the bit-by-bit verify operation, thereby ensuring a sufficient Vpp margin and ensuring a sufficient memory cell capacity. A narrow threshold distribution width allows high-speed electron injection.
An EPROM can be realized. Also, electron emission can be easily performed by reversing the polarity of the control gate voltage of the memory cell. Furthermore, the memory cell is a p-channel MOS
The same can be applied to a transistor.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure and an equivalent circuit of a memory cell used in an embodiment of the present invention.

FIG. 2 is a diagram showing an electron injection characteristic by an electron injection method incorporating a verify operation in the first embodiment.

FIG. 3 is a diagram showing an electron injection characteristic by an electron injection method incorporating a verify operation in the second embodiment.

FIG. 4 is a diagram showing a threshold change of a memory cell according to a conventional electron injection method that incorporates a bit-by-bit verify operation in the second embodiment.

FIG. 5 is a diagram showing an electron injection characteristic by an electron injection method in which a verify operation is incorporated in order to further enhance the controllability of the threshold value of the memory cell in the second embodiment.

FIG. 6 is a diagram showing an electron injection characteristic by an electron injection method incorporating a verify operation in the third embodiment.

FIG. 7 is a diagram showing electron injection characteristics by an electron injection method incorporating a verify operation in the fourth embodiment.

FIG. 8 is a diagram showing a modification of the electron injection method incorporating the verify operation in the fourth embodiment.

FIG. 9 is a diagram showing a modification of the electron injection method incorporating the verify operation in the fourth embodiment.

FIG. 10 is a NAND cell type EE in the fifth embodiment.
The figure which shows the figure which shows the memory cell array of PROM.

FIG. 11 is a diagram showing the configuration of a circuit for driving a control gate in the fifth embodiment.

FIG. 12 is a diagram showing a circuit configuration of a control gate driver in a fifth embodiment.

FIG. 13 is a diagram showing a specific circuit configuration of a control gate driver in the fifth embodiment.

FIG. 14 is a diagram showing a specific configuration of a current control circuit in a control gate driver in the fifth embodiment.

FIG. 15 is a timing chart for explaining a write / verify operation in the fifth embodiment.

FIG. 16 is a diagram showing write characteristics of a memory cell in the fifth embodiment.

FIG. 17 is a diagram showing the configuration of a control gate driver in the sixth embodiment.

FIG. 18 is a diagram showing a specific circuit configuration of a control gate driver in the sixth embodiment.

FIG. 19 is a timing chart for explaining a write / verify operation in the sixth embodiment.

FIG. 20 is a diagram showing an electron injection method incorporating a verify operation and its electron injection characteristics in the seventh embodiment.

FIG. 21 is a diagram showing electron injection characteristics according to a conventional electron injection method.

FIG. 22 is a diagram showing electron injection characteristics according to a conventional method that incorporates a verify operation.

FIG. 23 is a diagram showing a threshold change of a memory cell according to a conventional electron injection method incorporating a bit-by-bit verify operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control gate 2 ... Gate insulating film 3 ... Floating gate 4 ... Tunnel oxide film 5 ... N-type diffusion layer 6 ... P-well 7 ... N-type substrate 8 ... NAND cell type cell array 9 ... Transfer circuit 10 ... First selection Gate driver 11 ... Control gate driver 12 ... Second selection gate driver 13 ... Boosting circuit 14 ... Vm boosting circuit 15 ... Vpp boosting circuit 16 ... First switch circuit 17 ... Second switch circuit 18 ... Third switch circuit 19 ... Current control Circuit 20 ... Vpp booster circuit A 21 ... Vpp booster circuit B 22 ... Fourth switch circuit Qn ... n-channel MOS transistor Qp ... n-channel MOS transistor QD ... n-channel D type MOS transistor I ... CMOS inverter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (3)

[Claims] 1. A memory cell array in which electrically rewritable memory cells, which are formed by stacking a charge storage layer and a control gate on a semiconductor layer, are arranged in a matrix, and an arbitrary number of memory cells in the memory cell array. Threshold varying means for applying a threshold varying voltage pulse between the control gate and the semiconductor layer for a time Δt0 in order to vary the threshold of the memory cell; Threshold verifying means for detecting a state after application of a threshold voltage fluctuation voltage pulse, and among the arbitrary number of memory cells, for memory cells with insufficient threshold fluctuation which have not reached a desired threshold value. A threshold value changing operation for applying the threshold value changing voltage pulse for a time Δt and changing the threshold value again, After the threshold value verifying operation by the threshold value verifying means, the threshold value of the memory cell reaches the desired value by the re-threshold value changing operation and the threshold value verifying operation by the re-threshold value changing means. In the nonvolatile semiconductor memory device, the threshold voltage fluctuation voltage pulse is increased by a pulse wave height increment ΔVpp each time the rethreshold voltage fluctuation operation is performed, and the threshold voltage of the memory cell reaching the desired threshold voltage is increased. A non-volatile semiconductor memory device characterized by electrically erasing or writing data so that the distribution width becomes | ΔVpp |. 2. A memory cell array in which electrically rewritable memory cells, which are formed by stacking a charge storage layer and a control gate on a semiconductor layer, are arranged in a matrix, and data of each memory cell of the memory cell array. Erasing means for erasing data to the state of data "0", and write data ("") between the control gate and the semiconductor layer in order to change the threshold value of an arbitrary number of memory cells in the memory cell array. 1 ”,“ 2 ”, ...,
Threshold voltage fluctuation voltage pulse (Vpp1, V) depending on "n")
pp2, ..., Vppn), write pulse applying means, threshold verifying means for detecting a state of the arbitrary number of memory cells after the threshold voltage fluctuation voltage pulse is applied, and the arbitrary number of memories. Among the cells, for the insufficiently written memory cells that have not reached the desired threshold values (Vth1, Vth2, ..., Vthn) according to the write data (“1”, “2”, ..., “N”) A re-writing pulse applying means for applying a threshold voltage varying voltage pulse according to write data and again varying the threshold value according to write data. After the threshold verifying operation by the threshold verifying means, the re-threshold changing operation and the threshold verifying operation by the rewriting pulse applying means are performed in the memory cell. Is repeated until the threshold value reaches the desired value according to the write data, and the threshold voltage fluctuation pulse is Vpp1 = Vpp2-ΔV.
ppd2 = Vpp3−ΔVppd3 = ... = Vppn−ΔVppdn, and the desired threshold value is Vthi−Vthi−1 = ΔVppdi
A non-volatile semiconductor memory device characterized in that (i = 2, 3, ..., N). 3. The threshold voltage fluctuation voltage pulse by the write pulse applying means is applied for a time Δt0, and the threshold voltage fluctuation voltage pulse by the rewriting pulse applying means is applied for a time Δt. The fluctuating voltage pulse is increased by the pulse wave height increment ΔVpp each time the threshold voltage is changed again, and the data is electrically changed so that the threshold distribution width of the memory cell reaching the desired threshold becomes | ΔVpp |. The nonvolatile semiconductor memory device according to claim 2, wherein writing is performed.