JPH0773688A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor storage device capable of preventing the insulation destruction of a tunnel oxide film and the increase of a leakage current at the time of data erase and data write and improving the reliability of a memory cell. CONSTITUTION:In the nonvolatile semiconductor storage, the memory cell formed with source/drain areas on a surface of a semiconductor substrate, laminated with a first gate insulation film (tunnel oxide film), a floating gate, a second gate insulation film and a control gate in this order on the substrate, and capable of electrically rewriting by transferring a charge between the floating gate and the semiconductor substrate is used. At the time of the data erase, by the operation where a high potential (boosted potential; H level) is applied to the semiconductor substrate and intermediate potential (power source potential; M level) is applied to the control gate 16 first, and then, the H level is applied to the semiconductor substrate and low potential (grounded potential; L level) is applied to the control gate, the charge is pulled out from the floating gate 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) constructed by using a memory cell having a MOS transistor structure having a charge storage layer and a control gate.

[0002]

2. Description of the Related Art Conventionally, a memory cell having a MOS transistor structure having a charge storage layer (floating gate) and a control gate has been widely used in the field of EEPROM, and high integration has been advanced. This memory cell can be electrically rewritten by exchanging charges between the floating gate and the semiconductor substrate.

However, this type of device has the following problems. That is, when erasing data, a high electric field is applied to the tunnel oxide film between the floating gate and the substrate, which causes problems such as dielectric breakdown and increase in leak current. Further, even when writing data, a high electric field is applied to the tunnel oxide film and a large stress is applied, so that the tunnel oxide film deteriorates after being used for a certain period of time. Then, the deterioration of the tunnel oxide film causes the resistance of the cell data to the stress applied to the cell at the time of reading the cell data to be reduced, which causes the life of the cell data to be shortened.

As one of the EEPROMs, a NAND-type EEPROM capable of high integration is known. In this, a plurality of memory cells are connected in series so that their sources and drains are shared by adjacent ones to form one unit, which is connected to a bit line. A memory cell is usually a FETMOS in which a charge storage layer and a control gate are stacked.
Have a structure. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate.

The drain side of the NAND cell is connected to the bit line via the selection gate, and the source side is also connected to the source line (reference potential wiring) via the selection gate. The control gates of the memory cells are continuously connected in the row direction to form word lines. Usually, a set of cells connected to the same word line is called one page, and a set of pages sandwiched between a set of drain and source side select gates is called one NAND block or simply one block. Normally, one block is the minimum unit that can be independently erased.

The operation of the NAND type EEPROM is as follows. Data is erased simultaneously for the memory cells in one NAND block. That is, the selected NA
All control gates of the ND block are set to Vss, and a high voltage Vpp (for example, 20V) is applied to the p-type well and the n-type substrate. As a result, in all memory cells, electrons are emitted from the floating gate to the substrate, and the threshold value shifts in the negative direction. Usually, this state is defined as a "1" state. Further, chip erasing is performed by putting all NAND blocks in a selected state.

The data write operation is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (for example, 20V) is applied to the selected control gate in the NAND block, and the intermediate potential VM is applied to the other non-selected gates.
(For example, 10 V) is applied. Further, Vss or VbitH (8V) is applied to the bit line according to the data. When Vss is applied to the bit line ("0" write), the potential is transmitted to the selected memory cell, and electron injection occurs in the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. Usually, this state is defined as a "0" state. In the memory cell in which VbitH is applied to the bit line ("1" write), electron injection does not occur, so the threshold value does not change and remains negative. Further, a voltage VM for transferring the bit line potential is applied to the drain side select gate.

In the data read operation, the control gate of the selected memory cell in the NAND block is set to Vss and the other control gates and select gates are set to Vcc to detect whether or not a current flows in the selected memory cell. Done by. The data is latched by the sense amplifier / data latch circuit.

A conventional write verify cycle will be described. After inputting the write data, the set voltage (for example, 20 V) is applied to the selected control gate for the set time (for example, 40 μsec). Next, reading is performed to confirm whether the writing has been completed. If there is a memory cell for which writing has been insufficient, the memory cell is rewritten to 20 times.
Writing of V and 40 μsec is performed. At that time, VbitH is applied to the bit line so that electrons are not further injected into the cell in which sufficient writing has been performed. That is, 20V, 4V until all memory cells have been written
Repeat writing for 0 μsec. The potentials of the respective parts at this time are shown in (Table 1).

[0010]

[Table 1]

In the writing method for verifying each block (or each chip), a writing method is known in which the voltage (high voltage Vpp) applied to the control gate is increased in order to shorten the programming time. (Hereinafter, referred to as “chip-by-chip verify-voltage rise method”).

This writing method will be described with reference to FIG. In this method, the program is written in the following procedure. The threshold value of each memory cell varies depending on process variations and previous usage.
For example, in this example, the threshold of the memory cell with the lowest threshold (that is, the memory cell M2 that is the least likely to be written) is Vth = -4V (A0 in FIG. 16) and the memory cell with the highest threshold ( That is, the threshold value of the memory cell M1 which is most easily written is Vth = -1V (B0 in FIG. 16).
Then, the case where "0" is written and the threshold Vth of the memory cell is set in the range of 0.5 to 2V will be described.

A page (or chip) is selected.
According to the data to be written in each memory cell of the selected page, if "0" is written, Vss (for example, 0V) is set to
If "1" is written, VbitH (for example, 10V) is applied to the bit line connected to each memory cell. Then, the high voltage Vpp (for example, 18.5 V) is applied to the selected word line (that is, the control gate of the selected memory cell) to perform the first writing.

At the time when the first writing is completed, it is checked whether the threshold value Vth of the memory cell is at the completion judgment level (verify). At this time, the threshold Vth of the memory cell M1 is 0V (B1),
The threshold Vth of the memory cell M2 is -3V (A1).

Both the memory cells M1 and M2 have a threshold value Vth.
Is less than or equal to a predetermined value, it is determined that the writing has not been completed, and a constant voltage Vpp (for example, 19.5 V) higher than the voltage applied the first time is applied to the selected word line to apply the second voltage. Write the second time. By the second writing, the threshold Vth of the memory cell M1 is 3V (B3), which is within the predetermined range. However, the threshold value Vth of the memory cell M2 is -0.5 V (A3), and the threshold value Vth is not within the predetermined range. Therefore, it is determined that the writing is not completed.

In order to write to the memory cell M2,
A constant voltage Vpp (for example, 20.5 V) higher than the voltage applied the second time is applied to the selected word line to perform the third writing. After that, verification and writing are performed while gradually increasing the voltage of the selected word line until the writing of the memory cell M2, which is the hardest to be written, is completed (until the threshold value falls within a predetermined range). Such a method is disclosed in, for example, Japanese Patent Laid-Open No. 61-239497.

In the above method, the voltage Vpp applied to the selected word line is sequentially increased until all memory cells on the selected page are programmed, and finally applied Vpp (= 21.5V). ) Is equally applied to both the memory cell that is the hardest to write and the memory cell that is the easiest to write. That is, all memory cells are written with the same Vpp.

Therefore, although the programming time is shortened, the width of the variation in the threshold value between the memory cells does not change, so that the memory cell that is most easily written is over-programmed.

In order to solve the above problem, there is a method of verifying a memory cell bit by bit (hereinafter referred to as a bit-by-bit verify-fixed voltage method). The threshold value of each memory cell varies depending on process variations and previous usage. For example, in this example, the threshold value of the memory cell having the lowest threshold value (that is, the memory cell M2 which is the least likely to be written) is Vth = -3V (C0 in FIG. 17),
The threshold value of the memory cell having the highest threshold value (that is, the memory cell M1 which is most easily written) is Vth = 0V (see FIG. 1).
A description will be given of the case where D0) of 7 is set, "0" is written, and the threshold Vth of the memory cell is set in the range of 0.5 to 2V.

This method will be described with reference to FIG. In this method, the program is written in the following procedure. A page (or chip) is selected. According to the data to be written in each memory cell of the selected page, Vss (for example, 0V) if “0” is written
If "1" is written, VbitH (for example, 10V) is applied to the bit line connected to each memory cell. The high voltage Vpp (= 18.5 V) is applied to the selected word line (that is, the control gate of the selected memory cell) to perform the first writing.

At the time when the first writing is completed, it is checked for each memory cell whether the threshold value Vth of the memory cell is at the judgment level of completion (verify). At this time, the threshold Vth of the memory cell M1 is 1
V (C1), and the threshold value falls within a predetermined range. However, the threshold Vth of the memory cell M2 is -2V (D
1) and the threshold value Vth is not within the predetermined range,
It is determined that writing has not been completed.

Again, 10V is applied to the bit line connected to the memory cell (not shown) where writing is not completed and the memory cell where the writing is completed, and 0V is applied to the bit line connected to the memory cell where the writing is not completed. Then, the same Vpp (18.5V) as that of the first time is applied to the selected word line for a time slightly longer than that of the first time.

The above operation is repeated until the writing of the memory cell M2 which is the most difficult to write is completed (until the threshold value falls within a predetermined range). Such a method is disclosed in, for example, Japanese Patent Application Laid-Open No. 1-159895.

In the above method, since the memory cells are verified, the over-programming of the memory cells can be prevented. That is, the threshold width of the memory cell can be set within a predetermined (desired) range. On the other hand, all the memory cells on the selected page are programmed with the same Vpp (18.5V). Therefore, a memory cell having a slow program characteristic (hard to be written) is fast (easy to be written).
Since the memory cells are also programmed with the same voltage, it takes a long time to program all the memory cells.

[0025]

As described above, the conventional E
In the EPROM, there are problems such as a dielectric breakdown of the tunnel oxide film and an increase in leak current of the tunnel oxide film due to a high electric field applied to the tunnel oxide film at the time of erasing data.

Further, in the conventional verify write in the NAND type EEPROM, the minimum pulse width and the maximum write time are determined by the variation of the cell characteristics and the booster circuit limiter. Therefore, when the integration progresses and the variation of the cell characteristics becomes large. There is a problem that the writing time becomes extremely long.

The present invention has been made in view of the above problems, and an object thereof is to prevent the dielectric breakdown of the tunnel oxide film and the increase of leak current at the time of data erasing and data writing. Another object of the present invention is to provide a non-volatile semiconductor memory device that is capable of improving the reliability of memory cells.

Another object of the present invention is to provide a non-volatile semiconductor memory device having a write verify method capable of suppressing an increase in write time even if cell characteristics vary.

[0029]

In order to solve the above problems, the present invention adopts the following configuration. That is, according to the present invention (claim 1), in a nonvolatile semiconductor memory device, a plurality of electrically rewritable and erasable memory cells are arranged in a matrix, and a plurality of memory cells connected to the drains of the memory cells. A bit line, a plurality of word lines that are control gates of the memory cells, and a memory that is connected to the selected word line and applies a first write potential to the selected word line at the time of page writing and performs writing. A first bit line potential is applied to a bit line to which a cell is connected, and a second bit line is connected to a bit line connected to the selected word line and to which a memory cell not to be written is connected.
The writing means for applying the bit line potential and the information written by the writing means are read, and if there is a memory cell in which writing is insufficient, rewriting is performed by the writing means again, and the first writing is performed according to the number of times of writing. Rewriting means for sequentially increasing the potential.

According to a tenth aspect of the present invention, in a nonvolatile semiconductor memory device, a semiconductor substrate, source and drain regions formed on the surface of the semiconductor substrate, and a first semiconductor layer sequentially stacked on the semiconductor substrate. A gate insulating film, a charge storage layer, a second gate insulating film, and a control gate,
A memory cell that is electrically rewritable by exchanging charges between the charge storage layer and the semiconductor substrate, and when erasing data, first applies a high potential to the semiconductor substrate and an intermediate potential to the control gate. Is applied to the semiconductor substrate for the second time and thereafter, and a low potential is applied to the control gate to extract electric charges from the charge storage layer.

According to a twelfth aspect of the present invention, in a nonvolatile semiconductor memory device, a semiconductor substrate, source and drain regions formed on the surface of the semiconductor substrate, and a first semiconductor layer sequentially laminated on the semiconductor substrate. A gate insulating film, a charge storage layer, a second gate insulating film, and a control gate,
A plurality of memory cells that can be electrically rewritten by exchanging charges between the charge storage layer and the semiconductor substrate and the memory cells are arranged in a matrix, and the first time when erasing data. A high potential is applied to the control gates of the semiconductor substrate and the non-selected memory cell, an intermediate potential is applied to the control gate of the selected memory cell, and a high potential is applied to the control gates of the semiconductor substrate and the non-selected memory cell from the second time onward. A means for applying a potential lower than the intermediate potential to the control gate of the selected memory cell to extract the charge from the charge storage layer.

The present invention (claim 14) has a memory cell array in which a plurality of electrically rewritable and erasable memory cells are arranged in a matrix, and a plurality of bit lines connected to the drain of the memory cell array. By having a plurality of word lines connected to the control gates of the memory cells and applying different program or erase pulses to each of the memory cells connected to the same word line, Means for programming or erasing the selected memory cell within the same operation.

[0033]

According to the present invention (claims 1 to 9), the write voltage Vpp applied to the selection control gate of the selected block and the bit line potential transfer applied to the non-selection control gate of the selected block according to the number of times of verify writing. VM, the bit line potential VbitH applied to the "1" write cell, etc. are controlled. Specifically, a predetermined number of times of writing is detected and these voltages are increased within a predetermined range. For example,
The Vpp pulse had the same set voltage as the conventional 20V-20V-20V-, but in the present invention, 19V-20V-.
21V-21V-, and the set voltage is sequentially increased from 19V to 21V in steps of 1V. Further, the set voltage voltage is increased according to a predetermined relationship between VM and VbitH with Vpp.

With this structure, the following effects can be obtained. First, the effect of lowering the initial write potential will be described. The setting of the write voltage for the first time is lowered by 1V from the conventional one. If the limiter varies in the high voltage direction (+ 0.5V), it is 2 with respect to the conventional setting of 20V.
A voltage of 0.5V was output. Therefore, the memory cell that is most easily written in 40 usecs reaches 2V which is the upper limit of the threshold distribution. Then, this pulse width determines the minimum pulse width.

However, according to the present invention, even if the limiter varies in the high voltage direction, the setting of the first write voltage is lowered by 1V as compared with the conventional one, so that the threshold value of 2V is exceeded even in the memory cell that is the easiest to write. It is 200 usec or more (see FIG. 15). In other words, with the write pulse of 40 usec, the allowable upper limit of the threshold distribution is not exceeded even if the output voltage of the limiter shifts by 1.5 V or more. As a result, the process control of the limiter is facilitated and the yield is improved.

Secondly, the effect of increasing the write voltage for the second and third times will be described. Next, consider the case where the limiter varies in the low voltage direction. Conventionally 20V
It is assumed that a voltage of 19.5V is output for the setting of. In this case, it takes 400 μsec to write the slowest write memory cell to the threshold lower limit of 0.5 V, and as described above, the minimum pulse width is 40 μsec.
In this case, it was necessary to repeat writing and verifying up to 10 times.

However, according to the present invention, since the write voltage is gradually increased, a lower voltage than the conventional one is output in the first write pulse, but the write voltage is increased in the second and third times, and the third and subsequent times. Even if the voltage is fixed, according to the thick solid line in FIG. 15, writing is performed up to the threshold of the lower limit of 0.5 V by writing 5 times for 40 usec.
This writing time is 1 compared to the net writing time.
It is / 2. The effect of shortening the writing time is the threshold distribution in the case of not verifying (±
The larger the value (calculated at 1 V), the greater the effect.

Third, the reliability of the memory cell will be described. It is known that the deterioration phenomenon of the memory cell is greatly related to the maximum electric field applied to the tunnel oxide film during writing. Consider a memory cell that is most easily written when the limiter varies in the high voltage direction by the conventional method. Before the first writing, the memory cell has a negative threshold value in the erased state. Since memory cells that are easily written are usually easily erased,
It has a deep negative threshold. When a write voltage varying in the high voltage direction is applied to this, a very large electric field is applied to the tunnel oxide film, and the memory cell is deteriorated.

However, according to the present invention, since the first write voltage is lowered, only a smaller electric field is applied to the tunnel oxide film as compared with the conventional method, which suppresses the deterioration of the memory cell.

Fourthly, the point that the bit line potential transfer voltage VM applied to the non-selected control gate of the selected block and the bit line potential VbitH applied to the "1" write cell are increased with respect to the increase of Vpp will be described. .

For the "1" data cell and the cell for which writing has been completed in the "0" write cell, V is applied to the control gate.
VbitH is applied to pp and source / drain to prevent charges from being injected. Therefore, for an increase in Vpp, Vbi
Increasing tH can prevent erroneous writing. Therefore, the voltage VM of the non-selected gate is also increased so that VbitH is transferred. However, since the memory cell connected to the non-selection control gate is exposed to a weak write mode in which VM is applied to the gate and Vss is applied to the source / drain, it is necessary to increase Vpp and VbitH in a balanced manner so that erroneous writing does not occur. Becomes

As described above, according to the present invention, it is possible to simultaneously improve the reliability of the memory cell and increase the writing speed.
The inventors of the present invention call such a method for programming cells with slow and fast programming characteristics at an optimum Vpp for each bit as a high-speed bit-by-bit programming method.

Next, the operation of the present invention (claim 3) will be described. In an EEPROM in which data is written or erased by flowing an F-N tunnel current through the entire gate insulating film of a memory cell to store negative charges or positive charges in a charge storage layer, F-N is generally used in the gate insulating film. It is known that as the tunnel current is passed, the leak current on the low electric field side increases and the data retention characteristic deteriorates. The degree of deterioration of this gate insulating film is
It is also known that depending on the electric field applied to the gate insulating film, the degree of deterioration can be suppressed to a small level by reducing the electric field.

In the memory cell, the capacitance of the capacitor formed by the substrate and the charge storage layer is C1, the capacitance formed by the charge storage layer and the control gate is C2, and the potential applied to the control gate at the time of writing is Vpp and C1. When the potential difference is V1, the charge stored in the charge storage layer is Q, and the thickness of the gate insulating film is Tox, the electric field Eox applied to the gate insulating film is Eox = (Q + C2 Vpp) / (C1 + C2) .

E using n-channel cell transistor
In the case of EPROM, writing is performed by injecting electrons into the charge storage layer and storing negative charges, so Eox
It can be seen that becomes smaller as the writing progresses. At this time, the injection of electrons depends on the F-N tunnel current,
The intensity of the F-N tunnel current is strongly proportional to the electric field Eox applied to the gate (tunnel) insulating film. Therefore, the fact that Eox becomes smaller as the writing progresses means that the electron injection efficiency becomes worse as the writing progresses.

In other words, a large value for Vpp is required rather at the time when writing has advanced to some extent,
At the beginning of writing, sufficient injection efficiency can be obtained even if Vpp is made small to some extent. At the same time, by lowering Vpp in the initial stage of writing, the maximum value of the electric field Eox applied to the gate insulating film can be suppressed to a small value, and there is an advantage that deterioration of the gate insulating film can be reduced.
More specifically, this effect is obtained by increasing the rising time of the first pulse of the plurality of pulses during the write operation. The larger the rise time, the greater the expected effect, but it is not realistic to make it too large in consideration of the writing speed.

At the time of writing by the pulse for the second time and thereafter, charges are accumulated in the charge storage layer to some extent.
Even if the pulse rise is delayed, the effect on the deterioration of the gate insulating film cannot be expected as much as the first time, and it is no longer necessary to take a long pulse rise time. How long the rise time of the first pulse is made depends on the balance with the writing speed, but if the rise of the first pulse is made at least slower than the normal rise (pulse rise after the second pulse), the deterioration of the gate insulating film will occur. Can be kept small compared to normal writing.

In the present invention (claims 10 and 12), before erasing data, the data of the memory cell is
It is "1" or "0" data. here,
The threshold value of the memory cell having “0” data is higher than the reference potential. That is, many electrons are injected into the charge storage layer. After that, by applying a higher potential to the substrate, electrons are emitted from the charge storage layer to the substrate to erase the data.
In the case of “0” data, electrons are contained in the charge storage layer, so that the electric field applied to the tunnel oxide film is stronger.

Therefore, according to the present invention, by applying a high potential (H level) to the substrate and an intermediate potential (M level) to the control gate in the first erase operation, the voltage is actually applied between the gate and the substrate. The applied voltage becomes (HM), and the peak electric field applied to the tunnel oxide film is reduced. At this time, the threshold value moves in the negative direction and the number of electrons in the charge storage layer decreases. In the second erase operation, for example, by applying H level to the substrate and applying L (or a potential lower than M) to the control gate, the applied voltage increases, but at this time, electrons escape from the charge storage layer. Since the potential of the storage layer is lowered, the peak electric field applied to the tunnel oxide film can be suppressed. In this way, the peak electric field applied to the tunnel oxide film is suppressed, and problems such as dielectric breakdown and increase in leak current can be improved.

[0050]

First, the basic concept of the present invention will be described before describing the embodiments. The essence of the present invention is to gradually increase the write voltage Vpp (or gradually decrease the select gate voltage Vpp) while repeating the cycle of the write operation and the verify operation for each bit.

The features of the present invention will be described with reference to FIGS. In this example, the threshold of the memory cell having the lowest threshold (that is, the memory cell M2 that is the least likely to be written) is Vth = -4V (E0 in FIG. 1), and the memory cell having the highest threshold (that is, E0). , The threshold value of the memory cell M1 which is most easily written is set to Vth = -1V (F0 in FIG. 1), "0" is written, and the threshold value Vth of the memory cell is set to 0.
The case of setting the voltage in the range of 5 to 2V will be described.

First, a page (or chip) is selected. According to the data to be written in each memory cell of the selected page, if "0" is written, Vss (for example, 0
If "1" is written to V), VbitH (for example, 10)
V) is applied to the bit line connected to each memory cell.
At this time, each memory cell has a variation in the threshold due to the process variation and the previous usage.

A high voltage Vpp (= 18.5V) is applied to the selected word line (that is, the control gate of the selected memory cell),
The first writing is performed. At the time when the first writing is completed, it is checked for each memory cell whether the threshold value Vth of the memory cell is at the judgment level of completion (verify). At this time, the threshold Vth of the memory cell M1 is 1V (E1), and the threshold falls within a predetermined range. However, the threshold Vth of the memory cell M2 is −
Since it is 2V (F1) and the threshold value Vth is not within the predetermined range, it is determined that the writing is not completed.

Again, 10V is applied to the bit line connected to the memory cell (not shown) where writing is not performed and the memory cell where writing is completed, and 0V is applied to the bit line connected to the memory cell where writing is not completed. A constant voltage V applied to the selected word line, which is higher than the first voltage applied to the selected word line.
The second writing is performed by applying pp (eg, 19.5 V). By the second write, the memory cell M1
Has a threshold value Vth of 3V (F3), which falls within a predetermined range. However, the threshold value Vth of the memory cell M2 is -0.5 V (E3), and the threshold value Vth is not within the predetermined range. Therefore, it is determined that the writing is not completed.

In order to write to the memory cell M2,
A constant voltage Vpp (for example, 20.5 V) higher than the voltage applied the second time is applied to the selected word line to perform the third writing. After that, verification and writing are performed while gradually increasing the voltage of the selected word line until the writing of the memory cell M2, which is the hardest to be written, is completed (until the threshold value falls within a predetermined range). Therefore, a cell having a slow program characteristic is programmed at 21.5V, and a cell having a fast program characteristic is programmed at 19.5V, which is programmed at an optimum Vpp for each bit while performing page programming. The present inventors call this method a bit-by-bit verify-voltage rise method.

By doing so, it is possible to eliminate the over-programming of the memory cell as in the bit-by-bit verify-fixed voltage method and prevent the programming time from being long as in the chip-by-chip verify-voltage rising method. .

FIG. 2 is a graph showing the relationship between the programming time and the threshold width after writing to the memory cell. The vertical axis represents the program time, and the horizontal axis represents the range of variation in threshold voltage. In FIG. 2, the curve A shows the case of the chip-by-chip verify-voltage rise method, the curve B shows the case of the bit-by-bit verify-fixed voltage method, and the curve C shows the case of the present invention.

In the case of the chip-by-chip verify-voltage rise method, the threshold width for each memory cell cannot be modified by the program, and the h
It doesn't depend on.

In the case of the bit-by-bit verify-fixed voltage method, the more time it takes to write data, the smaller the variation in threshold value of each memory cell after writing. For example, when the threshold width is 2V, about 500
μsec is sufficient, but it takes about 3 times as long as 1V.

According to the present invention, as compared with the above-mentioned two methods, even when the threshold variation is set to 0.5 V, about 300 μ.
Since it is sec, it is possible to write with less variation in threshold value without requiring a long time.

FIG. 3 is a graph showing the relationship between the maximum electric field (peak electric field) and the coupling coefficient. The vertical axis represents the maximum electric field, and the horizontal axis represents the coupling coefficient. In FIG. 3, the types of curves are the same as those in FIG. 2, so description will be omitted.

According to FIG. 3, the curve A and the curve C show almost the same characteristics. In the curve B, when the coupling coefficient is increased, the maximum electric field is also increased (for example, when the coupling coefficient is 0.5, about 1.2 times the curves A and C).
Therefore, the peak electric field applied to the tunnel oxide film becomes high, and problems such as dielectric breakdown and increase in leak current occur.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing a system configuration of a NAND cell type EEPROM according to an embodiment of the present invention. 1 is an EEPROM chip and 2 is these EEs
This is a control circuit LSI chip for controlling data rewriting of the PROM chip 1.

FIGS. 5A and 5B are a perspective view and a plan view of an LSI memory card which is a specific system configuration example of FIG. Here, four EEPROMs are provided in the card body 3.
A chip 1 and a control circuit LSI chip 2 are mounted. 4 is an external terminal.

FIG. 6 shows a NAND type EE in this embodiment.
It is a block diagram which shows the circuit structure of PROM. A bit line control circuit 26 is provided to write and read data to and from the memory cell array 21. The bit line control circuit 26 includes a data input / output buffer 25.
Leads to. The control gate control circuit 23 outputs a predetermined control signal to the control gate line selected by the row decoder 22 of the memory cell array 21 in response to each of data write, erase, read and verify operations. The substrate potential control circuit 24 normally sets the p-type well in which the cell is formed to 0 V, and erases Vpp (up to 20 V).
To control. The input address is transmitted to the row decoder 23 and the column decoder 27 through the address buffer 28.

Although not shown in the figure, a write potential corresponding to data writing, erasing and reading, which gives necessary write potential Vw, erase potential Ve and intermediate potential Vm to the control gate line, bit line, substrate, etc., respectively. A generation circuit, an erase potential generation circuit, an intermediate potential generation circuit, etc. are provided.

7A and 7B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array,
8A and 8B are cross-sectional views taken along line AA 'and BB' of FIG. 7A, respectively. A plurality of N's are formed on the p-type silicon substrate (or p-type well) 11 surrounded by the element isolation oxide film 12.
A memory cell array composed of AND cells is formed. Explaining one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. In each memory cell, a floating gate 14 (14 ₁ , 14 ₂ , ..., 14 ₈ ) is formed on a substrate 11 via a gate oxide film 13, and a control gate 16 (16 ₁ ，
16 ₂ , ..., 16 ₈ ) are formed and configured.
The n-type diffusion layers 19 which are the sources and drains of these memory cells are connected in series so that adjacent ones are shared with each other.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 1 formed at the same time as the floating gate and the control gate of the memory cell on the drain side and the source side of the NAND cell, respectively.
6 ₁₀ are provided. CVD is performed on the substrate on which elements are formed.
The oxide film 17 covers the bit line 18, and the bit line 18 is disposed on the oxide film 17. The bit line 18 is in contact with the drain diffusion layer 19 at one end of the NAND cell.

Control gate 1 of NAND cells arranged in the row direction
6 are commonly arranged as control gate lines CG1, CG2, ..., CG8. These control gate lines become word lines. The select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also sequentially arranged in the row direction in the select gate lines SGs, SGd.
Is arranged as. FIG. 9 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 10 shows a specific structure of the row decoder of the NAND cell type EEPROM. The row decoder is E
Type, n-channel MOS transistors Qn41, Qn42 and E type, p-channel MOS transistors Qp11, Qp1
Enable circuit consisting of 2 and E type, n channel M
And a transfer circuit including OS transistors Qn43 and Qn44 and E type p-channel MOS transistors Qp13 and Qp14. The row decoder is activated and the block is selected by the address signal ai and the decoder enable signal RDENB. ΦER is “H” when erasing
And work. Further, the voltage VppRW is Vcc during reading and Vpp (up to 20 V) during erasing / writing.

The E type, n-channel MOS transistors Qn50 to Qn69 and the E type, p-channel MOS transistors Qp20 to Qn29 have select gate potentials SG1D and SG2D.
And control gate potentials CG1D to CG8D and Vuss potential,
A transfer gate that receives and transmits the output of the row decoder. Vuss, SG1D, SG2D, and CG1D to CG8D are signals common to each row decoder.

Next, the data erasing operation in this embodiment will be described. FIG. 11 shows the waveforms of the voltages applied to the substrate, the control gate CG, and the select gate SG at the time of erasing. Figure 1
1, the selection gate SG and the non-selected CG'1 to
CG'8 outputs the H level at the first and second times, and the selected word lines CG1 to CG8 output the M level at the first time and the L level at the second time.

Thus, in the data erasing operation, 1
By applying the M level to the word line at the time of applying the erase pulse for the second time, the threshold value is changed while the electric field applied to the tunnel oxide film is lowered, and a high electric field is applied to the tunnel oxide film after the second time. By applying it, the peak electric field applied to the tunnel oxide film is suppressed, and as a result, the EE
The reliability of the PROM is improved.

Next, the data write operation in this embodiment will be described. Writing is performed according to the flowchart shown in FIG. That is, data is set after setting the write mode, and writing is performed in the memory cell. After that, verify read is performed to determine whether or not the written data is normal, and if normal, the write ends. If it is abnormal, the write operation starts again. At this time, the write potential is variably set as described later. Then, if the writing is not normally performed even after writing 10 times, for example, the writing ends as abnormal writing.

SGd, SGs, CG1 to C at the time of writing
The relationship between G8 and the bit line potential in this embodiment (Table 2)
~ (Table 5). Here, it is assumed that CG8 is selected. The "1" write includes the case where the data is originally "1" and the case where the same voltage is applied to the "1" write because the "0" write is completed and no more electrons are injected.

[0076]

[Table 2]

[0077]

[Table 3]

[0078]

[Table 4]

[0079]

[Table 5]

(Table 2) shows that the write voltage is 19-20.
21V shows a case of increasing in two steps. In this case, when the write voltage is increased by 2V, the bit line potential,
Also, the select gate SGd is increased by 1V.

In Table 3, each time the write voltage is increased, the bit line potential and the select gate potential VM are increased. Here, the above voltages are not limited to those in the embodiment, and can be changed appropriately. For example, in the above example, the voltage is increased every 1V, but it may be increased every 0.5V or every 2V. Furthermore, it is not necessary to increase the same difference. Gradually decrease the increase, for example 19V
It may be decreased like -20V-20.5V-20.7V, or conversely, the increase may be gradually increased.

In the above embodiment, the voltage is changed once every time, but for example, 19-19-20-20-2 every two times.
It may be increased like 1-21V, or 19-20-
20-21-21-21V, for example, may be increased at every set number of times. Similarly, the method of increasing the bit line potential, VbitH and VM has many degrees of freedom. Of course, both may be fixed potentials as long as there is a sufficient voltage margin for erroneous writing.

As in the above-mentioned embodiment, the timing of increase does not necessarily have to be the same as the timing of increase of the write voltage, and may be controlled independently. In the above embodiment, V
Although pp is gradually increased, the bit line potential may be lowered while the write voltage is fixed in the sense that the potential difference between the control gate and the source / drain is increased. The bit line potential may be decreased stepwise as shown in Table 4.

Further, it is not necessary to increase both VbitH and VM. For example, VM may be fixed and only VbitH may be increased (Table 5). However, the increased VbitH must be transferred to the selected memory cell. Also, Vbi
tH and VM may have the same potential. In this case, the threshold voltage drops at the drain side select gate, so that the threshold voltage is sent to the bit line. On the contrary, VM applied to SGd
And VM applied to the non-selected memory cells may be different.

Next, the write verify method will be described based on the sense amplifier / data latch circuit (FF) shown in FIG. As shown in FIG. 13, there is a sense amplifier / data latch circuit (FF) composed of a CMOS flip-flop, the first output of which is an E-type, n-channel MOS transistor Qn7 controlled by φF, and a bit line BLi. It is connected to the. Bit line BLi
Between Vcc and Vcc, an E type n-channel MOS transistor Qn8 controlled by the first output of the flip-flop FF and an E type n-channel MOS transistor Qn9 controlled by the signal .phi.V are connected in series. Further, an E type p-channel MOS transistor Qp5 for precharging the bit line and an E type n-channel MOS transistor Qn10 for discharging the bit line are connected. The sense line VDTC and Vss are connected by the detection transistor Qn11 which receives the second output of the flip-flop FF.

At the time of writing, F is written when "1" is written.
"H" is latched at the bit line side node of F, and the intermediate potential is sent to the bit line. FF when writing "0"
"L" is latched at the node on the bit line side of, and VSS is transferred to the bit line.

The write confirmation operation is performed with Qn7 closed.
First, the precharge signal φPB becomes "L" to precharge the bit line to Vcc. In this state, the write data is held in the FF. After that, the selection gate and the control gate are driven. If the cell data is D type, the bit line is discharged to Vss. If the cell data type is E, the bit line maintains the Vcc level. After the selection gate and the control gate are reset, the verify signal φV becomes “H”, and the bit line holding the “1” data is charged to Vcc-Vth. After that, after deactivating the CMOS inverter that constitutes the FF, Gn7 is turned on, the potential of the bit line is sensed and latched, and this is used as rewrite data.

That is, "H" is latched to the bit line of "1" write, and "H" is latched to the bit line of "0" write that has been sufficiently written. further,
Only "0" -written bit lines for which insufficient writing is performed are latched with "L". Rewrite all F
This continues until "H" is latched in the node on the bit line side of F.

This is detected as follows. The sense transistors of all FFs are connected to the sense line SL. VDTC is connected to the p-channel transistor Qpk. After the end of the above-mentioned latch, Qpk is activated for a predetermined time. At this time, if writing of all bits is completed, all the detection transistors are in the OFF state, so VDTC is charged to Vcc. If a cell with insufficient writing remains, the detection transistor corresponding to the bit line is in the ON state, so the potential of VDTC is V
It decreases to ss. By detecting the potential of the VDTC, it is possible to detect whether or not the writing is completed at once (that is, not to read all the bits by changing the address). If writing has not been completed, rewriting is performed.

FIG. 14 shows an example of a limiter circuit for realizing the above write operation. A diode D in a reverse bias state is connected to the output of the booster circuit 29 via a p-type transistor Mp. The breakdown voltage of the diode D is set to 9.5V per stage.

When φ1 and φ2 are set to Vss at the time of the first writing, the p-type transistor Mp3, between the nodes N1 and N3,
Since it is short-circuited by Mp4, 19V is output as Vpp. In the second writing, φ1 is set to Vpp and φ2 is set to Vss. At this time, the nodes N2 and N3 are short-circuited, but the p-type transistor M is connected between the nodes N1 and N2.
The voltage drops by the threshold value Vth of p1. Therefore, if the threshold of this p-type transistor is set to 1 V, the output Vpp
Is 20V. Similarly, at the time of the third writing, φ1,
Both φ2 and Vpp. Therefore, Vpp of 21V is output together with the voltage drop of two stages of Vth.

As described above, a desired voltage can be obtained by detecting the number of times of writing and controlling the limiter circuit. Here, two stages of p-type transistors are used, but various modifications are possible. Transistors having different thresholds may be arranged to change the increased voltage, or three or more transistors having the same threshold may be arranged to be divided into two stages and one stage. Furthermore, you may combine p type and n type. Further, a booster circuit can be formed for VM and VbitH with the same configuration.

The write and verify read cycles may be automatically performed inside the chip or may be controlled outside the chip. In the case of automatic control inside the chip, a counter circuit for storing the number of times of writing is provided, and the set voltage of the booster circuit limiter is switched according to its output signal or the like. Also, keep the Ready / busy pin busy during the write-verify cycle and confirm the completion of the write by verify read, or if the write is not completed even after the specified number of times of write and verify are repeated, the Ready / busy pin Is returned to the ready state and, for example, information indicating whether the verification is completed is output to a specific I / O pin. Naturally, Rea
The counter circuit is reset at a predetermined timing, such as when the dy / busy pin returns to Ready or after that, a reset signal is input.

When controlling outside the chip, a command for data input, write, verify, etc. is provided, a verify command is input when writing is completed, and a write command is input again if writing is not completed. At that time, a CPU or the like outside the chip remembers the number of times of writing. At the time of such control, for example, three types of write commands are prepared, and the output voltage of the booster circuit is associated with each of them. By doing so, the write voltage can be controlled according to the number of times of writing.

By such a write verify operation, the following effects can be obtained. That is, since the first-time write potential is lower than in the conventional case, even if the limiter varies in the high voltage direction, the upper limit of the threshold distribution is not exceeded and the limiter process control becomes easy. Further, by gradually raising the write potential, the number of times of verification can be reduced, and the write time can be shortened. Further, since the first write potential at which the largest electric field is applied to the tunnel oxide film is set low, deterioration of the tunnel oxide film can be prevented and the reliability of the memory cell can be improved.

Next, another example in the case of performing the write verify will be described. First, a memory cell array block for writing data is selected. Prior to data writing to the selected block, data erasing of the memory cells of all NAND cells in the block is performed. When erasing data, all control gate lines (word lines)
0V is applied to CG. At this time, the select gate line SGs
, SGd, the bit line, the source line and the p-type substrate (or p-type well) on which the memory cell array is formed, the erase potential V
e is applied. The erase potential Ve is also applied to the control gate line of the non-selected block. This bias condition is
By holding for 10 ms, electrons are emitted from the floating gates in all the memory cells in the selected block, and the threshold value moves in the negative direction.

Then, an erase verify operation for checking whether the threshold value of the erased memory cell is sufficiently negative is started. The control gates of all the memory cells in the selected NAND cell are set to 0V. The select gates SGs and SGd are set to, for example, 5V, a read potential of 1.5V is applied to the bit line, and the source line and the p-type substrate (or p-type well) are set to 0V. At this time, the time when the select gates SGs and SGd are set to 5V is set to the time when the data "0" can be read if the threshold value of the erased memory cell is negative to some extent. If the data “0” is not read in time, the data is erased again and the verify operation is repeated until the condition is satisfied.

Then, the data write operation is started. For data writing, word data for the number of NAND cell stages,
For example, if there is a case of forming 1 NAND with 8 bits,
8 words of data are latched in the data latch circuit,
The bit line potential is controlled by the data and "0" or "1" is written. At this time, the write potential Vw is applied to the selected control gate line and the intermediate potential VM is applied to the non-selected control gate line. Further, the bit line BL is supplied with 0V when writing data "1" and with an intermediate potential VM when writing data "0". Further, at the time of this writing operation, the intermediate potential VM is given to the selection gate SGd,
0V is applied to the select gate SGs and the p-type substrate (or p-type well).

By keeping the bias state of this data write for 1 ms, for example, the threshold value shifts in the positive direction in the memory cell in which "1" is written, and the threshold value in the memory cell in which "0" is written. The value stays negative.

Then, the write verify operation is started.
In this embodiment, whether or not the threshold value of the memory cell in which the data "1" is written is equal to or higher than a desired value is checked by the write verify potential VVER. This threshold value is determined in consideration of the data retention characteristic of the memory cell, and is set to, for example, 1.5V.

Specifically, first, the write verify potential VVER is supplied to the selected control gate line. Vcc is supplied to the other control gate lines. At this time, the select gates SGs and SGd which are simultaneously selected are both set to Vcc, a read potential of 1.5V is applied to the bit line, and the source line is set to 0V. As a result, if the selected memory cell is the one to which "1" is written and the threshold value thereof exceeds the write verify potential, the selected memory cell becomes non-conductive and data "1" is written.
Is read. When the "1" write is insufficient and the threshold value has not reached the write verify potential, the selected memory cell becomes conductive, so that it is read as data "0" and the "1" data is written again. And the stress relaxation operation 2 is repeated. Then, the verify operation is performed again, and the operation is repeated until the write verify potential is exceeded.

Here, writing is performed by a plurality of pulses that are repeatedly applied until a desired cell Tr threshold value is obtained. The conceptual diagram of the circuit for applying the write potential is as shown in FIG. 14 in this embodiment. That is, the ring oscillator 31 that gives a signal to the booster circuit 32.
On the other hand, a signal is given from the write number counter 30 in the controller of the program system, and by this signal, the cycle of the ring oscillator 31 is delayed only for the first write potential pulse, Increase the pulse rise time for the second and subsequent pulses.

An example of a circuit for making the cycle of the ring oscillator 31 variable is as shown in FIG. Normally, “L” potential (for example, 0V) is applied to Vselect, but when it is desired to delay the cycle, Vselect is provided with an “H” potential (for example, 5V). By adding the above-described pulse rise speed control circuit to the conventional circuit, the rise time of the first pulse can be made longer than in the second and subsequent times, and the deterioration of the gate insulating film can be made smaller than in the conventional case. . It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0104]

As described above in detail, according to the present invention, the peak electric field applied to the tunnel oxide film at the time of erasing data or writing data can be suppressed, and the dielectric breakdown of the tunnel oxide film and the increase of leak current can be suppressed. This can be prevented, and thus reliability of the memory cell can be improved.
Further, by controlling the write potential according to the number of times of writing, it is possible to realize a write verify method that can suppress an increase in write time even if the cell characteristics vary.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention.

FIG. 2 is a diagram showing a relationship between a program time and a threshold width after writing to a memory cell.

FIG. 3 is a diagram showing a relationship between a maximum electric field (peak electric field) and a coupling coefficient.

FIG. 4 is a block diagram showing a NAND cell type EEPROM system configuration according to an embodiment.

5 is a perspective view and a plan view of an LSI memory card which is a specific system configuration example of FIG.

FIG. 6 is a diagram showing a configuration of a NAND type EEPROM in the present embodiment.

FIG. 7 is a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array.

FIG. 8 is a view showing a cross section taken along the line AA ′ and the line BB ′ of FIG.

FIG. 9 is a diagram showing an equivalent circuit of a cell array in which NAND cells are arranged in a matrix.

FIG. 10 is a diagram showing a specific configuration of a row decoder of a NAND cell type EEPROM.

FIG. 11 is a diagram showing waveforms of voltages applied to a substrate, a control gate, and a select gate at the time of erasing.

FIG. 12 is a flowchart showing how writing is performed.

FIG. 13 is a diagram showing an example of a sense amplifier / data latch circuit.

FIG. 14 is a diagram showing an example of a limiter circuit for realizing the write operation of the embodiment.

FIG. 15 is a diagram showing write characteristics in an example.

FIG. 13 is a diagram showing write characteristics in a conventional example.

FIG. 14 is a conceptual diagram of a circuit for applying a write potential.

FIG. 15 is a diagram showing an example of a circuit for varying the cycle of the ring oscillator.

FIG. 16 is a diagram for explaining a verify-voltage rise method for each chip.

FIG. 17 is a diagram for explaining a bit-by-bit verify-fixed voltage method.

[Explanation of symbols]

1 ... EEPROM chip, 2 ... control circuit LSI chip,
3 ... Card body, 4 ... External terminal, 11 ... P-type silicon substrate, 12 ... Element isolation oxide film, 13 ... Tunnel oxide film (first gate insulating film), 14 ... Floating gate,
15 ... Interlayer insulating film, 16 ... Control gate,
17 ... CVD oxide film, 18 ... Bit line, 19 ... N-type diffusion layer, 21 ... Memory cell array, 22 ... Row decoder, 23 ...
Control gate control circuit, 24 ... Substrate potential control circuit, 25 ... Data input / output buffer, 26 ... Bit line control circuit, 27 ... Column decoder, 28
... address buffer, 29 ... booster circuit.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 8, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention.

FIG. 2 is a diagram showing a relationship between a program time and a threshold width after writing to a memory cell.

FIG. 3 is a diagram showing a relationship between a maximum electric field (peak electric field) and a coupling coefficient.

FIG. 4 is a block diagram showing a NAND cell type EEPROM system configuration according to an embodiment.

5 is a perspective view and a plan view of an LSI memory card which is a specific system configuration example of FIG.

FIG. 6 is a diagram showing a configuration of a NAND type EEPROM in the present embodiment.

FIG. 7 is a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array.

FIG. 8 is a view showing a cross section taken along the line AA ′ and the line BB ′ of FIG.

FIG. 9 is a diagram showing an equivalent circuit of a cell array in which NAND cells are arranged in a matrix.

FIG. 10 is a diagram showing a specific configuration of a row decoder of a NAND cell type EEPROM.

FIG. 11 is a diagram showing waveforms of voltages applied to a substrate, a control gate, and a select gate at the time of erasing.

FIG. 12 is a flowchart showing how writing is performed.

FIG. 13 is a diagram showing an example of a sense amplifier / data latch circuit.

FIG. 14 is a diagram showing an example of a limiter circuit for realizing the write operation of the embodiment.

FIG. 15 is a diagram showing write characteristics in an example.

FIG. 16 is a diagram for explaining a verify-voltage rise method for each chip.

FIG. 17 is a diagram for explaining a bit-by-bit verify-fixed voltage method.

[Explanation of Codes] 1 ... EEPROM chip, 2 ... control circuit LSI chip,
3 ... Card body, 4 ... External terminal, 11 ... P-type silicon substrate, 12 ... Element isolation oxide film, 13 ... Tunnel oxide film (first gate insulating film), 14 ... Floating gate,
15 ... Interlayer insulating film, 16 ... Control gate,
17 ... CVD oxide film, 18 ... Bit line, 19 ... N-type diffusion layer, 21 ... Memory cell array, 22 ... Row decoder, 23 ...
Control gate control circuit, 24 ... Substrate potential control circuit, 25 ... Data input / output buffer, 26 ... Bit line control circuit, 27 ... Column decoder, 28
... address buffer, 29 ... booster circuit. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] September 9, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0102

[Correction method] Change

[Correction content]

Here, writing is performed by a plurality of pulses that are repeatedly applied until a desired cell Tr threshold value is obtained. A conceptual diagram of a circuit for applying a write potential is as shown in FIG. 18 in this embodiment. That is, the ring oscillator 31 that gives a signal to the booster circuit 32.
On the other hand, a signal is given from the write number counter 30 in the controller of the program system, and by this signal, the cycle of the ring oscillator 31 is delayed only for the first write potential pulse, Increase the pulse rise time for the second and subsequent pulses.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0103

[Correction method] Change

[Correction content]

An example of a circuit for making the cycle of the ring oscillator 31 variable is as shown in FIG. Normally, “L” potential (for example, 0V) is applied to Vselect, but when it is desired to delay the cycle, Vselect is provided with an “H” potential (for example, 5V). By adding the above-described pulse rise speed control circuit to the conventional circuit, the rise time of the first pulse can be made longer than in the second and subsequent times, and the deterioration of the gate insulating film can be made smaller than in the conventional case. . It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention.

FIG. 2 is a diagram showing a relationship between a program time and a threshold width after writing to a memory cell.

FIG. 3 is a diagram showing a relationship between a maximum electric field (peak electric field) and a coupling coefficient.

FIG. 4 is a block diagram showing a NAND cell type EEPROM system configuration according to an embodiment.

5 is a perspective view and a plan view of an LSI memory card which is a specific system configuration example of FIG.

FIG. 6 is a diagram showing a configuration of a NAND type EEPROM in the present embodiment.

FIG. 7 is a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array.

FIG. 8 is a view showing a cross section taken along the line AA ′ and the line BB ′ of FIG.

FIG. 9 is a diagram showing an equivalent circuit of a cell array in which NAND cells are arranged in a matrix.

FIG. 10 is a diagram showing a specific configuration of a row decoder of a NAND cell type EEPROM.

FIG. 11 is a diagram showing waveforms of voltages applied to a substrate, a control gate, and a select gate at the time of erasing.

FIG. 12 is a flowchart showing how writing is performed.

FIG. 13 is a diagram showing an example of a sense amplifier / data latch circuit.

FIG. 14 is a diagram showing an example of a limiter circuit for realizing the write operation of the embodiment.

FIG. 15 is a diagram showing write characteristics in an example.

FIG. 16 is a diagram for explaining a verify-voltage rise method for each chip.

FIG. 17 is a diagram for explaining a bit-by-bit verify-fixed voltage method.

FIG. 18 is a conceptual diagram of a circuit for applying a write potential.

FIG. 19 is a diagram showing an example of a circuit for varying the cycle of the ring oscillator.

[Explanation of Codes] 1 ... EEPROM chip, 2 ... control circuit LSI chip,
3 ... Card body, 4 ... External terminal, 11 ... P-type silicon substrate, 12 ... Element isolation oxide film, 13 ... Tunnel oxide film (first gate insulating film), 14 ... Floating gate,
15 ... Interlayer insulating film, 16 ... Control gate,
17 ... CVD oxide film, 18 ... Bit line, 19 ... N-type diffusion layer, 21 ... Memory cell array, 22 ... Row decoder, 23 ...
Control gate control circuit, 24 ... Substrate potential control circuit, 25 ... Data input / output buffer, 26 ... Bit line control circuit, 27 ... Column decoder, 28
... address buffer, 29 ... booster circuit.

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 18

[Correction method] Added

[Correction content]

FIG. 18

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 19

[Correction method] Added

[Correction content]

FIG. 19

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/788 29/792 7210-4M H01L 27/10 434 29/78 371 (72) Inventor Shirata Riichiro 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Within Toshiba Research and Development Center (72) Inventor Seiichi Aridome 1 Komu-shi Toshiba-cho, Kouki-Toshiba, Kawasaki, Kanagawa Prefectural Research and Development Center, Toshiba ( 72) Inventor Tomoharu Tanaka 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (17)

[Claims] 1. A memory cell array in which a plurality of electrically rewritable and erasable memory cells are arranged in a matrix, a plurality of bit lines connected to a drain of the memory cell, and a control gate of the memory cell. A plurality of word lines and a first word line selected from the selected word lines at the time of page writing.
A write potential is applied and connected to the selected word line,
The first bit line is connected to the memory cell for writing.
A bit line potential is applied and connected to the selected word line,
Writing means for applying a second bit line potential to a bit line to which a memory cell not to be written is connected; and information written by the writing means. And a rewriting unit that sequentially increases the first write potential according to the number of times of writing, and a non-volatile semiconductor memory device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the rewriting means includes means for variably setting the first and second bit line potentials. 3. A nonvolatile memory according to claim 1, further comprising means for setting the rise time of the first write pulse to be longer than the rise time of the second and subsequent pulses in data writing by a plurality of pulses. Semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the memory cells are connected in series to form a NAND cell. 5. A first select gate connected to one end of the NAND cell and the bit line, a second select gate connected to the other end of the NAND cell, and the NAND via a second select gate. The non-volatile semiconductor memory device according to claim 4, further comprising a source line connected to the other end of the cell. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cells are connected in parallel to the bit line to form a memory cell unit. 7. A memory cell having a common drain connected to a bit line via a first select gate and a common source line connected to a common source line via a second select gate,
The nonvolatile semiconductor memory device according to claim 1, having a NOR structure connected in parallel to the bit line. 8. The non-volatile memory according to claim 1, further comprising means for setting a first write pulse to a potential at which a memory cell which is cheapest to be written is not over-programmed in writing data by a plurality of pulses. Semiconductor memory device. 9. A nonvolatile semiconductor memory according to claim 1, further comprising means for setting an upper limit potential of a write pulse to a withstand voltage of the memory cell and its peripheral circuit in writing data by a plurality of pulses. apparatus. 10. A semiconductor substrate, source and drain regions formed on the surface of the semiconductor substrate, a first gate insulating film sequentially stacked on the semiconductor substrate, a charge storage layer, and a second gate insulating film. And a control gate, which is electrically rewritable by exchanging charges between the charge storage layer and the semiconductor substrate, and when erasing data, a high potential is applied to the semiconductor substrate for the first time. And an intermediate potential is applied to the control gate, a high potential is applied to the semiconductor substrate and a low potential is applied to the control gate from the second time onward, and a charge is extracted from the charge storage layer. And a nonvolatile semiconductor memory device. 11. The nonvolatile semiconductor memory device according to claim 10, wherein the high potential is a boosted potential, the intermediate potential is a power source potential, and the low potential is a ground potential. 12. A semiconductor substrate, source and drain regions formed on the surface of the semiconductor substrate, a first gate insulating film sequentially stacked on the semiconductor substrate, a charge storage layer, and a second gate insulating film. A plurality of memory cells that have a control gate and are electrically rewritable by transfer of charges between the charge storage layer and the semiconductor substrate; and the memory cells are arranged in a matrix. When erasing data, a high potential is applied to the control gates of the semiconductor substrate and unselected memory cells at the first time, an intermediate potential is applied to the control gates of the selected memory cell, and the semiconductor substrate and unselected memory are applied at the second time and thereafter. A means for applying a high potential to the control gate of the cell and a potential lower than the intermediate potential to the control gate of the selected memory cell to extract the charge from the charge storage layer. The nonvolatile semiconductor memory device according to claim. 13. The nonvolatile semiconductor memory device according to claim 12, wherein the high potential is a boosted potential, the intermediate potential is a power source potential, and the low potential is a ground potential. 14. A memory cell array in which a plurality of electrically rewritable and erasable memory cells are arranged in a matrix, and a plurality of bit lines connected to the drain of the memory cell array and connected to a control gate of the memory cell. By having a plurality of word lines, the plurality of memory cells connected to the same word line, by applying a different program or erase pulse for each memory cell,
Means for programming or erasing the selected memory cell in the same operation. 15. The non-volatile semiconductor memory device according to claim 14, wherein said program pulse or erase pulse is applied during a program or erase period of said plurality of memory cells. 16. The word line is provided to the word line by means for varying the maximum value of the voltage applied between the channel and the control gate for each memory cell during the operation period for programming or erasing the plurality of memory cells. 16. The non-volatile semiconductor memory device according to claim 15, further comprising means for programming or erasing a plurality of connected selected memory cells. 17. A means for applying a time-increasing voltage to the selected word line, and a different program or erase pulse for each memory cell,
And a means for programming or erasing the selected memory cell in the same operation, and a means for programming or erasing the selected memory cell by means of applying the word line voltage only for a different time for each memory cell. 16. The non-volatile semiconductor memory device according to claim 15, wherein