JP4988264B2 - Nonvolatile memory device for controlling gradient of word line voltage and program method thereof - Google Patents

Description

  The present invention generally relates to non-volatile memory devices, and more particularly, to a non-volatile memory device for controlling a gradient of a word line voltage and a program method thereof. The present invention also relates to a memory system including the nonvolatile memory device.

  Semiconductor memories are classified into volatile semiconductor memories and nonvolatile semiconductor memories. The volatile memory can read the stored data while power is supplied, and if the power is turned off, the data is lost. On the other hand, non-volatile memories such as MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM) and flash memory can store data even when the power is turned off. .

  The flash memory in the nonvolatile memory device is classified into a NOR flash memory and a NAND flash memory according to the connection structure between the cells and the bit lines. The NOR flash memory can be easily applied to high-speed operation, but has a disadvantage in integration. On the other hand, the NAND flash memory has an advantage in the degree of integration.

  1A and 1B respectively show an initial state and a programmed state of a flash memory cell transistor having a floating gate.

  Referring to FIGS. 1A and 1B, a single transistor flash memory cell 100 generally includes a channel formed between a source 105 and a drain 110 on a semiconductor memory substrate 115, a control gate 120, and a dielectric oxide film. 140 and a floating gate 130 formed between the gate oxide film 150. Here, the dielectric oxide film 140, the floating oxide film 130, the gate oxide film 150, and the control gate 120 are connected in a stack on the channel. The floating gate 130 traps electrons. The trapped electrons form a threshold voltage for the flash memory cell 100. Electrons moving to the floating gate 130 are generated by FN tunneling and electron injection. Electron injection is performed by CHE (Channel hot-electron injection), CISEI (Channel-Initiated Secondary Electron Injection), or the like. In general, FN tunneling is used to erase data at a time in a flash memory device. Further, when the nonvolatile semiconductor memory device performs a read operation, a data value stored in the flash memory cell 100 is determined by sensing a threshold voltage of the flash memory cell 100. This will be described in detail below.

  Referring to FIG. 1A, the initial flash memory cell 100 is in an unprogrammed state. Therefore, the flash memory cell 100 logically stores “1”. In the unprogrammed state, the flash memory cell 100 has an initial threshold voltage Vth1. Here, if a voltage lower than the threshold voltage Vth1 is applied to the control gate 120, the flash memory cell 100 is turned off. If a voltage higher than the threshold voltage Vth1 is applied to the control gate 120, the flash memory cell 100 is turned on.

  On the other hand, referring to FIG. 1B, the flash memory cell 100 logically stores “0” when it is in a programmed state. In the programmed state, the memory cell 100 has a second threshold voltage Vth2 that is higher than the threshold voltage Vth1. Here, if a voltage lower than the threshold voltage Vth2 is applied to the control gate, the flash memory cell 100 is turned off. If a voltage higher than the threshold voltage Vth2 is applied to the control gate 120, the flash memory cell 100 is turned on.

  2A and 2B illustrate an erase operation and a program operation for the flash memory cell 100, respectively.

  Referring to FIG. 2A, the erase operation causes the flash memory cell 100 to logically store “1”. Here, in order to remove electrons from the floating gate 130 of the memory cell 100, the erase voltage Vearse is applied to the bulk substrate of the flash memory cell 100, and the control gate 120 is grounded. Referring to FIG. 3, electrons removed from the floating gate 130 reduce the threshold voltage Vth1 of the flash memory.

  FIG. 3 shows that the threshold voltage Vth1 of all the memory cells of the nonvolatile memory device is not the same, and instead shows how the threshold voltage Vth1 has a variance and deviation with respect to the average value. For example, the threshold voltage Vth1 is distributed between 1V and 3V. After the erase operation is performed on the flash memory cell 100, the flash memory cell 100 referred to as the “erased cell” logically stores “1”. Generally, the erase voltage Verase is higher than the operating voltage Vcc of the NAND flash memory device. For example, the erase voltage Verase may be 19V when the operating voltage Vcc is 5V.

  Referring to FIG. 2B, the program operation causes the flash memory cell 100 to logically store “0”. Here, the program voltage Vpgm is used to generate electrons stored in the plotting gate 130. The program voltage Vpgm is applied to the control gate 120 of the flash memory cell 100 to generate a current that flows through the source 105 and the drain 110. Referring to FIG. 3, electrons increase the threshold voltage Vth2 of the flash memory cell 100. FIG. 3 shows that the threshold voltage Vth2 of all the memory cells of the nonvolatile memory device is not the same, and instead shows how the threshold voltage Vth2 has a variance and deviation with respect to the average value. For example, the threshold voltage Vth2 is distributed between 1V and 3V. After the program operation is performed on the flash memory cell 100, the mentioned “programmed cell” or flash memory cell 100 logically stores “0”.

  The NAND flash memory device includes a memory cell array (or memory block). The memory cell array includes a plurality of NAND flash memory cell strings 300. Here, the NAND flash memory cell string 300 is generally connected from the bit line BL0 to the bit line BLn-1.

  FIG. 4 shows a typical NAND flash memory string 400. Each string 400 includes a string selection transistor (SST), a ground selection transistor (GST) and a plurality of flash memory cells 100 connected in series between the SST and the GST. SST includes a drain connected to the corresponding bit line and a gate connected to SSL. Memory cell 100 is connected to each corresponding word line from word line WL0 to word line WLn-1. Although not shown in FIG. 4, the word lines WL to WLn−1, SSL, and GSL are controlled by a row selection circuit.

  The NAND flash memory device can perform a program operation on an individual flash memory cell string 400. However, the NAND flash memory device can perform only the erase operation in only one memory block.

  In order to program selected row (or word line) memory cells of a NAND flash memory device, the memory cells of a memory block (or memory array) must first be erased. This is because a threshold voltage of 0 V or less is applied to each memory cell (all memory cells logically store “1”). Once the memory cell is erased, the program data is loaded into the page buffer of the NAND flash memory device. Thereafter, the high voltage pump circuit generates each high voltage for program operation. Thereafter, the loaded data is programmed from the memory cells of the selected word line by repeating the program loop. Each program loop includes a bit line setup section, a program section, a discharge / recovery section, and a verification section.

  During the bit line setup period, the bit lines BL0 to BLn-1 are charged to the power supply voltage Vcc or the ground voltage according to the loaded program data. That is, referring to FIG. 5, the bit line BL is charged to the ground voltage so that the memory cell is programmed, and charged to the power supply voltage Vcc so that the memory cell is not programmed.

  In the program period, the program voltage Vpgm is applied to the selected word line, and the lower pass voltage Vpass is applied to the unselected word line. In the case of a memory cell connected to a selected word line and connected to a charged bit line connected to ground voltage, the channel voltage is 0V. Therefore, a sufficient bias condition (for example, 18V) is satisfied to reduce FN tunneling. Therefore, electrons are injected from the bulk into the floating gate of the memory cell. On the other hand, as is well known, in the case of a memory cell connected to a bit line charged to the power supply voltage Vcc, the SST is electrically turned off, and the channel voltage of the memory cell connected to the selected word line is self-posting. (Self-Boosting) raises the voltage to a level sufficient to prevent FN tunneling. Therefore, the memory cell is prevented from being programmed (see FIG. 6).

  The voltage of the bit line and the word line is discharged during a discharge period that acts as a recovery period. A determination as to whether the memory cell has been programmed to a desired target threshold voltage is made during the verification interval.

  Step pulse programming techniques have been developed for programming flash memory devices. FIG. 7 shows that a pulse program voltage is applied to the selected word line connected to the control gate of the flash memory cell to be programmed. Referring to FIG. 7, a program voltage (for example, 18V) is applied to a word line selected by a program pulse. Between each program pulse is a “confirmation period” in which data stored in the memory cell to be programmed is read. When determining whether the memory cell connected to the selected word line has been programmed as desired, the program is performed by charging the bit line associated with the memory cell to Vcc, as shown in FIG. Make sure that the action is prevented.

  Generally, a program operation and an erase operation are repeatedly performed in a memory cell of a nonvolatile memory device. Flash memory cells are programmed on a page basis. That is, for example, a flash memory cell is configured such that 512 bytes of memory are programmed simultaneously.

  On the other hand, the flash memory cell is erased in units of one block. That is, for example, flash memory cells are simultaneously erased in units of 32 pages (for example, 16 Kbytes of memory).

  In order to read data stored in the memory cell, a voltage Vread is applied to the control gate of the memory cell. Vread is selected between Vth1 and Vth2. (Vth1 <Vread <Vth2). For example, here, Vth1 is generally −2V, Vth2 is 2V, and Vread is 0V (ground). In this case, if the memory cell is turned on when Vread is applied to the control gate, the memory cell becomes an erased cell, i.e., whether it logically stores "1". Determined. On the other hand, when Vread is applied to the control gate, if the memory cell is in a turn-off state, it is determined whether the memory cell has become a programmed cell, that is, whether it is logically storing “0”. Is done.

  Referring to FIG. 3, the memory cells of the memory device generally have various first and second threshold voltages Vth1 and Vth2. The first and second threshold voltages are distributed around the average value with a certain deviation. However, if the dispersion and deviation of the threshold voltage become too wide, the difference between the first and second threshold voltages gradually decreases. Therefore, an operation margin and a noise margin are reduced with respect to Vread for reading data from the memory cell.

  ISSP (Incremental Step Pulse Program) technology has been developed to program flash memory cells to reduce the difference in threshold voltage between flash memory cells in a flash memory device. Referring to FIG. 8, a pulse for gradually increasing a voltage level is applied to a selected word line. However, the operation is the same as described in FIG. FIG. 9 shows how the threshold voltage distribution changes after applying a first pulse, a second pulse having a voltage greater than the first pulse, a third pulse having a voltage greater than the second pulse, and the like. If the ISPP technology is used, the threshold voltage difference between the flash memory cells in the flash memory device is reduced.

  However, the flash memory cell program technology including the above-mentioned ISSP technology has a problem. This problem will be described with reference to FIGS.

  FIG. 10 illustrates a flash memory cell string 1000 that includes parasitic coupling capacitance that exists between word lines connected to various memory cells. Of interest is the capacitance 1010 between the word line WL31 and a nearby SSL (String Selection Line). FIG. 11 illustrates that parasitic coupling capacitance can cause problems when a word line is selected during a flash memory cell program operation.

  In particular, during the flash memory cell program operation, the power supply voltage Vcc is applied to SSL, and the channel voltages of all memory cells in the string 1100 are raised to “Vcc−Vth”. Thereafter, if the word line WL31 is selected, the program voltage Vpgm of each high voltage level (for example, 15 to 18 V) is applied to the word line WL31. Therefore, the memory cell 1050 connected to the word line is programmed. On the other hand, a low pass voltage Vpass is applied to the remaining unselected word lines. Vpass is a voltage that is sufficient to turn on a memory cell connected to an unselected word line when the bit line is grounded, but not sufficient to program the memory cell.

  Referring to FIG. 11, due to the capacitance 1010 between the word line WL31 and the nearby SSL, the rising edge of the program voltage Vpgm causes a voltage spike in the SSL. This spike will increase the voltage of the SST control gate to be "VSSL> (Vcc + Vth)". On the other hand, as described above, if the memory cell 1050 connected to the selected word line WL31 is not programmed, the associated bit line is connected to the power supply voltage Vcc. In this case, when the gate voltage of the SST becomes “Vssl> (Vcc + Vth)”, the SST is turned on. As shown in FIG. 11, the channel voltage of the memory cell 1050 decreases. A decrease in the channel voltage of the memory cell 1050 combined with the program voltage Vpgm applied to the control gate of the memory cell 1050 provides a bias condition for the FN tunneling to occur in the memory cell 1050. Accordingly, the program-protected memory cell 1050 is programmed. Furthermore, due to the coupling capacitance, a similar problem will occur with other word lines located near SSL.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory device and a programming method thereof that can increase the programming speed by adjusting the rising slope of the word line voltage. Another object of the present invention is to provide a memory system including such a nonvolatile memory device.

  A non-volatile memory device according to the present invention generates a first and second voltage pulse sequence and includes a non-volatile memory cell array including a plurality of non-volatile memory cells connected to a plurality of word lines, and connects the selected word lines. Voltage generation for selecting one of the word lines to selectively provide one of the first and second voltage pulse sequences to program the programmed nonvolatile memory cell. The slope of at least one voltage pulse in one voltage pulse sequence is greater than the slope of at least one voltage pulse in the second voltage pulse sequence.

  Another aspect of the non-volatile memory device according to the present invention includes a plurality of non-volatile memory cells connected to a plurality of word lines and a plurality of bit lines, a memory cell of each bit line including a plurality of strings, A non-volatile memory cell array including an array including a plurality of selection lines for selecting a string and a word line including a first word line set of at least one word line or a second word line set of at least one word line; Selecting one of the word lines to generate first and second voltage pulse sequences of voltage pulses for programming the connected nonvolatile memory cells, and the selected word line is connected to the first word line set. When belonging, providing the first voltage pulse sequence to the selected word line; And a word line voltage generator for providing the second voltage pulse sequence when the selected word line belongs to a second word line set, the second word line set being more than the first word line set. Close to one of the selected lines, the slope of at least one of the voltage pulses of the first voltage pulse sequence is greater than the slope of at least one of the voltage pulses of the second voltage pulse sequence. Features.

  A method of programming a non-volatile memory device including a non-volatile memory cell array having a plurality of non-volatile memory cells connected to a plurality of word lines according to the present invention programs a non-volatile memory cell connected to a first word line. Applying a first voltage pulse sequence to the first word line and applying a second voltage pulse sequence to the second word line when programming a non-volatile memory cell connected to the second word line. Wherein the slope of at least one voltage pulse of the first voltage pulse sequence is greater than the slope of at least one voltage pulse of the second voltage pulse sequence.

  A memory system according to the present invention generates a first and second voltage pulse sequence having a plurality of nonvolatile memory cells connected to a plurality of word lines, and is connected to a selected word line. One of the first and second voltage pulse sequences is selectively provided to a word line for programming the nonvolatile memory cell, and a gradient of at least one voltage pulse of the first voltage pulse sequence is the second voltage pulse sequence. A word line voltage generator characterized by greater than the slope of at least one voltage pulse of the voltage pulse sequence, and the selected to write data to a non-volatile memory cell connected to the selected word line; And a memory controller for providing an address corresponding to the word line.

  The nonvolatile memory device according to the present invention may include a program voltage controller and provide a program voltage having a different rising slope according to a word line. According to the present invention, the program speed is increased and the program time is shortened.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings in order to describe in detail so that a person having ordinary knowledge in the technical field to which the present invention belongs can easily implement the technical idea of the present invention. explain.

  FIG. 12 is a timing diagram for explaining a conventional problem solving process. Referring to FIG. 12, by reducing the slope of the program voltage Vpgm applied to the selected word line (increasing the rising time), the voltage spikes induced by the SSL coupling capacitance are reduced. Or removed. Accordingly, the SST is prevented from being turned on when connected to a bit line charged to Vcc during a program operation. That is, the decrease in the channel voltage of the memory cell connected to the selected word line that must be prevented from being programmed is suppressed. Therefore, FN tunneling does not occur and the program prevention function operates properly.

  However, if the gradient of the program voltage Vpgm decreases (if the rising time decreases), the time required for the corresponding program operation increases.

  The present invention is advantageous in providing a nonvolatile memory device that can solve the above-described problems. It is also advantageous to provide a method for programming such a non-volatile device. Furthermore, it is advantageous to provide a memory system including such a nonvolatile memory device.

  FIG. 13 shows voltage pulses used to program memory cell strings 1300 and corresponding string 1300 memory cells of a non-volatile memory device (eg, flash). Referring to FIG. 13, program pulse gradients or rising times have different configurations for different word lines. Here, the word line is connected to the memory cell of the string 1300. In particular, in the embodiment of FIG. 13, the slope of the program pulse for word lines WL30, WL31 located near SSL is smaller than the slope of the program pulse for word lines WL0-WL29 not located near SSL. Thus, the voltage pulses connected to the selected word line can have a reduced slope (increasing the rising time) to suppress spikes caused by the capacitance coupled to the control gate of the SST. Such spikes cause the program prevention function to fail. On the other hand, the word lines selected to prevent such problems should be far enough away from the SSL (very low coupling to the SSL). The selected word line can be driven with voltage pulses having an increased slope (to increase the rising time) to increase the programming speed.

  FIG. 14 illustrates an embodiment of voltage pulses used to program a memory cell in a non-volatile (eg, flash) memory device. Here, the word lines are classified into two sets. In the embodiment shown in FIG. 14, the word lines of the non-volatile memory device have a first word line set (for example, WL0 to WL29) that is not located near SSL and one that is located near SSL. Alternatively, a plurality of second word line sets (for example, WL30 and WL31) are distinguished. As shown, ISSP technology uses all of the two sets. However, the gradient of one or many voltage pulses in the first voltage pulse sequence (first ISSP pattern) of the first word line set is the same as the gradient of the second voltage pulse sequence (second ISSP pattern) of the second word line set. Greater than the slope of the voltage pulse. As a result, the program prevention function can be ensured to operate normally in all word lines. And the overall block program time is only slightly increased compared to a device that uses the second ISSP pattern for all word lines. In particular, in the case of a string having a length of 32 memory cells, if the programming time of the voltage pulse of the first ISSP pattern is Tpgm1 and the programming time of the voltage pulse of the second ISSP pattern is Tpgm2, the entire block is programmed. The time is “Tblock = 60 × Tpgm2 + 4 × Tpgm1”. Optionally, the word lines can be divided into three or multiple sets. Thus, the voltage pulses applied to the selected word lines belonging to each set have different voltage sequences.

  FIG. 15 shows another embodiment for voltage pulses used for programming a nonvolatile memory device. Here, the word lines are divided into two sets. Referring to FIG. 15, the gradients of all voltage pulses in the second voltage pulse sequence (second ISSP pattern) are different from each other. However, the gradient of at least one of the voltage pulses of the first voltage pulse sequence shown in FIG. 15 (eg, a word line not located near SSL) is equal to the second voltage pulse sequence (one near SSL). Or any voltage pulse slope of multiple word lines).

  FIG. 16 is another embodiment of voltage pulses used to program memory cells in a non-volatile (flash) memory device. Here, the word lines are divided into two sets. Referring to FIG. 16, the slopes of at least two voltage pulses in the first ISSP pattern are the same. In fact, all voltage pulses in the first ISSP pattern can be identical to each other. However, the slope of at least one voltage pulse of the first voltage pulse sequence shown in FIG. 16 is at least one of the second voltage pulse sequence (one or multiple word lines located near SSL) (or Is greater than the slope of (all). In other words, desirably, the slope of all voltage pulses in the first voltage pulse sequence will be greater than the slope of any voltage pulse in the second voltage pulse sequence shown in FIG.

  FIG. 17 illustrates a diagram of a high level function according to one embodiment of the non-volatile memory device 1700. Although not shown, among other components, the memory device 1700 includes a high voltage generator 1710, a word line voltage generator 1750, and a NAND flash memory cell array 1790. The word line voltage generator 1750 includes a pulse voltage generator 1760, a word line slope controller 1770 and a multiplexer 1780.

  The high voltage generator 1710 generates a high voltage (for example, 18V) for programming the memory cell, and provides the high voltage to the pulse voltage generator 1760. The pulse voltage generator 1760 generates a first voltage pulse sequence of voltage pulses applied to the selected word line for programming the memory cells of the NAND flash memory cell array 1790. Preferably, the pulse voltage generator 1760 outputs the first voltage pulse sequence according to the ISSP technique. A word line slope controller 1770 receives the first voltage pulse sequence and controls the slope of at least one of the voltage pulses of the first voltage pulse sequence, thereby generating a second voltage pulse sequence. Preferably, the first and second voltage pulse sequences will be any one of the sequence pairs shown in FIGS. The multiplexer 1780 receives the first and second voltage pulse sequences and outputs one of the first and second voltage pulse sequences depending on the selected word line indicated by the row address. In particular, multiplexer 1780 outputs a first voltage pulse sequence when a row address indicates a selected word line (first word line set) that is not located near SSL. On the other hand, when the row address indicates a selected word line (second word line set) near SSL, the multiplexer 1780 outputs a second voltage pulse sequence from the word line slope controller 1770.

  As described above, FIG. 17 is a high-level function diagram, and the arrangement of components shown in FIG. 17 is an example. For example, in FIG. 17, as an example, multiplexer 1780 is at the output of word line slope controller 1770, but could also be at its input. The multiplexer function changes the slope provided by the wordline slope controller 1770 to generate the first and second voltage pulse sequences.

  FIG. 18 shows a block diagram of relevant portions according to one embodiment of a non-volatile (eg, flash) memory device 1800. The memory device 1800 includes a clock generator 1815, a program voltage controller 1850, a word line decoder 1885, and a NAND flash memory cell array 1890. Program voltage controller 1850 includes a pulse voltage generator (FIG. 17) 1760 and a word line slope controller (FIG. 17) 1770.

  FIG. 19 shows a block diagram of the first embodiment of the program voltage controller 1900. The program voltage controller 1900 includes a voltage ladder 1920, a step voltage controller 1940, and a time controller 1960. The voltage ladder 1920 receives a sequence of voltage pulses Vpgm1 and generates a plurality of voltages V0 to Vn-1. The time controller 1960 outputs a plurality of clock signals having generally the same period. The step voltage controller 1940 receives a clock signal from the time controller 1960 and is responsive to a row address corresponding to the selected word line to control a slope of at least one of the voltage pulses. A voltage is selected from the voltage ladder 1920 for each time period. That is, the step voltage controller 1940 sets the voltage magnitude during each clock period according to the row address of the selected word line, and controls the slope of the voltage pulse according to the selected word line position. To do.

  In particular, referring to FIG. 20, when the row address points to a selected word line that is not located near SSL (eg, WL0 to WL29), the voltage controller 1940 detects the voltage shown on the right side of FIG. To generate the pulse Vpgm2, a larger voltage step is output during every clock period. Optionally, voltage controller 1940 sets the maximum possible step to V8 during the first clock period and maintains that voltage at V8 during voltage pulse Vpgm1. Accordingly, in this case, the program voltage controller 1900 outputs a first voltage pulse sequence having a relatively large gradient. On the other hand, when the row address indicates a selected word line near SSL (eg, WL30, WL31), the voltage controller 1940 generates each of the voltage pulses Vpgm2 shown on the left side of FIG. Output a small voltage step during the clock period. Accordingly, in this case, the program voltage controller 1900 outputs a second voltage pulse sequence having a relatively reduced slope.

  FIG. 21 shows a block diagram of the second embodiment of the program voltage controller 2100. The program voltage controller 2100 includes a voltage ladder 2120, a step voltage controller 2140, and a time controller 2160. The voltage ladder 2120 receives a sequence of voltage pulses Vpgm1 and generates a plurality of voltages V0 to Vn-1. The time controller 2160 outputs a clock signal having a plurality of time periods. The step voltage controller 2140 receives the clock signal from the time controller 2160 and increases the voltage provided from the voltage ladder 2120 according to a predetermined amount in each of a plurality of time periods. Preferably, the time controller 2160 sets a time period to control at least one slope of the voltage pulse in response to the corresponding row address of the selected word line. That is, the time controller 2160 sets the time period of each clock period according to the row address of the selected word line. Thereby, the time controller 2160 controls the slope of the voltage pulse according to the position of the selected word line.

  In particular, referring to FIG. 22, when the row address indicates a selected word line that is not located near SSL (eg, WL0 to WL29), the time controller 2160 detects the voltage shown on the right side of FIG. A very short time period is set to generate the pulse Vpgm2. Accordingly, in this case, the word line voltage generator 2100 outputs a first voltage pulse sequence having a relatively large gradient. On the other hand, when the row address indicates a selected word line (eg, WL30, WL31) located near SSL, the time controller 2160 outputs an output pulse having the voltage pulse Vpgm2 shown on the left side of FIG. In order to generate, each clock cycle is set longer. Accordingly, in this case, the word line voltage generator 2100 outputs a second voltage pulse sequence having a relatively reduced slope.

  FIG. 23 shows a block diagram of a third embodiment of program voltage controller 2300. The program voltage controller 2300 includes a pulse voltage generator (not shown), a ramper (ramp circuit) 2320, a multiplexer 2340, and a detector 2360. The pulse voltage generator generates a first voltage pulse sequence of voltage pulses Vpgm1 to be applied to selected word lines for programming memory cells of a non-volatile memory array (not shown). Preferably, the pulse voltage generator outputs the first voltage pulse sequence according to the ISSP technology. The ramp 2320 receives the first voltage pulse sequence of the voltage pulse Vpgm1 and controls the gradient of at least one of the voltage pulses Vpgm1 of the first voltage pulse sequence, thereby generating the second voltage pulse sequence of the voltage pulse Vpgm2. To do. Desirably, the first and second voltage pulse sequences of the pulse voltages Vpgm1 and Vpgm2 will be one of the sequence pairs shown in FIGS. Multiplexer 2340 receives first and second voltage pulse sequences of pulse voltages Vpgm1, Vpgm2 and first and second voltage pulses of voltage pulses Vpgm1, Vpgm2 depending on the selected word line sensed by detector 2360. Output one of the sequences. In particular, when detector 2360 senses a word line (first word line set) not located near SSL, detector 2360 causes multiplexer 2340 to output a first voltage pulse sequence of voltage pulse Vpgm1. Control. On the other hand, when the detector 2360 senses a selected word line (second word line set) not located near SSL, the detector 2360 outputs a second voltage pulse sequence of the voltage pulse Vpgm2. The multiplexer 2340 is controlled.

  The embodiment of FIG. 23 shows a multiplexer 2340 at the output of the ramper 2320. Multiplexer 2340 can also be present at the input end of ramper 2320. Further, multiplexer 2340 may be integrated into the multiplexer of word line decoder 1885 of FIG.

  FIG. 24 is a flowchart relating to a programming method for a non-volatile (eg, flash) memory device. In a first stage 2410, a first voltage pulse sequence is generated. The voltage pulse Vpgm1 of the first voltage pulse sequence has a first gradient. Preferably, the voltage pulse of the first voltage pulse sequence has a voltage pulse that gradually increases according to the ISSP technique.

  In step 2420, it is determined whether the selected word line is located near SSL. If step 2420 determines that the selected word line is located near SSL, step 2430 generates a second voltage pulse sequence. The voltage pulse Vpgm2 of the second voltage pulse sequence has a second gradient. At least one of the voltage pulses Vpgm1 of the first voltage pulse sequence is greater than the gradient of at least one of the voltage pulses Vpgm2 of the second voltage pulse sequence. Preferably, the voltage pulse Vpgm2 of the second voltage pulse sequence has a voltage pulse that gradually increases in accordance with the ISSP technique.

  In step 2440, a second voltage pulse sequence is applied to the selected word line.

  On the other hand, if at step 2420, the selected word line is not located near SSL, then at step 2450, a first voltage pulse sequence is applied to the selected word line.

  Finally, at step 2470, the program operation ends.

  FIG. 25 illustrates a memory system 2500 that includes a memory controller 2520 and a non-volatile (eg, flash) memory device 1800. Here, the memory device 1800 selects one of the first voltage pulse sequence and the second voltage pulse sequence for the selected word line to program the nonvolatile memory cells connected to the selected word line. To provide. Here, the gradient of at least one of the voltage pulses of the first voltage pulse sequence is greater than the gradient of at least one of the voltage pulses of the second voltage pulse sequence.

  The memory controller 2520 provides an address for writing data to one or a plurality of nonvolatile memory cells to which the selected word line is connected. The memory device 1800 receives an address from the memory controller 2520. Word line decoder 1885 decodes the address to determine the corresponding word line to be selected to program the memory cells connected to it. Preferably, as described above, when the memory device 1800 senses that the selected word line is not located near SSL (first word line set), the program voltage controller 1850 may apply the first word line to the selected word line. 1 voltage pulse sequence is output. On the other hand, when the detector 2360 senses that the selected word line is located near SSL (second word line set), the program voltage controller 1850 outputs a first voltage pulse sequence to the selected word line. . Here, the gradient of at least one of the voltage pulses of the first voltage pulse sequence is greater than the gradient of at least one of the voltage pulses of the second voltage pulse sequence. Desirably, the first and second voltage pulse sequences may be the sequences shown in FIGS.

  FIG. 26 summarizes the program conditions for word lines in the memory device. Referring to FIG. 26, the program time Tpgm1 for the first voltage pulse sequence when the selected word line is far from the SSL is the first voltage pulse when the selected word line is near SSL. Less than the program time Tpgm2 for the voltage pulse sequence. However, by reducing the slope of the voltage pulse in the first voltage pulse sequence (increasing the rising time), large spikes caused by the capacitance coupled to the control gate of the SST will cause the program protection function to fail. Can be suppressed. . As a result, the program prevention function can be ensured to work properly for all word lines. On the other hand, the overall block program time is slightly increased compared to a device using program time Tpgm1 for all word lines.

  On the other hand, while the detailed description of the present invention has been described with respect to specific embodiments, various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be determined only by the above-described embodiments, but must be determined not only by the claims but also by the equivalents of the claims of the present invention.

FIG. 3 is a diagram showing an erased flash memory cell. FIG. 3 shows a programmed flash memory cell. FIG. 10 is a diagram showing an erase operation for a flash memory cell. FIG. 10 is a diagram showing a program operation for a flash memory cell. FIG. 3 is a diagram showing threshold voltage distributions for different memory cells in a flash memory device. 1 is a diagram showing a basic NAND flash memory cell string. FIG. FIG. 5 is a diagram illustrating a method of preventing a memory cell connected to a selected word line from being programmed by charging a bit line associated with the memory cell to Vcc. FIG. 10 is a diagram illustrating coupling between a gate and a channel during a NAND flash memory cell program operation. FIG. 6 is a diagram showing a pulse program sequence for programming a NAND flash cell. FIG. 6 is a diagram showing an ISSP for programming a NAND flash cell. FIG. 5 is a diagram showing how the threshold voltage distribution of a flash memory device changes as a result of each voltage pulse of an ISSP sequence. FIG. 5 illustrates a flash memory cell string including parasitic coupling capacitance that exists between word lines connected to various memory cells. FIG. 6 is a diagram illustrating the effect of coupling capacitance between a string selection line and a nearby selected word line when a program voltage pulse is applied to the selected word line. FIG. 5 is a diagram illustrating how to solve the problem that the slope of the word line voltage pulse interferes with the normal operation of the program prevention function. FIG. 6 is a diagram illustrating voltages used to program memory cell strings of a non-volatile memory device and memory cells of corresponding strings. FIG. 4 is a diagram illustrating an embodiment for first and second voltage pulse sequences applied to different word lines of a memory device. FIG. 6 is a diagram illustrating another embodiment of first and second voltage pulse sequences applied to different word lines of a memory device. FIG. 6 is a diagram illustrating another embodiment of first and second voltage pulse sequences applied to different word lines of a memory device. It is a figure which shows the high level functional block diagram of a non-volatile memory device. It is a figure which shows the detailed block diagram of a non-volatile memory device. It is a figure which shows the block diagram by 1st Embodiment of a word line voltage generator. FIG. 20 shows voltage pulses generated by the word line voltage generator shown in FIG. 19. It is a figure which shows the block diagram by 2nd Embodiment of a word line voltage generator. FIG. 22 shows voltage pulses generated by the word line voltage generator shown in FIG. 21. It is a figure which shows the block diagram by 3rd Embodiment of a word line voltage generator. 5 is a flowchart for a method of programming a non-volatile memory device. It is a figure which shows the block diagram of a memory system. FIG. 6 is a diagram illustrating a program operation in a memory device using a first voltage pulse sequence of a first word line set and a second voltage pulse sequence of a second word line set.

Explanation of symbols

WL0 to WL31 Word line BL0 to BLn-1 Bit line 100 Flash memory cell 105 Source 110 Drain 115 Semiconductor memory substrate 120 Control gate 130 Floating gate 140 Dielectric oxide film 150 Gate oxide film 300 NAND flash memory cell string 400 NAND flash memory string 1000 Flash memory cell string 1010 Capacitance 1050 Memory cell 1100 String 1300 Memory cell string 1700 Non-volatile memory device 1710 High voltage generator 1750 Word line voltage generator 1760 Pulse voltage generator 1770 Word line gradient controller 1780 Multiplexer 1790 NAND flash memory cell array 1800 Non-volatile memory Device 1815 Clock generator 1850 Program voltage controller 185 Word line decoder 1890 NAND flash memory cell array 1900 Program voltage controller 1920 Voltage ladder 1940 Step voltage controller 1960 Time controller 2100 Program voltage controller 2120 Voltage ladder 2140 Step voltage controller 2160 Time controller 2300 Program voltage controller 2320 Lamper 2340 Multiplexer 2360 Detector 2500 Memory system 2520 Memory controller

Claims (31)

In a non-volatile memory device,
A non-volatile memory cell array including a plurality of non-volatile memory cells connected to a plurality of word lines;
Of the first and second voltage pulse sequences on the selected word line to generate a first and second voltage pulse sequence and program the non-volatile memory cell connected to the selected word line. A word line voltage generator that selectively provides one,
The nonvolatile memory cell array includes a plurality of bit lines and a plurality of selection lines,
The plurality of selection lines are respectively connected to the bit lines that select strings of the nonvolatile memory cells;
The gradient of the at least one voltage pulse of the first voltage pulse sequence rather greater than the gradient of the at least one voltage pulse of the second sequence of voltage pulses,
The word line voltage generator is
A voltage ladder providing multiple voltages;
A step voltage controller for selecting a voltage from the voltage ladder in each of a plurality of time periods;
Providing the first voltage pulse sequence when the selected word line belongs to a first set of word lines comprising the plurality of word lines, wherein the selected word line comprises a second word comprising the plurality of word lines; Providing the second voltage pulse sequence when belonging to a line set;
The second word line set is closer to one of the selected lines than the first word line set;
The step voltage controller selects a voltage from the voltage ladder in each of the plurality of time periods that controls a slope of at least one of the voltage pulses in response to a row address corresponding to the selected word line. A non-volatile memory device characterized by:   The nonvolatile memory device of claim 1, wherein at least one of the first and second voltage pulse sequences is configured to increase a voltage pulse. All voltage pulses in the first voltage pulse sequence have the first slope,
The nonvolatile memory device of claim 1, wherein all voltage pulses in the second voltage pulse sequence have a second gradient smaller than the first gradient. The nonvolatile memory device of claim 1, wherein at least two voltage pulses in the first voltage pulse sequence have the same slope.   The nonvolatile memory device of claim 1, wherein at least two voltage pulses of the second voltage pulse sequence have different slopes.   The nonvolatile memory device of claim 1, wherein all voltage pulses in the second voltage pulse sequence have a slope smaller than a slope of all voltage pulses in the first voltage pulse sequence. The word line voltage generator is
A step voltage generator for generating the first voltage pulse sequence;
The nonvolatile memory of claim 1, further comprising a word line gradient controller that controls a gradient of at least one voltage pulse of the first voltage pulse sequence to generate the second voltage pulse sequence. Memory device. The word line voltage generator is
When the word line voltage generator selectively provides the second voltage pulse sequence, the word line voltage generator provides the first voltage pulse sequence to the word line slope controller, and the word line voltage generator selectively The nonvolatile memory device of claim 7 , further comprising a multiplexer that bypasses the word line slope controller when providing a voltage pulse sequence. Claim wherein the word line voltage generator which receives the first and second sequence of voltage pulses, characterized in that it comprises a first and a multiplexer for outputting one selectively of the second sequence of voltage pulses The nonvolatile memory device according to claim 7 . The word line voltage generator generates a third voltage pulse sequence to program the non-volatile memory cells connected to the selected word line to the first and second selected word lines. Providing one of the second and third voltage pulse sequences;
The nonvolatile memory device of claim 1, wherein a slope of at least one voltage pulse in the third voltage pulse sequence is greater than a slope of at least one of the first voltage pulse sequences. A plurality of nonvolatile memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cells including a plurality of strings, a plurality of selection lines for selecting the strings, and at least one or a plurality of words A nonvolatile memory cell array including a word line including a first word line set composed of lines and a second word line set composed of at least one or a plurality of word lines;
First and second voltage pulse sequences are generated to program a non-volatile memory cell connected to a selected word line, and when the selected word line is the first word line set, the first Providing a voltage pulse sequence, and when the selected word line is the second set of word lines, a word line voltage generator that provides the second voltage pulse sequence;
The second word line set is closer to one of the selected lines than the first word line set, and a gradient of at least one voltage pulse of the first voltage pulse sequence is equal to that of the second voltage pulse sequence. the size of at least one of the gradient of out rather,
The word line voltage generator is
A voltage ladder providing multiple voltages;
A step voltage controller for selecting a voltage from the voltage ladder in each of a plurality of time periods;
The step voltage controller selects a voltage from the voltage ladder in each of the plurality of time periods that controls a slope of at least one of the voltage pulses in response to a row address corresponding to the selected word line. A non-volatile memory device characterized by: The non-volatile memory device of claim 11 , wherein at least one of the first and second voltage pulse sequences is configured to increase a voltage pulse. The nonvolatile memory device of claim 11 , wherein at least two voltage pulses in the first voltage pulse sequence have the same slope. The nonvolatile memory device of claim 11 , wherein at least two voltage pulses in the second voltage pulse sequence have different slopes. The word line voltage generator is
A step voltage generator for generating the first voltage pulse sequence;
The nonvolatile memory of claim 11 , further comprising a word line gradient controller that controls a gradient of at least one voltage pulse of the first voltage pulse sequence to generate the second voltage pulse sequence. Memory device. The word line voltage generator generates a third voltage pulse sequence and applies the first and second voltages to the selected word line to program the nonvolatile memory cell to which the selected word line is connected. And one of the third voltage pulse sequences,
The nonvolatile memory device of claim 11 , wherein a slope of at least one voltage pulse in the third voltage pulse sequence is greater than a slope of at least one of the first voltage pulse sequences. In a method for programming a nonvolatile memory device including a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines,
Applying a first voltage pulse sequence to the first word line when a word line voltage generator programs the non-volatile memory cell connected to the first word line;
Applying a second voltage pulse sequence to the second word line when the word line voltage generator programs the non-volatile memory cell connected to the second word line;
The nonvolatile memory cell array includes a plurality of selection lines connected to each of the bit lines for selecting a plurality of bit lines and a string of the nonvolatile memory cells,
The second word line is closer to one of the selection lines than the first word line, and
Here the slope of at least one voltage pulse of said first sequence of voltage pulses is much larger than the slope of the at least one voltage pulse of the second sequence of voltage pulses,
The word line voltage generator is
A voltage ladder providing multiple voltages;
A step voltage controller for selecting a voltage from the voltage ladder in each of a plurality of time periods;
The step voltage controller selects a voltage from the voltage ladder in each of the plurality of time periods that controls a slope of at least one of the voltage pulses in response to a row address corresponding to the selected word line. A method for programming a nonvolatile memory device. The method of claim 17 , wherein at least one of the first and second voltage pulse sequences increases a voltage pulse. All voltage pulses in the first voltage pulse sequence have a first slope,
The method of claim 17 , wherein all the voltage pulses in the second voltage pulse sequence have a second gradient smaller than the first gradient. The method of claim 17 , wherein at least two voltage pulses in the first voltage pulse sequence have the same slope. The method of claim 17 , wherein at least two voltage pulses in the second voltage pulse sequence have different slopes. The method of claim 17 , wherein when programming a nonvolatile memory cell connected to a third word line, the first voltage pulse sequence is applied to the third word line. . In order to generate a third voltage pulse sequence and program the non-volatile memory cell to which the selected word line is connected, the first, second and third voltage pulse sequences are applied to the selected word line. One of them,
The method of claim 17 , wherein at least one voltage pulse gradient of the third voltage pulse sequence is greater than at least one gradient of the first voltage pulse sequence. In the system,
A non-volatile memory device;
A memory controller,
The nonvolatile memory device includes:
A non-volatile memory cell array including a plurality of non-volatile memory cells connected to a plurality of word lines;
The first and second voltage pulse sequences are applied to the selected word line to generate the first and second voltage pulse sequences and program the nonvolatile memory cells connected to the selected word line. Selectively provide one of
A word line voltage generator, wherein a slope of at least one voltage pulse of the first voltage pulse sequence is greater than a slope of at least one voltage pulse of the second voltage pulse sequence;
The memory controller provides an address corresponding to the selected word line to write data to the one or multiple non-volatile memory cells connected to the selected word line ;
The nonvolatile memory cell array includes a plurality of bit lines and a plurality of selection lines,
The plurality of selection lines are respectively connected to the bit lines that select strings of the nonvolatile memory cells;
The word line voltage generator is
A voltage ladder providing multiple voltages;
A step voltage controller for selecting a voltage from the voltage ladder in each of a plurality of time periods;
Providing the first voltage pulse sequence when the selected word line belongs to a first set of word lines comprising the plurality of word lines, wherein the selected word line comprises a second word comprising the plurality of word lines; Providing the second voltage pulse sequence when belonging to a line set;
The second word line set is closer to one of the selected lines than the first word line set;
The step voltage controller selects a voltage from the voltage ladder in each of the plurality of time periods that controls a slope of at least one of the voltage pulses in response to a row address corresponding to the selected word line. A system characterized by: 25. The non-volatile memory device of claim 24 , wherein at least one of the first and second voltage pulse sequences is configured to increase a voltage pulse. All voltage pulses in the first voltage pulse sequence have a first slope,
25. The system of claim 24 , wherein a voltage pulse in the second voltage pulse sequence has a second slope that is less than the first slope. 25. The system of claim 24 , wherein at least two voltage pulses of the first voltage pulse sequence have the same slope. The system of claim 24 , wherein at least two voltage pulses of the second voltage pulse sequence have different slopes. The word line voltage generator is
A step voltage generator for generating the first voltage pulse sequence;
25. The system of claim 24 , further comprising a word line slope controller that controls a slope of at least one voltage pulse of the first voltage pulse sequence to generate the second voltage pulse sequence. . The word line voltage generator is
When the word line voltage generator selectively provides the second voltage pulse sequence, the word line voltage generator provides the first voltage pulse sequence to the word line slope controller, and the word line voltage generator selectively 30. The system of claim 29 , including a multiplexer that bypasses the word line slope controller when providing a voltage pulse sequence. Claim wherein the word line voltage generator which receives the first and second sequence of voltage pulses, characterized in that it comprises a first and a multiplexer for outputting one selectively of the second sequence of voltage pulses 30. The system according to 29 .

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