JP3884420B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM that performs writing / erasing on a memory cell by a tunnel current.

  As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their adjacent sources and drains are shared with each other and connected to a bit line as a unit. A memory cell usually has a FETMOS structure in which a floating gate (charge storage layer) and a control gate are stacked. The memory cell array is integrated in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the selection gate, and the source side is also connected to the common source line via the selection gate. The control gates of the memory cells are continuously arranged in the row direction to become word lines.

  The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate voltage Vppm (= about 10V) is applied to the control gate and the selection gate of the memory cell on the bit line side. The bit line is supplied with 0V or an intermediate voltage Vm (= about 8V) according to the data.

  When 0V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electrons are injected into the charge stack. As a result, the threshold value of the selected memory cell is shifted in the positive direction. This state is, for example, “0”. When Vm is applied to the bit line, electron injection does not occur effectively, so the threshold value remains unchanged and remains negative. This state is “1” in the erased state. Data writing is performed simultaneously on the memory cells sharing the control gate.

  Data erasure is performed simultaneously on all the memory cells in the NAND cell. That is, all the control gates are set to 0V, and the p-type well is set to 20V. At this time, the selection gate, the bit line, and the source line are also set to 20V. As a result, electrons in the charge storage layer are emitted to the p-type well in all the memory cells, and the threshold value is shifted in the negative direction.

  In the data read, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply potential Vcc (for example, 5 V) to detect whether a current flows in the selected memory cell. Is done.

  Due to restrictions on the read operation, the threshold value after writing “0” must be controlled between 0 V and Vcc. For this reason, write verification is performed, only the memory cells insufficiently written “0” are detected, and rewrite data is set so that only the memory cells insufficiently written “0” are rewritten (bit-by-bit verification). ). A memory cell in which “0” is insufficiently written is detected by reading the selected control gate at 0.5 V (verify voltage) (verify read). That is, if the threshold value of the memory cell is not 0.5 V or more with a margin with respect to 0 V, a current flows in the selected memory cell, and it is detected that “0” writing is insufficient.

  By writing data while repeating the write operation and write verify, the write time is optimized for each memory cell, and the threshold value after writing “0” is controlled between 0 V and Vcc.

  In such a NAND cell type EEPROM, since the write voltage Vpp at the time of writing is constant, the threshold value of the memory cell changes rapidly at the initial stage of writing when the amount of electrons in the charge storage layer is relatively small, and electron injection is performed. In the latter period of writing when the amount of electrons in the charge storage layer is relatively large, the threshold change of the memory cell is slow. In addition, the electric field applied to the insulating film through which the tunnel current flows is strong in the early stage of writing, and the electric field is weak in the late stage of writing.

  For this reason, when the write voltage Vpp is increased in order to increase the write speed, the maximum threshold value after writing becomes high, the threshold distribution width after writing becomes wide, and the electric field applied to the insulating film through which the tunnel current flows. Becomes stronger and less reliable. Conversely, if Vpp is lowered in order to narrow the threshold distribution width after writing, the writing speed becomes slower. In other words, there is a problem that the write voltage margin is narrow.

  Hereinafter, this problem will be described in detail. Here, the configuration of FIG. 1 to be described later is considered as the memory cell. In FIG. 1, 1 is a control gate, 2 is an inter-gate insulating film, 3 is a floating gate, 4 is a tunnel oxide film, 5 is an n-type diffusion layer, and 6 is a p-type well.

  Conventionally, for example, when electrons are injected into a floating gate, a control gate voltage Vcg is applied as shown in FIG. 21A, and the p-type well and the n-type diffusion layer are set to 0V. In this case, the control gate voltage Vcg is set to a constant voltage Vpp only for a fixed time T. Initially, since the amount of electrons in the floating gate is small, the floating gate potential Vfg is relatively high as shown in FIG. 21B, and the tunnel current Itunnel is relatively large as shown in FIG. As electron injection into the floating gate proceeds, the amount of electrons in the floating gate increases, so the floating gate potential Vfg becomes relatively low and the tunnel current Itunnel becomes relatively small. Therefore, the amount of change in the threshold value Vth of the memory cell is initially large and gradually decreases as shown in FIG.

  In general, when performing electron injection into a floating gate while performing a threshold value checking operation of a memory cell called “verify”, the result is as shown in FIG. The control gate voltage Vcg is divided into several pulses, and verification is performed after the electron injection operation to each floating gate. In FIG. 22, the control gate voltage Vcg during the verify operation is set to 0 V for convenience, but some voltage is often applied to the control gate by the verify method. When it is detected by verify that the threshold value of the memory cell has reached a desired value, the electron injection operation is terminated. When electrons are injected into a plurality of memory cells at the same time, the electron injection operation is terminated for each memory cell when it is detected by verify that the threshold value of the memory cell has reached a desired value.

  FIG. 23 is a diagram showing a change in threshold value of each memory cell when electrons are injected into a plurality of memory cells by the same method as FIG. Usually, the shape of the memory cell varies little by little, and as a result, the time course of electron injection varies. In the memory cell that is most likely to inject electrons, the upper limit Vth-max of the range in which the threshold value of the memory cell should be reached is reached immediately, and the voltage Vpp is set so that the threshold value does not exceed Vth-max in the first electron injection operation. The upper limit voltage Vpp-max is determined. In the memory cell that is most difficult to inject electrons, it is difficult to reach the lower limit Vth-min of the range in which the threshold value of the memory cell should fall, and the voltage Vpp is set so that the threshold value exceeds Vth-min within a predetermined number of electron injection operations. The lower limit voltage Vpp-min is determined.

  Vpp-max-Vpp-min is called a Vpp margin and must be a positive value. If Vth-max is lowered and the threshold distribution width is narrowed, Vpp must be lowered and the Vpp margin approaches 0V. When the electron injection / emission is repeated, the tunnel oxide film deteriorates and the electron injection / emission characteristics change. Therefore, if the Vpp margin is not sufficient, there is a problem in reliability.

  As described above, the conventional NAND cell type EEPROM has a so-called trade-off relationship in which the threshold distribution width after writing increases when the writing voltage Vpp is increased, and the writing speed decreases when the writing voltage Vpp is decreased. It was. And since the write voltage Vpp margin is narrow, there is a problem that the device reliability is lowered.

  The present invention has been made in consideration of the above-described circumstances. The object of the present invention is to ensure a sufficient write voltage Vpp margin and to reduce the threshold distribution width of the memory cell. An object of the present invention is to provide an EEPROM that can perform electron injection at high speed.

In order to solve the above problems , the present invention adopts the following configuration.

That is, the present invention controls a plurality of non-volatile semiconductor memory cells configured to include a charge storage layer between a semiconductor layer and a control gate and capable of electrically multi-value data identification recording, and a threshold of the memory cell. A first step of applying a voltage pulse between the control gate and the semiconductor layer to vary the threshold value of the memory cell; and after applying the voltage pulse. Threshold control for repeating the second step of detecting the threshold value of the memory cell while increasing the voltage pulse by a certain amount of voltage fluctuation until the threshold value of the memory cell reaches a desired threshold value. a nonvolatile semiconductor memory device and means, the voltage initial value of the pulse having a voltage corresponding to the write state to reach the corresponding memory cell, the said first step second Performed simultaneously step to the plurality of memory cells, each memory cell is characterized by stopping the independent application of the voltage pulse for each of the memory cell upon reaching the desired threshold.

  More specifically, a memory cell array in which electrically rewritable memory cells formed by stacking a charge storage layer and a control gate on a semiconductor layer are arranged in a matrix, and data of the memory cell is set to data “0”. In order to change the threshold value of the erasing means for erasing the memory cell array and an arbitrary number of memory cells in the memory cell array, write data (“1”, “2”, .., “N”), a write pulse applying means for applying threshold fluctuation voltage pulses (Vpp1, Vpp2,..., Vppn), and a state after application of threshold fluctuation pulses to an arbitrary number of memory cells. Threshold verifying means to be detected and a desired threshold value (Vth1, Vth2,...,...) Corresponding to write data (“1”, “2”,..., “N”) among an arbitrary number of memory cells. Vthn) has not been reached Rewriting pulse applying means for applying a threshold fluctuation pulse corresponding to write data to a memory cell that is insufficiently written and simultaneously changing the threshold value according to write data is provided. After the threshold value changing operation and the threshold value verifying operation by the threshold value verifying means, the rethreshold value changing operation and the threshold value verifying operation by the rewrite pulse applying means are performed. In a nonvolatile semiconductor memory device that repeats until a desired value is reached, the threshold fluctuation voltage pulse is Vpp1 = Vpp2−ΔVppd2 = Vpp3−ΔVppd2 = ... = Vppn−ΔVppdn, and the desired threshold is Vthi. −Vthi−1 = ΔVppdi (i = 2, 3,..., N).

  In the present invention, the write voltage Vpp is gradually increased as the write time elapses. For memory cells that are easy to write, writing is completed at a relatively low write voltage Vpp, and for memory cells that are difficult to write, a comparison is made. A wide write voltage Vpp margin can be obtained by performing writing at a relatively high write voltage Vpp.

  Further, ΔVpp and Δt are set so that the threshold distribution width after writing “0” becomes ΔVpp, which means that the threshold shift amount in one cycle is substantially constant ΔVpp. The voltage applied to the insulating film through which the tunnel current flows is controlled to be average in the same way every cycle, the maximum value can be reduced, and the reliability is improved.

  According to the present invention, the write voltage Vpp is gradually increased while repeating the cycle of the write operation and the bit-by-bit verify operation, thereby securing a sufficient Vpp margin, narrowing the threshold distribution width of the memory cell, and increasing the speed. An EEPROM capable of performing electron injection can be realized. Electron emission can also be easily performed by inverting the polarity of the control gate voltage of the memory cell. Further, the same can be implemented when the memory cell is a p-channel MOS transistor.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A shows the structure of a nonvolatile memory cell used in the example of the present invention. A floating gate (charge storage layer) 3 and a control gate 1 are stacked on a p-type well 6 on an n-type silicon substrate 7. The p-type well 6 and the floating gate 3 are insulated by a tunnel oxide film 4, and the floating gate 3 and the control gate 1 are insulated by an inter-gate insulating film 2. The n-type diffusion layer 5 forms the source / drain of the memory cell transistor.

  The capacitance between the floating gate 3 and the control gate 1 and the capacitance between the floating gate 3 and the p-type well 6 are Ccg and Cox, respectively, as shown in FIG. The capacitance Cox includes the capacitance between the floating gate 3 and the n-type diffusion layer 5. The memory cell stores data at the threshold value, and the threshold value is determined by the amount of charge stored in the floating gate 3. The amount of charge in the floating gate 3 is changed by a tunnel current passing through the tunnel oxide film 4.

  That is, when the control gate 1 is set to a sufficiently high potential with respect to the p-type well 6 and the n-type diffusion layer 5, electrons are injected into the floating gate 3 through the tunnel oxide film 4, and the threshold value is increased. Conversely, when the p-type well 6 and the n-type diffusion layer 5 are set to a high potential with respect to the control gate 1, electrons are emitted from the floating gate 3 through the tunnel oxide film 4, and the threshold value is lowered.

  FIG. 2 shows an electron injection method according to the first embodiment of the present invention. (A) is the control gate voltage Vcg, (b) is the floating gate potential Vfg, (c) is the tunnel current Itunnel, and (d) is the threshold Vth of the memory cell.

  A high voltage Vpp pulse is applied to the control gate, and verification is performed after the Vpp pulse is applied. The first Vpp pulse voltage is Vcg0 and is gradually increased by ΔVpp. The pulse width is a certain time Δt. Δt and ΔVpp are set such that the maximum change amount ΔVth of the threshold value of the memory cell in one electron injection operation becomes equal to ΔVpp. Actually, when Vpp is sufficiently high and the tunnel current starts to flow sufficiently, if the threshold voltage change ΔVth of the memory cell in one electron injection operation is made equal to ΔVpp, one electron injection is performed. The electrons injected by the operation cancel the increase in voltage applied to the tunnel oxide film due to the increase ΔVpp of Vpp in the next electron injection operation, and thereafter, the threshold change amount ΔVth becomes a constant value ΔVpp every time. .

  If the initial pulse voltage Vcg0 is made sufficiently small, the threshold value of the memory cell that is most likely to inject electrons can be reliably controlled to be lower than the upper threshold value Vth-max, and a wide Vpp margin can be obtained. max−Vth−min = ΔVpp. In the memory cell that is most difficult to inject electrons, Vth-min is reached at a high speed by increasing Vpp. By verifying the threshold value for each memory cell and detecting that the threshold lower limit Vth-min has been reached, the electron injection operation is terminated for each memory cell.

  In this method, Vpp is further increased as the electron injection amount increases, so that the maximum value Vfg-max of the floating gate voltage Vfg is suppressed, and deterioration of the tunnel oxide film is also suppressed. Actually, the threshold change amount ΔVth becomes a constant value ΔVpp at the time of every electron injection operation, and the floating gate voltage Vfg is applied in the same way every time. As a result, Vfg-max is suppressed.

  FIG. 3 shows an electron injection method according to the second embodiment of the present invention. Basically, it is the same as that of the first embodiment, but the number of pulses at the initial stage of electron injection is combined into one and the verification operation is omitted to increase the speed. This method is effective for performing electron injection at high speed when the threshold value of the memory cell does not reach Vth-min with several pulses at the beginning of electron injection in the electron injection method shown in FIG. It is.

  FIG. 4 shows changes over time in threshold values of a memory cell in which electrons are most easily injected, a typical memory cell, and a memory cell in which electrons are most difficult to be injected in the second embodiment. In order to prevent the deterioration of the tunnel oxide film, it is preferable that Vfg-max is small. For this reason, as shown in FIG. 5, it is preferable to reduce the Vpp pulse width Δt and the Vpp increase rate ΔVpp. However, this increases the number of verify operations and takes time for electron injection. In addition, the threshold distribution width is narrower than necessary and wasteful.

  FIG. 6 shows an electron injection method according to the third embodiment of the present invention. This is a summary of several Vpp pulses seen in FIG. Initially, as described in FIGS. 3 and 4, more Vpp pulses are collected. By this method, the floating gate voltage Vfg becomes substantially constant, and similarly, Vth−max−Vth−min = ΔVpp can be obtained while suppressing the deterioration of the tunnel oxide film as compared with the method described with reference to FIGS.

  FIG. 7 shows an electron injection method according to the fourth embodiment of the present invention. This is a method shown in FIG. 6 in which Δt0 → 0 and ΔVpp0 → 0. Each Vpp pulse has a constant dVpp / dt and continuously increases by ΔVpp. In this method, the floating gate potential during electron injection can be made substantially constant, and the deterioration of the tunnel oxide film can be minimized.

  During the electron injection operation to the NMOS memory cell described above, if Vpp is sufficiently high, the channel portion is inverted, and the drain, source, and channel portions are at the same potential. Therefore, for example, the method shown in FIG. 7 is the same as the method shown in FIGS.

  In the method shown in FIG. 8, the control gate voltage Vcg is made constant and the drain voltage Vd is gradually lowered. As a result, the method shown in FIG. 7 and the method shown in FIG. 8 produce the same effect. If the initial value Vd0 of the voltage applied to the drain is high and exceeds the breakdown voltage by the method shown in FIG. 8, the method shown in FIG. 9 may be used. That is, the initial value Vd0 of the drain voltage is lowered, and at the same time, the initial value Vcg0 of the control gate is also lowered. When the drain voltage Vd has dropped to 0V, the control gate voltage Vcg is increased by Vd0, and Vd is decreased from Vd0. Even with this method, the same effect as the method shown in FIG. 7 can be obtained.

  7-9, dVpp / dt = constant, but even if this is difficult in practice, Vpp is changed at a rate of ΔVpp at the time of Δt while dVpp / dt ≧ 0, and If the threshold distribution width after electron injection is set to ΔVpp, an effect close to that obtained when dVpp / dt = constant is obtained.

  Of course, the voltage Vpp has an upper limit, which is determined by the breakdown voltage Vbreak of the device. Once Vpp reaches Vbreak, Vpp cannot be increased any further. Even in this case, the effect of the present invention can be obtained until Vpp reaches Vbreak. 2 to 9, the case of electron injection has been described, but the case of electron emission can be similarly implemented by inverting the polarity of the control gate with respect to the p-type well.

  FIG. 10 shows a memory cell array of a NAND cell type EEPROM according to the fifth embodiment of the present invention. Eight memory cells M1 to M8 are connected in series so that adjacent ones share the source and drain to form one NAND cell, and one terminal is a bit via the first selection transistor S1. Connected to line BL. The other terminal is connected to the common source line Vs via the second selection transistor S2. The selection gates SG1 and SG2 are the gate electrodes of the selection transistors S1 and S2, and the control gates CG1 to CG8 are the gate electrodes of the memory cells. A page is constituted by a memory cell group sharing the control gate CG, and a block is constituted by a NAND cell group sharing the selection gate SG. Each memory cell has a structure as shown in FIG. 1, and the memory cell array is formed in a common p-type well.

  The operations of erasing, writing, reading and writing verification of the NAND cell type EEPROM are as follows.

  Erasing is performed in units of blocks. The p-type well is set to the high voltage Vpp (˜20V), and the control gates CG1 to CG8 in the selected block are set to 0V. The control gate and all select gates in the unselected block are set to Vpp. Electrons in the floating gate are emitted to the p-type well, and the threshold value of the memory cell becomes negative.

  After erasure, data is written in batches in units of pages from the page at the position farthest from the bit line. During the write operation, Vpp (about 10 to 20 V) is applied to the control gate (for example, CG4) of the selected page, and the control gates CG1 to 3 and 5-8 of the non-selected page and the first selection gate SG1 are applied. An intermediate potential Vm (-10 V) is applied. The bit line BL is supplied with 0V for “0” write operation and Vm for “1” write operation. The second selection gate SG2 is 0V.

  In the “0” write operation, electrons are injected from the channel into the floating gate by the tunnel current due to the potential difference Vpp between the selected control gate CG4 and the channel, and the threshold value changes in the positive direction. In the “1” write operation, since the channel potential is set to Vm, the electric field applied to the tunnel oxide film is weak and effective injection of electrons into the floating gate does not occur. Therefore, the threshold value does not change.

  After the write operation, verification is performed to check the threshold value of the memory cell. A verification potential (˜0.5 V) is applied to the selected control gate (for example, CG4), and the non-selected control gates CG1 to 3, 5 to 8, and the first and second selection gates SG1 and SG2 are set to the power supply voltage Vcc. . If the bit line BL and the source line are electrically connected after the “0” write operation, the threshold value of the selected memory cell is lower than the verify potential, and “0” write is insufficient. The write operation is executed again. Otherwise, it is determined that “0” writing is sufficient when the threshold value is equal to or higher than the verify potential, and no further electron injection into the floating gate is necessary, and “1” writing operation is executed at the time of rewriting. After the “1” write operation, the “1” write operation is executed again during the rewrite operation regardless of the threshold value of the memory cell.

  By writing data while repeating the write operation and the verify operation, the write time is adjusted for each memory cell. When it is detected that all the memory cells for one page are sufficiently written, the data writing for one page is completed.

  In reading, the selected control gate (for example, CG4) is set to 0 V, and the non-selected control gates CG1 to 3, 5 to 8 and the first and second selection gates SG1 and SG2 are set to the power supply voltage Vcc. When the potential of the precharged bit line BL is lowered, the threshold value of the memory cell is 0 V or less and the data is “1”. If the potential of the bit line BL is held, the threshold value of the memory cell is 0 V or more and the data is “0”. From the read operation, the threshold value of the memory cell must be lower than the power supply voltage Vcc.

  Next, a method of applying the write voltage Vpp to the selected control gate CG at the time of writing in such a NAND cell type EEPROM will be described.

  FIG. 11 is a diagram showing a configuration of a circuit for driving the control gate. A transfer circuit 9 is provided for selectively transferring the outputs of the control gate driver 11 and the first and second selection gate drivers 10 and 12 to each control gate and selection gate. Ten transfer circuits 9 corresponding to the blocks of the cell array 8 are selected by block selection signals φwi and φwBi. The booster circuit 13 generates Vpp and Vm necessary for writing / erasing from the power supply voltage Vcc and supplies them to the control gate driver 11 and the first and second selection gate drivers 10 and 12.

  FIG. 12 shows more specifically the configuration of the transfer circuit 9, the control gate driver 11, and the booster circuit 13 of the control gate CG4 of FIG. The transfer circuit 9 includes a CMOS transfer circuit composed of an n-channel MOS transistor (n-ch. MOS Tr.) Qn1 and a p-channel MOS transistor (p-ch. MOS Tr.) Qp1, an n-ch. MOS Tr. The reset circuit is composed of Qn2. When the signals φwi and φwBi become “H” and “L”, respectively, the voltage at the node N1 is transferred to the control gate, and when it becomes “L” and “H”, the control gate is grounded. The booster circuit 13 includes a Vm booster circuit 14 and a Vpp booster circuit 15. The control gate driver 11 includes a first switch circuit 16, a second switch circuit 17, and a third switch circuit 18.

  The first switch circuit 16 controls whether or not the output Vm of the Vm booster circuit 14 is connected to the node N1. The second switch circuit 17 controls whether or not the output Vpp of the Vpp booster circuit 15 is connected to the node N1, but the voltage transferred to the node N1 is Vpp−ΔVpp. The third switch circuit 18 controls whether or not the output Vpp of the Vpp booster circuit 15 is connected to the node N1, but the amount of current when Vpp is transferred to the node N1 is the rate of increase in the potential of the node N1 dVpp / Controlled to control dt.

  FIG. 13 shows a specific configuration of the control gate driver 11. The first switch circuit 16 includes p-ch. MOS Tr. Qp2-4, n-ch. MOS Tr. Qn3,4, n-channel D-type MOS transistor (n-ch. D-type MOS Tr.) QD1, and It is composed of an inverter I1. A circuit composed of Qp2,3, Qn3,4 and an inverter I1 converts a signal φ1 having an amplitude between 0V and Vcc into a signal having an amplitude between 0V and Vpp. When φ1 is “L”, the gate of Qp4 is Vpp, the gate of QD1 is 0V, and Vm and N1 are separated. φ1 is “H”, the gate of Qp4 is 0V, the gate of QD1 is Vpp, and Vm and N1 are connected. QD1 is for preventing Vpp from being transferred to Qp4 when N1 becomes Vpp.

  The second switch circuit 17 comprises p-ch. MOS Tr. Qp5-8, n-ch. MOS Tr. Qn5, 6 and an inverter I2. When φ2 is “L”, the gate of Qp7 becomes Vpp, and Vpp and N1 are disconnected. When φ2 is “H”, the gate of Qp7 becomes 0V, Vpp and N1 are connected, and a voltage lower than Vpp by the threshold value of Qp8 (˜1V) is transferred to N1.

  The third switch circuit 18 includes p-ch. MOS Tr. Qp9 to 11, n-ch. MOS Tr. Qn7, 8, an inverter I3, and a current control circuit 19. When φ3 is “L”, the gate of Qp11 becomes Vpp, and Vpp and N1 are disconnected. When .phi.3 is "H", the gate of Qp11 becomes 0V, Vpp and N1 are connected, and Vpp is transferred to N1 while the current control circuit 19 controls dVpp / dt.

  p-ch. MOS Tr. Qp12, n-ch. MOS Tr. Qn9, n-ch. D-type MOS Tr. QD2 is a circuit for setting N1 to VGH or Vcc. When φ4 is “H”, N1 is VGH, and φ4 is “L” and N1 is Vcc. The voltage VGH is normally 0V and becomes a verify voltage VVRFY (up to 0.5V) during verification. QD2 is for preventing Vm and Vpp from being transferred to Qp12 when the signal φ5 becomes "L" and Vm or Vpp is applied to the node N1.

  FIG. 14 is a diagram showing a specific configuration of current control circuit 19 in FIG. 14A includes p-ch. MOS Tr. Qp13 to 15 and n-ch. D-type MOS Tr. QD3, 4, and the signal φ3B is an inverted signal of the signal φ3 in FIG. When the signal .phi.3 is "H" and .phi.3B is "L" and the node N2 becomes Vpp, the gate of Qp15 becomes Vpp-2Vtp (Vtp is the threshold value of p-ch. MOS Tr.). Is controlled by Qp15.

  FIG. 14B includes p-ch. MOS Tr. Qp16, 17, n-ch. MOS Tr. Qn10, a capacitor C1, and a resistor R1. When the signal .phi.3 is "H" and the node N2 is Vpp, the gate of Qp16 is controlled and changed from Vpp to 0V by the capacitor C1 and the resistor R1. Therefore, the current from the node N3 to N1 is controlled by Qp16.

  FIG. 15 is a timing chart showing the write operation of the EEPROM configured as described above. Here, it is assumed that the control gate CG4 is selected. First, the voltages Vm and Vpp are boosted from the power supply voltage Vcc by the booster circuits 14 and 15. The voltage Vpp increases from Vpp1 by Vtp every time the writing / verification is repeated. Signals φwi and φwBi seen in FIG. 12 are selected blocks and are Vpp and 0V, respectively.

  In the write operation, the signal φ4 becomes “L”, the node N1 becomes Vcc, and the control gates CG1 to CG8 of the selected block all become Vcc. At the same time, the selection gate SG1 of the selected block is also set to Vcc, and the bit line BL is set to Vcc only when "1" is written. The selection gate SG2 is set to 0V during the write operation. φ1 becomes “H”, and the control gates CG1 to CG8, the selection gate SG1, and the “1” write bit line BL become Vm. The selected control gate CG4 is raised while being controlled from Vm to Vpp1 over time Δt0 by φ3 becoming “H”. The non-selection control gates CG 1 to 3 and 5 to 8 and the selection gate SG 1 and the “1” write bit line BL remain at Vm. Signals φ1, φ2, φ3, and φ4 relating to unselected control gates are indicated by dotted lines in the figure.

  φ4 becomes “H” and all the control gates CG1 to CG8 become 0V. At this time, the selection gate SG1 is also reset to 0V, and the bit line BL is reset to 0V with a delay.

  Subsequently, a verify operation is performed. The selection control gate CG4 becomes the verify potential VVRFY, and the non-selection control gates CG1 to 3 and 5-8 are set to Vcc with φ4 being "L". The selection gates SG1 and SG2 are also at Vcc. When it is detected that the threshold value of the memory cell to which “0” is to be written exceeds VVRFY, “1” is written during the rewriting operation, and excessive “0” writing is prevented. When it is detected that the threshold value of the memory cell to which “0” is to be written does not exceed VVRFY, “0” is written again during the rewrite operation. In the memory cell to which “1” is to be written, “1” is written again during the rewrite operation.

  In the second and subsequent write operations, after the selection control gate CG4 is charged to Vm, φ2 is output and rapidly charged to the maximum voltage of the selection control gate in the previous write operation. Further, φ3 becomes “H” and is raised while being controlled by Vtp over time Δt. For example, during the second write operation, the voltage is raised while being controlled from Vpp1 to Vpp2 (Vpp2 = Vpp1 + Vtp).

  (Vpp1−Vm) / Δt0 in the first write operation and Vtp / Δt in the second and subsequent write operations are set to be substantially the same value. In the first write operation, the threshold value of the memory cell to be written “0” the fastest is equal to or less than the maximum value of the threshold distribution that should be accommodated after “0” write. The threshold value of the memory cell to be written with 0 ″ is set to shift by ΔVpp (ΔVpp is an increase rate of Vpp, Vtp in this example) (FIG. 16). Therefore, the threshold distribution width after writing “0” is ΔVpp (Vtp in this example).

  The data write operation is repeated when the above write operation and verify operation are repeated, and it is detected that the threshold values of all the memory cells to be written with “0” exceed VVRFY.

  Another embodiment of the control gate driver 11 is shown in FIGS. Here, two Vpp booster circuits A20 and Bpp booster circuit B21 are provided, and their outputs are VppA and VppB, respectively. The fourth switch circuit 22 controls whether or not the output VppA of the Vpp booster circuit A20 is connected to the node N1.

  FIG. 19 is a timing chart showing a write operation. VppA and VppB are the same Vpp1 in the first write operation, and VppB = VppA + ΔVpp after the second write operation. Except for VppA and VppB, it is the same as FIG. In this embodiment, the setting of ΔVpp is easier than in the embodiments shown in FIGS.

  FIG. 20 shows an electron injection method according to the seventh embodiment of the present invention. In this case, three states (data “0”, “1”, “2”) are stored in one memory cell. The Vpp pulse waveform is the same as that shown in FIG. 7, but the voltage applied to the memory cell for writing “2” and the memory cell for writing “1” differs by ΔVppB. In the verify operation, the memory cell to be written “2” does not reach the desired threshold value (VVRFY2), and the memory cell to be written “1” does not reach the desired threshold value (VVRFY1). Are detected, and “2” or “1” additional writing is performed only on those memory cells. At this time, dVpp2 / dt = dVpp1 / dt = ΔVppA, and ΔVppA is made equal to the threshold value change amount dVth / dt of the memory cell.

  As a result, the threshold distribution ΔVth after writing “2” and “1” becomes ΔVppA. ΔVppB is equal to the threshold margin ΔVmarjin between the threshold distributions after writing “2” and “1” plus the threshold distribution width ΔVth (ΔVppB = ΔVth + ΔVmarjin, or ΔVppB = VVRFY2 -VVRFY1). As a result, “2” and “1” writing are independently processed in parallel, and writing is performed at high speed. Naturally, the maximum voltage applied to the tunnel oxide film of the memory cell is minimized.

  Further, in the sense that “2” and “1” writing are independently processed in parallel and writing is performed at a high speed, the Vpp pulse waveform is in any form and the memory cell to be written “2” and the “1” writing It is effective to make a difference of ΔVppB between the voltages applied to the memory cells.

  According to the above gist, the present invention can be similarly implemented in the case of multivalue storage of four or more values. Although the case of electron injection has been described with reference to FIG. 20, the case of electron emission can be similarly implemented by inverting the polarity of the control gate with respect to the p-type well.

  Basically, according to the present invention, the potential change of the floating gate due to electron (hole) injection or emission is gradually increased by Vpp, and the electric field applied to the oxide film portion where the electrons (holes) under the floating gate move. It is characterized by canceling the rise. Therefore, according to this gist, for example, a tunnel between a drain or a source and a floating gate other than the one in which electrons (holes) are injected or emitted by a tunnel current through the entire channel surface as in the embodiment described above. The same effect can be obtained by using current, hot electrons, or hot holes.

FIG. 3 is a diagram showing a structure and an equivalent circuit of a memory cell used in an example of the present invention. The figure which shows the electron injection characteristic by the electron injection system which took in the verify operation | movement in a 1st Example. The figure which shows the electron injection characteristic by the electron injection system which took in the verify operation | movement in a 2nd Example. The figure which shows the threshold value change of the memory cell by the conventional electron injection system which took in the verify operation | movement for every bit in a 2nd Example. The figure which shows the electron injection characteristic by the electron injection system which took in the verify operation | movement for improving controllability of the threshold value of a memory cell more in the 2nd Example. The figure which shows the electron injection characteristic by the electron injection system which took in the verify operation | movement in a 3rd Example. The figure which shows the electron injection characteristic by the electron injection system which took in the verify operation | movement in a 4th Example. The figure which shows the modification of the electron injection system which took in verify operation | movement in a 4th Example. The figure which shows the modification of the electron injection system which took in verify operation | movement in a 4th Example. The figure which shows the figure which shows the memory cell array of the NAND cell type EEPROM in a 5th Example. The figure which shows the structure of the circuit which drives a control gate in a 5th Example. The figure which shows the circuit structure of the control gate driver in a 5th Example. The figure which shows the specific circuit structure of the control gate driver in a 5th Example. The figure which shows the specific structure of the current control circuit in a control gate driver in a 5th Example. FIG. 10 is a timing chart for explaining a write / verify operation in the fifth embodiment. The figure which shows the write-in characteristic of the memory cell in a 5th Example. The figure which shows the structure of the control gate driver in a 6th Example. The figure which shows the specific circuit structure of the control gate driver in a 6th Example. FIG. 10 is a timing chart for explaining a write / verify operation in the sixth embodiment. The figure which shows the electron injection system which took in the verify operation | movement in the 7th Example, and its electron injection characteristic. The figure which shows the electron injection characteristic by the conventional electron injection system. The figure which shows the electron injection characteristic by the conventional system which took in verify operation | movement. The figure which shows the threshold value change of the memory cell by the conventional electron injection system which took in the verify operation | movement for every bit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control gate 2 ... Inter-gate insulating film 3 ... Floating gate 4 ... Tunnel oxide film 5 ... N-type diffusion layer 6 ... P-type well 7 ... N-type substrate 8 ... NAND cell type cell array 9 ... Transfer circuit 10 ... First selection Gate driver 11 ... Control gate driver 12 ... Second selection gate driver 13 ... Booster circuit 14 ... Vm booster circuit 15 ... Vpp booster circuit 16 ... First switch circuit 17 ... Second switch circuit 18 ... Third switch circuit 19 ... Current control Circuit 20 ... Vpp booster circuit A
DESCRIPTION OF SYMBOLS 21 ... Vpp booster circuit B 22 ... 4th switch circuit Qn ... n channel MOS transistor Qp ... n channel MOS transistor QD ... n channel D type MOS transistor I ... CMOS inverter

Claims (6)

A plurality of nonvolatile semiconductor memory cells capable of electrically multi-valued data identification and recording , each comprising a charge storage layer between a semiconductor layer and a control gate ;
Threshold value control means for controlling a threshold value of the memory cell, wherein a voltage pulse is applied between the control gate and the semiconductor layer in order to change the threshold value of the memory cell; And a second step of detecting a threshold value of the memory cell after application of the voltage pulse, and the voltage pulse is subjected to constant voltage fluctuation until the threshold value of the memory cell reaches a desired threshold value. Threshold control means to repeat while increasing by minutes,
With
The initial value of the voltage pulse has a voltage corresponding to the write state to be reached by the corresponding memory cell ,
The first step and the second step are simultaneously performed on the plurality of memory cells, and when each memory cell reaches the desired threshold value, the voltage pulse is independently applied to each memory cell. the nonvolatile semiconductor memory device characterized by stopping the.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage of the write pulse increases stepwise.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage of the write pulse increases linearly with time.   2. The nonvolatile semiconductor memory device according to claim 1, wherein a write state of the memory cell is detected during a period in which the write pulse is not applied.   5. The nonvolatile semiconductor memory device according to claim 4, wherein detection of a write state of the memory cell is omitted a predetermined number of times.   2. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cells are connected in series to form a NAND type memory unit.

Images