JPH07162781A - Digital audio signal reproducing device - Google Patents

Abstract

PURPOSE:To receive and reproduce audio signals transmitted at a transmission rate not in integer multiple relation with the sampling frequency of the audio signals by switching the operations of respective memories at the same point of time as the point of time of ending the data read of the memory for outputting audio data. CONSTITUTION:When audio frame signals are received, a synchronizing signal detection protective circuit 5 outputs frame synchronizing signal detection signals to a data write circuit 6 and sends a write address to a data read circuit 9. When the write address and a data read address are separated for more than a fixed value, the data read circuit 9 resets the read address and performs a read operation. Simultaneously, the operation switching signals of RAMs 14-17 are generated from the read address so as to be the same point of time as the data read ending point of time and the RAMs 14-17 are switched at a prescribed timing. Thereafter, until it is judged that no frame synchronizing signal is detected, the switching operations of the RAMs 14-17 are performed at the timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for high-definition broadcasting or satellite broadcasting, and relates to a digital audio signal reproducing apparatus for reproducing a digital audio signal transmitted together with a video signal.

[0002]

2. Description of the Related Art Hi-vision transmission method is described in Yuichi Ninomiya, MUSE-Hi-vision transmission method (published by The Institute of Electronics, Information and Communication Engineers, December 1, 1990).
In particular, digital audio is described in detail in 4.11 audio system (pages 163 to 184).

FIG. 4 shows the structure of a voice frame. There are two types of audio modes, A mode and B mode. In A mode, differentially encoded audio data for 4 channels with a sampling frequency of 32 kHz is transmitted, and in B mode, differential encoding is performed. The converted audio data for two channels having a sampling frequency of 48 kHz is transmitted.

A voice frame signal having this structure is interleaved, further time-axis compressed, and transmitted. On the receiving side, after expanding the time axis and deinterleaving to reproduce the audio frame signal, error correction and DPCM demodulation are performed to reproduce the audio data.

[0005]

However, the data transmission rate of the digital audio signal transmitted by the broadcast and the sampling frequency (48 kHz) of the audio signal are as described above.
z, 32 kHz) is not in an integral multiple relationship.

An object of the present invention is to receive a digital voice signal transmitted at a transmission rate which is not an integral multiple of the sampling frequency (48 kHz, 32 kHz) of the voice signal,
An object of the present invention is to provide a digital audio signal reproducing device capable of reproducing an audio signal with a simple configuration.

[0007]

SUMMARY OF THE INVENTION The above-mentioned object is to provide a memory for writing an audio frame signal, a memory for performing an error correction process, a memory for descrambling, an audio data according to an audio sampling frequency. A memory for outputting the audio frame signal is detected, and after the frame synchronization signal in the audio frame signal is detected, the end point of the audio data read of the memory for outputting the audio data according to the sampling frequency of the audio is set in the audio frame signal. Within the period of the frame sync signal and the control code, and thereafter, the operation of each memory is switched until the frame sync signal is not detected at the same time as the end of the audio data read of the memory for outputting the audio data. It can be achieved by doing in points.

[0008]

After the frame sync signal in the audio frame signal is detected, the end point of the audio data read from the memory for outputting the audio data in accordance with the audio sampling frequency,
The audio data is read from the memory to output the audio data by switching the operation of each memory until the frame sync signal in the audio frame signal and the control code are within the period, and thereafter the frame sync signal is not detected. By performing at the same time as the end point, the sampling frequency (48 kHz, 32 kHz) of the audio signal is received as a digital audio signal transmitted at a transmission rate that is not an integer multiple
The audio signal can be reproduced with a simple configuration.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows one embodiment of the present invention, which is an example in which the present invention is applied to a high-definition transmission type digital audio reproducing apparatus. 1 is an antenna, 2 is a receiving circuit, 3
Is a time axis expansion circuit, 4 is a deinterleave circuit, 5 is a frame sync signal detection protection circuit, 6 is a data write control circuit, 7 is an error correction circuit, 8 is a descrambling circuit, and 9 is a descrambling circuit.
Is a data read circuit, 10 to 13 are data and address selection circuits, 14 to 17 are RAMs, and 18 is a DPC.
It is an M reproducing circuit. The transmission signal received by the reception circuit 2 has its digital voice portion expanded in time by a time axis expansion circuit 3, and is deinterleaved by a deinterleave circuit 4.
The audio frame signal of the format shown in FIG. 4 is demodulated by being deinterleaved. The audio frame signal is A mode,
Both B modes are made up of 1350 bits per frame, the frame frequency is 1 kHz, and therefore the transmission rate is 1.35 Mbps. On the other hand, the sampling frequency of the audio signal is 32 kHz in the A mode and 48 kHz in the B mode. The sync signal detection protection circuit 5 detects a frame sync signal in the deinterleaved audio frame signal and protects the frame sync signal when an error occurs. The data writing circuit 6 generates an address for writing the audio frame signal in the memory based on the frame synchronization signal detected by the synchronization signal detection protection circuit 5, and writes the audio frame signal in the RAM-1, for example. The voice frame signal written in RAM-1 is
In the next frame, the error correction circuit 7 is connected to correct an error that occurred during transmission. RAM in next frame
-1 is connected to the descramble circuit and descrambled. And finally, in the next frame, RAM-
1 is connected to the data reading circuit, and the audio data is read from the RAM-1 according to the sampling frequency. Since the read audio data is differentially encoded, it is demodulated by the DPCM reproducing circuit 18 into a PCM signal. The operation of other RAMs is similar. Next, the RAM switching timing will be described with reference to FIG. FIG. 2 shows the switching timing of the memory of the present invention and each R
It shows an example of the operation of the AM. The frame sync signal undetected area is used when no audio signal is transmitted,
This shows a case where the receiving circuit is not in the receiving state. When the audio frame signal is received, the sync signal detection protection circuit 5 outputs a frame sync signal detection signal to the data writing circuit. Data writing circuit 6
Sends the write address to the data read circuit 9.
The data read circuit 9 resets the read address and performs a read operation when the write address of the data write circuit 6 and the data read address are separated by a certain value or more. At the same time, the data read circuit 9 generates the operation switching signals of the four RAMs from the read address at the same time as the data read end time,
Each RAM is switched at the timing shown in FIG. Or later,
The switching operation of each RAM is performed at this timing until it is determined that the frame synchronization signal has not been detected. Figure 3
6 shows an example of a more detailed timing of a RAM switching operation according to the present invention. When it is determined that the frame synchronization signal is detected from the state where the frame synchronization signal is not detected, the frame synchronization signal detection signal is generated, and the RAM switching operation is performed within the period in which the frame synchronization signal and the control code are combined. . As described above, according to the present embodiment, by switching the operation of each memory at the same time as the data read end time of the memory for outputting the audio data, the sampling frequency of the audio signal (48 kHz, 32 kHz).
z) is capable of receiving a digital audio signal transmitted at a transmission rate that is not in an integral multiple relationship and reproducing the audio signal with a simple configuration. Since the present embodiment has a simple structure, it is possible to integrate the reproducing portion 100 for reproducing the audio signal from the received digital audio signal in one semiconductor integrated circuit, which leads to the cost reduction of the receiver. ,effective. Further, in the present embodiment, it is determined that the frame synchronization signal is detected when even one of the patterns is detected, but in the undetected state, for example, when the pattern can be detected twice consecutively, it is true. The frame synchronization signal may be determined to be the frame synchronization signal. Next, the RAM of the present invention
The switching means will be described with reference to FIG. Figure 5
Shows one embodiment of the data read circuit. Reference numeral 19 is a counter for generating a data read address, and 20 is an address decoder. Also, 21 is
An address comparison circuit that compares a data write address and a read address. Address comparison circuit 21
Compares the data write address with the read address, and generates a reset signal to the address counter 19 when the values are separated by a certain value or more. As a result,
The read address is modified and the RAM switching signal is also modified. As described above, according to the present embodiment, since the RAM switching means can be configured only by the address comparison circuit, it can be realized with a simple configuration. In addition, when it is configured on a semiconductor integrated circuit, the ratio of the chip area to the chip area is very small, which is particularly advantageous when configuring the audio signal reproducing device with the semiconductor integrated circuit.

[0010]

According to the present invention, a digital voice signal transmitted at a transmission rate that does not have an integral multiple relation with the sampling frequency (48 kHz, 32 kHz) of the voice signal is received, and the voice signal has a simple structure. There is an effect that the signal can be reproduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a digital audio signal reproducing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a memory switching timing and an operation of each memory according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a more detailed timing of a RAM switching operation of the present invention.

FIG. 4 is a diagram showing an audio frame signal.

FIG. 5 is a diagram showing a configuration example of a data read control circuit of the digital audio signal reproducing device according to the embodiment of the invention.

[Explanation of symbols]

 5 ... Sync signal detection protection circuit, 6 ... Data write control circuit, 7 ... Error correction circuit, 8 ... Descramble circuit, 9 ... Data read circuit, 10-13 ... Data and address selection circuit, 14-17 ... Memory (RAM ), 21 ... Address comparison circuit, 100 ... Reproduction part.

Front page continuation (72) Toshifumi Takeuchi Toshifumi Takeuchi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stocks, Hitachi Media Visual Media Research Institute (72) Inventor Hiroaki Takagishi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Stocks Hitachi, Ltd. Semiconductor Division

Claims (4)

[Claims] 1. A playback apparatus for receiving a digital audio signal which is transmitted together with a video signal and in which the transmission rate of the signal and the sampling frequency do not have an integral multiple relationship, and reproduces the audio signal, a frame synchronization signal and a control code. And a plurality of memories for processing a voice frame signal composed of voice data, data independent of voice and an error correction code, and a plurality of memories for performing a plurality of processes for reproducing a voice signal from the voice frame signal. A digital audio signal reproducing device, characterized in that the operation is switched within a period of a frame synchronization signal and a control code in the audio frame signal. 2. The plurality of memories outputs audio data according to a memory for writing an audio frame signal, a memory for error correction processing, a memory for descrambling, and an audio sampling frequency. 2. The digital audio signal reproducing device according to claim 1, wherein the memory for reproducing the audio signal comprises four memories. 3. The switching of the operation of each memory according to claim 1 is for outputting audio data according to the audio sampling frequency according to claim 2 after a frame synchronization signal in the audio frame signal is detected. The end point of reading the data from the memory is controlled to be within the period of the frame synchronization signal and the control code in the audio frame signal, and thereafter,
2. The digital audio signal according to claim 1, wherein the operation of each memory is switched at the same point of time when the reading of the data from the memory for outputting the audio data is completed until the frame synchronization signal is not detected. Playback device. 4. An audio signal is provided by providing four memories, an audio frame signal writing means, an error correction means, a descrambling means, an audio data reading means, and an operation switching means of the four memories. A semiconductor integrated circuit of an audio signal reproducing device characterized by being obtained.