JPH10261268A - Digital signal processing method, recording method using it and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal recording device which can cope with a situation in which length and constitution of a packet are different depending on a form of broadcasting, when a packet different from setting is inputted, byte deviation and data omission occur, and a compressed video signal and a voice signal can not be expansion-processed. SOLUTION: Packet data is inputted to a packet length adjusting counter 104, the number of bytes and bits of packet data is counted, and a counted value is outputted to a packet length uncoincidence detecting circuit 102. Then, the number of bytes sent previously from a microcomputer and the like is compared with an inputted counted value, when they do not coincide, an uncoincidence detection flag is outputted. This uncoincidence detection flag is inputted to a microcomputer and the like, and it is utilized for signal processing afterward.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording device for recording digital video signals, and more particularly to a recording device for recording digital compressed video signals.

[0002]

2. Description of the Related Art Nikkei Electronics 1996.
2 (No. 669), pages 149 to 164, digital broadcasting using satellites has been put to practical use.
As described in this technique, the transmitting side converts a compressed video signal or audio signal into a packet-format digital signal, multiplexes the digital signal in a plurality of channels, and transmits the digital signal. On the receiving side, a high-quality multi-channel program service is realized by selecting only the packets of the selected channel and expanding the video signal and the audio signal.

An object of the present invention is to process a digital signal in a packet format selected on the receiving side and to record and reproduce the digital signal on and from a recording medium. Conventionally, there is no such technique.

[0004]

The length and configuration of the packet selected on the receiving side differ depending on the type of digital broadcasting, and it is necessary to perform appropriate signal processing on each packet. When a packet different from the setting is input, a byte shift, a bit shift, and a loss of data occur, and it becomes impossible to expand a compressed video signal or audio signal. An object of the present invention is to provide a digital signal recording apparatus capable of detecting the occurrence of the above-described problem and coping with the detection.

[0005]

The object of the present invention is to provide a packet length counting means for counting the number of bits per packet of a received digital signal, a packet length mismatch detecting means for detecting a mismatch of a predetermined number of bytes, When the number of bits per packet of the signal is different from the predetermined number of bits, this can be achieved by providing a packet length adjusting unit that adjusts the packet length and outputs a packet, and a recording control unit that controls a recording signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described. FIG. 1 shows a configuration example of a digital signal processing device according to the present invention. FIG.
, 001 is a data bus I / F circuit, 100 is a digital signal input terminal, 101 is a packet length counter,
102 is a packet length mismatch detection circuit, 103 is a packet data extraction circuit, 104 is a packet length adjustment counter, 1
05 is a data deletion / addition circuit, 106 is a mismatch detection flag output terminal, 107 is a packet mode input terminal, 108
Is a data output terminal.

First, the form of a signal input to the digital signal input terminal 100 will be described with reference to FIG. In FIG. 2, 200 is a packet, 201 is time information, 2
02 indicates control information. FIG. 2A is a packet format digital signal in which a compressed video signal, audio signal, or information signal is collected, and packet data 20 is shown.
0. The length of the packet differs depending on the type of digital broadcasting, and is transmitted, for example, in 188 bytes or 140 bytes. The packet configuration also differs depending on the form of the digital broadcast. For example, as shown in FIG. 2B, a packet data 200 may be sent with a 4-byte header provided at the beginning and time information 201 and control information 202 added. As shown in FIG. 2, the length of the packet is various, and it is necessary to perform signal processing corresponding to each packet. If the number of bytes and the configuration of the packets do not match, a byte shift or data loss occurs, making it impossible to decompress the compressed video signal or audio signal.

Next, the operation of FIG. 1 will be described with reference to FIG. The packet data 200 input from the digital signal input terminal 100 as shown in FIG.
3. Input to the packet length adjustment counter 104. In the packet length counter 101, the packet data 20 input from the section (blank) where no packet data exists is input.
The number of bytes and the number of bits of 0 are counted, and the count value up to the next blank is output to the packet length mismatch detection circuit 102 as shown in FIG. In the packet length mismatch detection circuit 102, a packet mode previously sent from a microcomputer or the like is input from the packet mode input terminal 107, and the number of bytes corresponding to the packet mode, for example, 188 bytes is set. The set 188 bytes are compared with the input count value.
The mismatch detection flag is output from the mismatch detection flag output terminal 106 as shown in FIG. This mismatch detection flag is
The data is input to a microcomputer and used for changing the packet mode and for subsequent signal processing.

The packet data conversion circuit 103 converts the input packet data into a format that can be easily processed inside the signal processing. For example, the packet data 200 is input in a 1-bit serial data format that is easy to wire, and is converted into 16-bit bus format data by the packet data conversion circuit 103. Conversion to a 16-bit bus is advantageous in terms of processing speed.

The packet length adjustment counter 104 counts the number of bytes set in advance from a microcomputer or the like from the packet mode input terminal 107 in synchronization with the input packet data 200, and the data deletion / addition circuit 105 uses the packet data conversion circuit 105. Gate the output of 103. As a result, even when the number of bytes of the packet data 200 does not match, the data deletion / addition circuit 105 deletes the data and adds dummy data as a result, and sets the bytes set as shown in FIG. The number is output from the data output terminal 108.

Here, the operation when the mismatch detection flag is detected will be described with reference to the flowcharts of FIGS. FIG. 4 illustrates the operation described with reference to FIG. At step 402, the number of bytes of the packet is counted. At step 403, a blank is detected. At this time, at step 405, comparison is made with the set value set in the packet mode. When the value does not match the set value, the mismatch detection flag is set to 1, and when the value matches, the value is reset to 0. FIG. 5 illustrates an operation when a mismatch detection flag is detected. In step 501, packet data is fetched, and in step 503, the packet length is confirmed. Step 50
If the mismatch detection flag is set to 1 and a mismatch is detected in step 4, the packet mode is changed in step 505 to change the set value. For example, when a mismatch is detected at 188 bytes, the mode is changed to the 140 byte mode, and the mismatch detection flag is checked again. By repeating this several times, the number of bytes of the packet data 200 can be matched. Further, assuming that a mismatch detection flag is temporarily detected due to noise or the like, the packet mode may be changed on the condition that two or more packets are continuously detected or detected again after a predetermined period. . Even when a mismatch is temporarily detected, data of a fixed number of bytes is always output by the packet length adjustment counter 104, so that occurrence of byte shift, bit shift, and the like in subsequent signal processing can be prevented.

As described above, according to the first embodiment, since the packet mode of the signal processing circuit can be made to match the length and configuration of the transmitted packet, the subsequent error correction processing and decompression processing are performed. And so on can be prevented from malfunctioning in signal processing.

Next, a description will be given of a second embodiment in which the present invention is applied to a digital signal recording / reproducing apparatus shared with analog signal recording / reproducing. FIG. 6 shows a configuration example of a digital signal recording / reproducing apparatus according to the present invention. In FIG. 6, 601 is a data input / output terminal, 602 is a buffer RAM, 603 is a recording / reproducing signal processing circuit, 604 is a microcomputer, 605 is a digital recording control circuit, 605 is a servo circuit, 607 is a capstan, 608 is a magnetic tape, 609 is a cylinder, 610 is an analog recording control circuit, 611 is an analog signal recording / reproducing circuit, 612 is an analog input terminal, and 613 is an analog output terminal. Next, the operation will be described.
The operation of the data bus I / F circuit 001 is similar to that of the first embodiment. The number of bytes according to the packet mode set by the microcomputer 604 is compared with the number of bytes of the packet data 200, and the comparison result is output to the microcomputer 604 as a flag. When the microcomputer 604 detects a mismatch, the packet mode is changed and the input packet data 200 is changed.
And the packet mode of the data bus I / F circuit 001 are matched. The data whose packet length is adjusted by the data bus I / F circuit 001 and converted into the bus format is once written in the buffer RAM 602. This is because the packet data 200 from the data input / output terminal 601 is input in a burst manner, but when it is recorded on a magnetic tape, it must be recorded at a constant rate. Buffer RAM
The data written in 602 is a read / write signal processing circuit 60.
The data is read out at a constant rate in step 3, and several packets are bundled at regular time intervals, and an error correction code is added thereto and modulation processing is performed to generate recording data. Here, if signal processing is performed with the packet length mismatching, the packet length is adjusted so that the beginning does not shift, but recording is performed with part of the packet data deleted or dummy data added. Therefore, the original packet cannot be reproduced when reproduced. The generated recording data is controlled by a digital recording control circuit 605 by a microcomputer 604 to start or stop recording. The digital recording control circuit 605 controls recording data and a recording amplifier. Here, the processing operation of the microcomputer 604 from the start of recording will be described with reference to FIG. First, before the start of recording, a mode change process is performed in step 701 to match the configuration and length of the packet data 200 with the packet mode. Here, the case where there is no matching packet mode is detected in step 707, and when the packet modes do not match, digital recording stop processing is performed in step 705. Recording is started in step 702, and the length of the packet is checked in step 703 while recording. Step 7
If no mismatch in packet length is detected in step 04, the recording is continued. If a mismatch is detected, digital recording stop processing of step 705 is performed to stop digital recording. In the digital recording stop processing of step 705, the digital recording control circuit 605 of FIG. 6 is controlled to gate the recording data, the recording amplifier is stopped, and the servo circuit 606 is controlled to stop the tape running. Here, when a mismatch is detected, the analog recording control 610 does not stop running the tape.
May be switched to a mode for recording an analog signal. Alternatively, the running of the tape is stopped, and step 701 is executed.
The detection may be continued until the packet mode matches any of the packet modes, and the recording may be resumed after the packet mode matches.

As described above, when the packet data 200 is input, the mismatch of the packet length can be detected. Therefore, before reading the data from the recording / reproducing signal processing circuit 603 and outputting the recording data, the recording data is read out. It can be controlled and erroneous recording data is not recorded.

Although the magnetic tape is used as the recording medium in the second embodiment, similar effects can be obtained in other recording media such as an optical disk. Although the first embodiment is an apparatus for both recording and reproduction, the same is true even when signal processing for recording and reproduction is independent.

FIG. 8 shows an example of connection between the digital signal recording / reproducing apparatus of the present embodiment and a digital broadcast receiver. 002 is a digital signal recording / reproducing apparatus of this embodiment,
801 is a digital broadcast receiver, 802 is an antenna, 8
Reference numeral 07 denotes a receiver. 803 is a tuner, 804
Is a program selection circuit, 805 is a decoding circuit, and 806 is an interface circuit.

After the digital broadcast signal received by the antenna 802 is demodulated by the tuner 803, the program selection circuit 804 selects a digital compressed video signal of a specified program. The selected compressed digital video signal is decoded into a normal video signal by the decoding circuit 805 and output to the receiver 806. When the received signal is subjected to a process such as scrambling, the decoding process is performed after the selection signal 804 or the decoding circuit 805 cancels it. At the time of normal reception, the digital broadcast receiver 801 demodulates the compressed digital signal from the received signal, and decodes the compressed digital signal into a normal video signal and an audio signal by a decoding circuit 805 to receive an image on a television or the like. Device 807. This digital compressed signal is
It is usually transmitted in a packet format, and the transmission rate of the packet varies depending on the content of the broadcast. The packet transmission interval also changes according to the encoding process. The decoding circuit 805 decodes the video signal by reproducing the frame frequency at the time of encoding from the information included in the data in the packet format and the interval at which the packet is transmitted.

At the time of recording from the digital broadcast receiver 801, the interface circuit 806 operates as shown in FIG.
Alternatively, the packet data shown in (b) is output. Thereafter, the digital signal is input from the input terminal 111 to the digital signal recording / reproducing apparatus 002, and is recorded by performing the above-described processing while confirming the coincidence of the packets. Also, even when a packet mismatch is detected, the digital signal recording / reproducing device 002 is also connected from the analog input / output terminal 612 to the output of the decoding circuit 805, and can switch to and record an analog video signal.

Although the above embodiment has been described for the case of recording and reproducing a digital compressed video signal, the same effect can be obtained when recording and reproducing other digital signals.

[0021]

According to the digital signal processing method of the present invention, even when the digital signal of the packet format input at the time of recording is different from the set packet length, this can be detected, and the packet modes can be matched. .
Further, since the packet length is adjusted and output, even if a temporary mismatch in the number of bytes or bits is detected, it is possible to prevent a byte shift or a bit shift in subsequent signal processing.

Further, according to the digital signal recording method of the present invention, the mismatch can be detected before the detected data is recorded, so that the recording signal can be controlled to record erroneous recording data. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of Embodiment 1 of a digital signal processing device of the present invention.

FIG. 2 is an example of packet data.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is a flowchart showing the operation of the first embodiment.

FIG. 5 is a flowchart showing an operation of the first embodiment.

FIG. 6 is a configuration diagram of a digital signal recording / reproducing apparatus according to a second embodiment of the present invention.

FIG. 7 is a flowchart illustrating the operation of the second embodiment.

FIG. 8 is a diagram showing an example of a connection between the digital signal recording / reproducing device of the present invention and a digital broadcast receiver.

[Explanation of symbols]

001: Data bus I / F circuit, 100: Digital signal input terminal, 101: Packet length counter, 102: Packet length mismatch detection circuit, 103: Packet data extraction circuit, 104: Packet length adjustment counter, 105: Data deletion / addition Circuit, 106: mismatch detection flag output terminal, 107: packet mode input terminal, 108: data output terminal, 200: packet, 201: time information, 20
2. Control information, 601 Data input / output terminal, 602 Buffer RAM, 603 Recording / reproducing signal processing circuit, 604
... microcomputer, 605 ... digital recording control circuit, 606
... Servo circuit, 607 ... Capstan, 608 ... Magnetic tape, 609 ... Cylinder, 610 ... Analog recording control circuit, 611 ... Analog signal recording / reproducing circuit, 612 ... Analog input / output terminal, 801 ... Digital broadcasting receiver, 80
2 ... antenna, 807 ... receiver, 803 ... tuner, 8
04: Program selection circuit, 805: Decoding circuit, 806
... Interface circuit.

Continued on the front page (72) Inventor Yasunori Ohara 1410 Inada, Hitachinaka-city, Ibaraki Pref. Hitachi, Ltd. Visual Information Media Division

Claims (9)

[Claims] 1. A digital signal processing method for receiving a digital signal transmitted in a packet format having a predetermined number of bits, wherein the number of bits per packet of the input digital signal is counted. A digital signal processing method comprising detecting a mismatch in the number of bits and outputting a result. 2. When the number of bits per packet of the digital signal is smaller than the predetermined number of bits, dummy data is added to the digital signal so as to have the predetermined number of bits. 2. The digital signal processing method according to claim 1, wherein when the number of bits is larger than the predetermined number of bits, the digital signal is deleted so as to have the predetermined number of bits, and a packet length is adjusted. 3. The digital signal processing method according to claim 1, wherein when a mismatch between the digital signal and the predetermined number of bits is detected, the predetermined number of bits is changed. 4. The digital signal processing method according to claim 1, wherein when a mismatch between the digital signal and the predetermined number of bits is continuously detected for two or more packets, the predetermined number of bits is changed. 5. A digital signal recording method for receiving a digital signal transmitted in a packet format having a predetermined number of bits and recording the digital signal on a recording medium, wherein the number of bits per packet of the input digital signal is counted. A digital signal recording method, comprising detecting a mismatch between a count result and the predetermined number of bits and outputting the result. 6. The digital signal recording method according to claim 5, wherein control is performed to stop recording or not start recording when a mismatch is detected. 7. A digital signal recording apparatus for receiving a digital signal transmitted in a packet format having a predetermined number of bits and recording the digital signal on a recording medium, wherein a packet length for counting the number of bits per packet of the received digital signal. A digital signal recording apparatus, comprising: counting means; and packet length mismatch detecting means for detecting a mismatch between the result of the packet length counting means and the predetermined number of bits and outputting the result. 8. The digital recording apparatus according to claim 7, further comprising recording control means for controlling not to stop recording or to start recording when a mismatch is detected by said packet length mismatch detecting means. Signal recording device. 9. When the number of bits per packet of the digital signal is smaller than the predetermined number of bits, dummy data is added to the digital signal so that the number of bits is equal to the predetermined number of bits. 8. The apparatus according to claim 7, further comprising a packet length adjusting means for deleting the digital signal so as to have the predetermined number of bits when the number of bits is larger than the predetermined number of bits, and outputting a packet whose packet length has been adjusted. 2. The digital signal recording device according to claim 1.